Patent application number | Description | Published |
20090302417 | STRUCTURE AND METHOD TO FORM DUAL SILICIDE E-FUSE - An e-fuse structure and method has anode, a fuse link, and a cathode. The first end of the fuse link is connected to the anode and the second end of the fuse link opposite the first end is connected to the cathode. This structure also includes a first silicide layer on the anode and the fuse link and a second silicide layer, different than the first silicide layer, on the cathode. The difference between the first silicide layer and the second silicide layer causes an enhanced flux divergence region at the second end of the fuse link. | 12-10-2009 |
20090309184 | STRUCTURE AND METHOD TO FORM E-FUSE WITH ENHANCED CURRENT CROWDING - An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region. | 12-17-2009 |
20110230030 | STRAIN-PRESERVING ION IMPLANTATION METHODS - An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized. | 09-22-2011 |
20120028430 | METHOD AND STRUCTURE TO IMPROVE FORMATION OF SILICIDE - A method begins with a structure having: a gate insulator on a silicon substrate between a gate conductor and a channel region within the substrate; insulating sidewall spacers on sidewalls of the gate conductor; and source and drain regions within the substrate adjacent the channel region. To silicide the gate and source and drain regions, the method deposits a metallic material over the substrate, the gate conductor, and the sidewalls, and performs a first heating process to change the metallic material into a metal-rich silicide at locations where the metallic material contacts silicon. The method removes the sidewall spacers, and performs a second heating process to change the metal-rich silicide into silicide having a lower metallic concentration than the metal-rich silicide. The silicide thus formed avoids being damaged by the spacer removal process. | 02-02-2012 |
20120098042 | SEMICONDUCTOR DEVICE WITH REDUCED JUNCTION LEAKAGE AND AN ASSOCIATED METHOD OF FORMING SUCH A SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity. | 04-26-2012 |
20120112292 | INTERMIXED SILICIDE FOR REDUCTION OF EXTERNAL RESISTANCE IN INTEGRATED CIRCUIT DEVICES - A method for forming an alternate conductive path in semiconductor devices includes forming a silicided contact in a source/drain region adjacent to an extension diffusion region and removing sidewall spacers from a gate structure. A metal layer is formed over a portion of the extension diffusion region in a substrate layer to intermix metal from the metal layer with the portion of the extension region without annealing the metal layer. An unmixed portion of the metal layer is removed. The alternate conductive path is formed on the extension diffusion region with intermixed metal by thermal processing after the unmixed portion of the metal layer has been removed. | 05-10-2012 |
20120181697 | METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE - A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm. | 07-19-2012 |
20120187460 | METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES - A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy. | 07-26-2012 |
20120190192 | Metal-Semiconductor Intermixed Regions - In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure. | 07-26-2012 |
20120214301 | STRUCTURE AND METHOD TO FORM E-FUSE WITH ENHANCED CURRENT CROWDING - An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region. | 08-23-2012 |
20120292670 | Post-Silicide Process and Structure For Stressed Liner Integration - A method of fabricating a semiconductor device and a corresponding semiconductor device are provided. The method can include implanting a species into a silicide region, the silicide region contacting a semiconductor region of a substrate. A stressed liner may then be formed overlying the silicide region having the implanted species therein. In a particular example, prior to forming the stressed liner, a step of annealing can be performed within an interval less than one second to elevate at least a portion of the silicide region to a peak temperature ranging from 800 to 950° C. The method may reduce the chance of deterioration in the silicide region, e.g., the risk of void formation, due to processing used to form the stressed liner. | 11-22-2012 |
20120295439 | Metal-Semiconductor Intermixed Regions - In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure. | 11-22-2012 |
20130020616 | SILICIDED DEVICE WITH SHALLOW IMPURITY REGIONS AT INTERFACE BETWEEN SILICIDE AND STRESSED LINER - A method of forming a semiconductor device includes forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region. | 01-24-2013 |
20130069124 | MOSFET INTEGRATED CIRCUIT WITH UNIFORMLY THIN SILICIDE LAYER AND METHODS FOR ITS MANUFACTURE - An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches. | 03-21-2013 |
20130127058 | LINER-FREE TUNGSTEN CONTACT - A liner-less tungsten contact is formed on a nickel-tungsten silicide with a tungsten rich surface. A tungsten-containing layer is formed using tungsten-containing fluorine-free precursors. The tungsten-containing layer may act as a glue layer for a subsequent nucleation layer or as the nucleation layer. The tungsten plug is formed by standard processes. The result is a liner-less tungsten contact with low resistivity. | 05-23-2013 |
20130137260 | MULTI-STAGE SILICIDATION PROCESS - A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices. | 05-30-2013 |
20130149865 | METHOD AND STRUCTURE FOR DIFFERENTIAL SILICIDE AND RECESSED OR RAISED SOURCE/DRAIN TO IMPROVE FIELD EFFECT TRANSISTOR - A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc. | 06-13-2013 |
20130175632 | REDUCTION OF CONTACT RESISTANCE AND JUNCTION LEAKAGE - A time clock clearly identifies where a user should position a time card therein. The clock and a printer platen are fixed relative to a base, and has the time card rests thereon. A printing mechanism moves relative to the base and has a target area, it is traversable between a print position and an idle position, and it impresses the time indicia onto the time card while in the print position. A ribbon shield is fixed relative to the base. A focused illuminated guide is fixed relative to the base, and in combination with the ribbon shield, guides the time card with respect to the printing mechanism to clearly identify where the user should position the time card in the time clock. | 07-11-2013 |
20130267090 | METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE - A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm. | 10-10-2013 |
20140073130 | FORMING NICKEL-PLATINUM ALLOY SELF-ALIGNED SILICIDE CONTACTS - A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO | 03-13-2014 |
20140154856 | Inducing Channel Strain via Encapsulated Silicide Formation - Methods of forming semiconductor structures having channel regions strained by encapsulated silicide formation. Embodiments include forming a transistor, depositing an interlevel dielectric (ILD) layer above the transistor, forming contact recesses exposing portions of source/drain regions of the transistor, forming metal-rich silicide layers on the exposed portions of the source/drain regions, forming metal contacts in the contact recesses above the metal-rich silicide layers, and converting the metal-rich silicide layer to a silicon-rich silicide layer. In other embodiments, the metal-rich silicide layers are formed on the source/drain regions prior to ILD layer deposition. Embodiments further include forming a transistor, depositing an ILD layer above the transistor, forming contact recesses exposing portions of source/drain regions of the transistor, forming metal liners in the contact recesses, forming metal fills in the contact recesses, and forming silicide layers on the source/drain regions by reacting portions of the metal liners with portions of the source/drain regions. | 06-05-2014 |
20140210011 | Dual Silicide Process - In one aspect, a method for silicidation includes the steps of: (a) providing a wafer having at least one first active area and at least one second active area defined therein; (b) masking the first active area with a first hardmask; (c) doping the second active area; (d) forming a silicide in the second active area, wherein the first hardmask serves to mask the first active area during both the doping step (c) and the forming step (d); (e) removing the first hardmask; (f) masking the second active area with a second hardmask; (g) doping the first active area; (h) forming a silicide in the first active area, wherein the second hardmask serves to mask the second active area during both the doping step (g) and the forming step (h); and (i) removing the second hardmask. | 07-31-2014 |
20140306290 | Dual Silicide Process Compatible with Replacement-Metal-Gate - In one aspect, a method for fabricating an electronic device includes the following steps. A wafer is provided having at least one first active area and at least one second active area defined therein. One or more p-FET/n-FET devices are formed in the active areas, each having a p-FET/n-FET gate stack and p-FET/n-FET source and drain regions. A self-aligned silicide is formed in each of the p-FET/n-FET source and drain regions, wherein the self-aligned silicide in each of the p-FET source and drain regions has a thickness T1 and the self-aligned silicide in each of the n-FET source and drain regions having a thickness T2, wherein T1 is less than T2. During a subsequent trench silicidation in the p-FET/n-FET source and drain regions, the trench silicide metal will diffuse through the thinner self-aligned silicide in the p-FET device(s) but not through the thicker self-aligned silicide in the n-FET device(s). | 10-16-2014 |
20140306291 | Dual Silicide Process Compatible with Replacement-Metal-Gate - In one aspect, a method for fabricating an electronic device includes the following steps. A wafer is provided having at least one first active area and at least one second active area defined therein. One or more p-FET/n-FET devices are formed in the active areas, each having a p-FET/n-FET gate stack and p-FET/n-FET source and drain regions. A self-aligned silicide is formed in each of the p-FET/n-FET source and drain regions, wherein the self-aligned silicide in each of the p-FET source and drain regions has a thickness T1 and the self-aligned silicide in each of the n-FET source and drain regions having a thickness T2, wherein T1 is less than T2. During a subsequent trench silicidation in the p-FET/n-FET source and drain regions, the trench silicide metal will diffuse through the thinner self-aligned silicide in the p-FET device(s) but not through the thicker self-aligned silicide in the n-FET device(s). | 10-16-2014 |
20140374844 | METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES - A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy. | 12-25-2014 |
20150044845 | METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES - A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy. | 02-12-2015 |
20150076607 | FIN FIELD EFFECT TRANSISTOR WITH MERGED METAL SEMICONDUCTOR ALLOY REGIONS - Raised active regions having faceted semiconductor surfaces are formed on semiconductor fins by selective epitaxy such that the raised active regions are not merged among one another, but are proximal to one another by a distance less than a thickness of a metal semiconductor alloy region to be subsequently formed. A contiguous metal semiconductor alloy region is formed by depositing and reacting a metallic material with the semiconductor material of raised active regions. The contiguous metal semiconductor alloy region is in contact with angled surfaces of the plurality of raised active regions, and can provide a greater contact area and lower parasitic contact resistance than a semiconductor structure including merged semiconductor fins of comparable sizes. Merged fins enable smaller, and/or fewer, contact via structures than a total number of raised active regions can be employed to reduce parasitic capacitance between a gate electrode and the contact via structures. | 03-19-2015 |
20150079751 | FIN FIELD EFFECT TRANSISTOR WITH MERGED METAL SEMICONDUCTOR ALLOY REGIONS - Raised active regions having faceted semiconductor surfaces are formed on semiconductor fins by selective epitaxy such that the raised active regions are not merged among one another, but are proximal to one another by a distance less than a thickness of a metal semiconductor alloy region to be subsequently formed. A contiguous metal semiconductor alloy region is formed by depositing and reacting a metallic material with the semiconductor material of raised active regions. The contiguous metal semiconductor alloy region is in contact with angled surfaces of the plurality of raised active regions, and can provide a greater contact area and lower parasitic contact resistance than a semiconductor structure including merged semiconductor fins of comparable sizes. Merged fins enable smaller, and/or fewer, contact via structures than a total number of raised active regions can be employed to reduce parasitic capacitance between a gate electrode and the contact via structures. | 03-19-2015 |
20150221740 | METAL SEMICONDUCTOR ALLOY CONTACT RESISTANCE IMPROVEMENT - Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. A first transition metal liner including at least one first transition metal element, a second transition metal liner including at least one second transition metal element that is different from the at least one first transition metal element and a metal contact are sequentially formed within each contact opening. Following a planarization process, the structure is annealed forming metal semiconductor alloy contacts at the bottom of each contact opening. Each metal semiconductor alloy contact that is formed includes the at least one first transition metal element, the at least one second transition metal element and a semiconductor element. | 08-06-2015 |
20150228745 | SELF-ALIGNED LINER FORMED ON METAL SEMICONDUCTOR ALLOY CONTACTS - Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact. Each transition metal-metal semiconductor alloy liner that is provided has outer edges that are vertically coincident with outer edges of each metal semiconductor alloy contact. The transition metal-metal semiconductor alloy liner is more etch resistant as compared to the underlying metal semiconductor alloy. As such, the transition metal-metal semiconductor alloy liner can serve as an effective etch stop layer during any subsequently performed etch process. | 08-13-2015 |
Patent application number | Description | Published |
20100296093 | APPARATUS AND METHODS USING HOLLOW-CORE FIBER TAPERS - An optical device and methods of using an optical device are provided. The optical device includes a hollow-core fiber including a first portion and a second portion. The first portion includes a hollow core having a first diameter. The second portion includes a hollow core having a second diameter smaller than the first diameter. The difference between the first diameter and the second diameter is less than 10% of the first diameter. | 11-25-2010 |
20110273712 | APPARATUS AND METHODS USING HOLLOW-CORE FIBER TAPERS - An optical device and methods of using an optical device are provided. The optical device includes a hollow-core fiber including a first portion and a second portion. The first portion includes a hollow core having a first diameter. The second portion includes a hollow core having a second diameter smaller than the first diameter. The difference between the first diameter and the second diameter is less than 10% of the first diameter. | 11-10-2011 |
20120063664 | INERTIAL PARTICLE FOCUSING FLOW CYTOMETER - A flow cytometry system includes an inertial particle focusing device including a plurality of substantially parallel microchannels formed in a substrate, each microchannel having a width to height ratio in the range of 2:3 to 1:4, an analyzer disposed adjacent the inertial particle focusing device such that the analyzer is configured to detect a characteristic of particles in the inertial particle focusing device, and a controller connected to the analyzer and configured to direct the detection of the characteristic of the particles. | 03-15-2012 |
20120148141 | COMPACT AUTOMATED SEMEN ANALYSIS PLATFORM USING LENS-FREE ON-CHIP MICROSCOPY - A compact and light-weight lens-free platform to conduct automated semen analysis is disclosed. The device employs holographic on-chip imaging and does not require any lenses, lasers or other bulky optical components to achieve phase and amplitude imaging of sperm a relatively large field-of-view with an effective numerical aperture of approximately 0.2. A series of digital image frames is obtained of the sample. Digital subtraction of the consecutive lens-free frames, followed by processing of the reconstructed phase images, enables automated quantification of the count, the speed and the dynamic trajectories of motile sperm, while summation of the same frames permits counting of immotile sperm. | 06-14-2012 |
20120157160 | COMPACT WIDE-FIELD FLUORESCENT IMAGING ON A MOBILE DEVICE - Wide-field fluorescent imaging on a mobile device having a camera is accomplished with a compact, light-weight and inexpensive optical components that are mechanically secured to the mobile device in a removable housing. Battery powered light-emitting diodes (LEDs) contained in the housing pump the sample of interest from the side using butt-coupling, where the pump light is guided within the sample holder to uniformly excite the specimen. The fluorescent emission from the sample is then imaged using an additional lens that is positioned adjacent to the existing lens of the mobile device. A color filter is sufficient to create the dark-field background required for fluorescent imaging, without the need for expensive thin-film interference filters. | 06-21-2012 |
20120218379 | INCOHERENT LENSFREE CELL HOLOGRAPHY AND MICROSCOPY ON A CHIP - A system for imaging a cytological sample includes a sample holder configured to hold a cytological sample. A spatial filter is disposed at a distance z | 08-30-2012 |
20120248292 | LENS-FREE WIDE-FIELD SUPER-RESOLUTION IMAGING DEVICE - A system for imaging objects within a sample includes an image sensor and a sample holder configured to hold the sample, the sample holder disposed adjacent to the image sensor. The system further includes an illumination source configured to scan in two or three dimensions relative to the sensor array and illuminate the sample at a plurality of different locations. The illumination source may include, by way of example, LEDs, laser diodes, or even a screen or display from a portable electronic device. The system includes least one processor configured to reconstruct an image of the sample based on the images obtained from illumination source at the plurality of different scan positions. | 10-04-2012 |
20130157351 | COMPACT WIDE-FIELD FLUORESCENT IMAGING ON A MOBILE DEVICE - Wide-field fluorescent imaging on a mobile device having a camera is accomplished with a compact, light-weight and inexpensive optical components that are mechanically secured to the mobile device in a removable housing. Battery powered light-emitting diodes (LEDs) contained in the housing pump the sample of interest from the side using butt-coupling, where the pump light is guided within the sample holder to uniformly excite the specimen. The fluorescent emission from the sample is then imaged using an additional lens that is positioned adjacent to the existing lens of the mobile device. A color filter is sufficient to create the dark-field background required for fluorescent imaging, without the need for expensive thin-film interference filters. | 06-20-2013 |
20130193544 | MICROSCOPY METHOD AND SYSTEM INCORPORATING NANOFEATURES - A lensfree imaging and sensing device includes an image sensor comprising an array of pixels and a substantially optically transparent layer disposed above the image sensor. Nano-sized features that support surface plasmon waves are populated on the substantially optically transparent layer separating the image sensor from the nano-sized features. The nano-sized features may include apertures through a substantially optically opaque layer (e.g., metal layer) or they may include antennas. An illumination source is provided that is configured to illuminate a sample. At least one processor is operatively coupled to the image sensor. Changes to the detected transmission pattern at the image sensor are used to sense conditions at or near the surface containing the nano-sized features. Conditions may include binding events or other changes to the index of refraction occurring near the surface of the device. | 08-01-2013 |
20130203043 | PORTABLE RAPID DIAGNOSTIC TEST READER - A portable rapid diagnostic test reader system includes a mobile phone having a camera and one or more processors contained within the mobile phone and a modular housing configured to mount to the mobile phone. The modular housing including a receptacle configured to receive a sample tray holding a rapid diagnostic test. At least one illumination source is disposed in the modular housing and located on one side of the rapid diagnostic test. An optical demagnifier is disposed in the modular housing interposed between the rapid diagnostic test and the mobile phone camera. | 08-08-2013 |
20130258091 | METHOD AND DEVICE FOR HOLOGRAPHIC OPTO-FLUIDIC MICROSCOPY - A method and system of imaging a moving object within a microfluidic environment includes illuminating a first side of a flow cell configured to carry the moving object within a flow of carrier fluid with an illumination source emitting at least partially coherent light, the at least partially coherent light passing through an aperture prior to illuminating the flow cell. A plurality of lower resolution frame images of the moving object are acquired with an image sensor disposed on an opposing side of the flow cell, wherein the image sensor is angled relative to a direction of flow of the moving object within the carrier fluid. A higher resolution image is reconstructed of the moving object based at least in part on the plurality of lower resolution frame images. | 10-03-2013 |
20130280752 | LENS-FREE TOMOGRAPHIC IMAGING DEVICES AND METHODS - A system for three dimensional imaging of an object contained within a sample includes an image sensor, a sample holder configured to hold the sample, the sample holder disposed adjacent to the image sensor, and an illumination source comprising partially coherent light. The illumination source is configured to illuminate the sample through at least one of an aperture, fiber-optic cable, or optical waveguide interposed between the illumination source and the sample holder, wherein the illumination source is configured to illuminate the sample through a plurality of different angles. | 10-24-2013 |
20140120563 | ALLERGEN TESTING PLATFORM FOR USE WITH MOBILE ELECTRONIC DEVICES - An allergy testing system for use with a mobile electronic device having a camera includes a housing that can be attached to the mobile electronic device. First and second light sources within the housing are configured to illuminate, respectively, a test sample and a control sample. A colorimetric assay is performed on the test sample and the control sample. The first light source and the second light source are activated and the camera of the mobile electronic device captures images of transmitted light. The relative intensity of transmitted light is then used by software loaded on the mobile electronic device to determine a relative absorbance value. The relative absorbance value is used, together with a calibration curve, to measure the concentration of a particular allergen within the test sample. Based on the concentration of the allergen the test sample can be labeled as either “positive” or “negative.” | 05-01-2014 |
20140160236 | LENSFREE HOLOGRAPHIC MICROSCOPY USING WETTING FILMS - A method of imaging a sample includes forming a monolayer wetting layer over a sample containing objects therein. A plurality of lower resolution images are obtained of the sample interposed between an illumination source and an image sensor, wherein each lower resolution image is obtained at discrete spatial locations. The plurality of lower resolution images of the sample are converted into a higher resolution image. One or more of an amplitude image and a phase image are reconstructed of the objects contained within the sample. | 06-12-2014 |
20140300696 | MASKLESS IMAGING OF DENSE SAMPLES USING MULTI-HEIGHT LENSFREE MICROSCOPE - A method of imaging includes illuminating a sample spaced apart from an image sensor at a multiple distances. Image frames of the sample obtained at each distance are registered to one another and lost phase information from the registered higher resolution image frames is iteratively recovered. Amplitude and/or phase images of the sample are reconstructed based at least in part on the recovered lost phase information. | 10-09-2014 |
20150111201 | PORTABLE RAPID DIAGNOSTIC TEST READER AND METHODS OF USING THE SAME - A portable rapid diagnostic test reader system includes a mobile phone having a camera and one or more processors contained within the mobile phone and a modular housing configured to mount to the mobile phone. The modular housing including a receptacle configured to receive a sample tray holding a rapid diagnostic test. At least one illumination source is disposed in the modular housing and located on one side of the rapid diagnostic test. An optical demagnifier is disposed in the modular housing interposed between the rapid diagnostic test and the mobile phone camera. | 04-23-2015 |
20150153558 | WIDE-FIELD MICROSCOPY USING SELF-ASSEMBLED LIQUID LENSES - A method of imaging a sample includes depositing a droplet containing the sample on a substrate, the sample having a plurality of particles contained within a fluid. The substrate is then tilted to gravitationally drive the droplet to an edge of the substrate while forming a dispersed monolayer of particles having liquid lenses surrounding the particles. A plurality of lower resolution images of the particles contained on the substrate are obtained, wherein the substrate is interposed between an illumination source and an image sensor, wherein each lower resolution image is obtained at discrete spatial locations. The plurality of lower resolution images of the particles are converted into a higher resolution image. At least one of an amplitude image and a phase image of the particles contained within the sample is then reconstructed. In some embodiments, only a single lower resolution image may be sufficient. | 06-04-2015 |