Patent application number | Description | Published |
20080292285 | Data Processing Device, Data Processing Method, Program, Program Recording Medium, Data Recording Medium, and Data Structure - The present invention relates to a data processing apparatus, a data processing method, a program, a prgram recording medium, a data recording medium, and a data structure that enable reading of coded video data in access units withour analyyzing the coded video data. In step S | 11-27-2008 |
20090142043 | DATA PROCESSING DEVICE, DATA PROCESSING METHOD, PROGRAM, PROGRAM RECORDING MEDIUM, DATA RECORDING MEDIUM, AND DATA STRUCTURE - A data reproducing apparatus, which is capable of reproducing stream data according to time stamps without need to have an independent time counting clock. At step S | 06-04-2009 |
20090168866 | ENCODING DEVICE, METHOD, AND PROGRAM - Pictures can be encoded such that no display wait occurs or a decoding side. Pictures are re-encoded such that their encoding order is changed. As a result, picture B | 07-02-2009 |
20090169183 | DATA RECORDING DEVICE, DATA RECORDING METHOD, DATA PROCESSING DEVICE, DATA PROCESSING METHOD, PROGRAM, PROGRAM RECORDING MEDIUM, DATA RECORDING MEDIUM, AND DATA STRUCTURE - To effectively reproduce video depending on the performance of a reproducing apparatus. A controller | 07-02-2009 |
20090279867 | REPRODUCING APPARATUS, REPRODUCING METHOD, REPRODUCING PROGRAM, RECORDING MEDIUM, AND DATA STRUCTURE - A state transition of a player operation is explicitly defined to facilitate the production of interactive contents. As a player model for reproducing a disk, a model including a player | 11-12-2009 |
20100128799 | ENCODING DEVICE AND METHOD, DECODING DEVICE AND METHOD, PROGRAM, RECORDING MEDIUM, AND DATA STRUCTURE - It is possible to display a caption with an aspect ratio independent from the aspect ratio of a main video. When a flag indicating that the aspect ratio of the caption is 16:9 is set, the caption video image frame size (720×480) is converted so as to match the aspect ratio of 16:9 and the caption video obtained as the result is superimposed on the main video and displayed. That is, when the main video has an aspect ratio of 4:3, as shown in FIG. | 05-27-2010 |
20100129052 | DATA RECORDING DEVICE, DATA RECORDING METHOD, DATA PROCESSING DEVICE, DATA PROCESSING METHOD, PROGRAM, PROGRAM RECORDING MEDIUM, DATA RECORDING MEDIUM, AND DATA STURCTURE - It is possible to realize variable-speed reproduction without deteriorating the image quality. For RAPI from a RAPI information extractor ( | 05-27-2010 |
20130117632 | STORAGE CONTROL APPARATUS - Embodiments of the technology disclosed herein are intended to flexibly set the rules of attaching error correction codes to a group of data sequences stored in a memory. A storage control apparatus has an error correction code attachment rule hold block and an error correction portion. The error correction code attachment rule hold block holds the rules of attaching error correction codes to a group of data sequences stored in a memory by relating the rules with the data for each address of the group of data sequences. If an access occurs to the memory, the error correction portion executes error correction processing on a group of data sequences stored in the memory in accordance with the attachment rules related to the address at which the access occurred. | 05-09-2013 |
20130139030 | STORAGE CONTROLLER, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND STORAGE CONTROLLING METHOD - A storage controller includes an error correcting code managing portion, an address managing portion and an error correcting portion. The error correcting code managing portion manages a correspondence relationship between predetermined plural pieces of unit data, and a second error code corresponding to the plural pieces of unit data every entry when plural pieces of unit data and a second error correcting code are stored in a storage portion. The address managing portion manages a correspondence relationship between logical addresses and the entries in the error correcting code managing portion. The error correcting portion acquires the entry in the error correction managing portion corresponding to the logical address as an object of read from the address managing portion, and carries out error correction based on the plural pieces of unit data managed in the entry concerned, and the second error correcting code. | 05-30-2013 |
20130254498 | STORAGE CONTROL APPARATUS, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM AND PROCESSING METHOD THEREFOR - A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed. | 09-26-2013 |
20130262737 | STORAGE CONTROL APPARATUS , STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM AND PROCESSING METHOD - Disclosed herein is a storage control apparatus including: a command processing section configured to receive a command requesting accesses to a plurality of access units by specifying an address in a memory space including a plurality of banks; and an address generating section configured to generate an address of an access unit serving as an object of the accesses in a bank selected from the banks as a bank determined in advance for the specified address. | 10-03-2013 |
20130272078 | STORAGE CONTROLLING APPARATUS, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM AND STORAGE CONTROLLING METHOD - Disclosed herein is a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a reference value in at least part of input data to a memory cell, which executes rewriting to one of the binary values and rewriting to the other one of the binary values in order in a writing process, to generate decision data indicative of a result of the decision; and a write side outputting portion configured to output, when it is decided that the bit number is greater than the reference value, the input data at least part of which is inverted as write data to the memory cell together with the decision data. | 10-17-2013 |
20130275818 | STORAGE CONTROLLING APPARATUS, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM AND PROCESSING METHOD - Disclosed herein is a storage controlling apparatus, including: a status acquisition section configured to acquire status including a number of times of execution of verification after writing into a memory from the memory; a history information retention section configured to retain a history of the status as history information in an associated relationship with each of predetermined regions of the memory; and a region selection section configured to select a region which satisfies a condition in accordance with the history information when a new region is to be used in the memory. | 10-17-2013 |
20130282993 | STORAGE CONTROL DEVICE, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM AND STORAGE CONTROL METHOD - A storage control device includes a first rewriting section, a second rewriting section, and a first retry control section. The first rewriting section performs first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written. The second rewriting section performs second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written. The first retry control section causes the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again if an error occurs during the first rewrite. | 10-24-2013 |
20130290620 | STORAGE CONTROLLING APPARATUS, STORAGE APPARATUS AND PROCESSING METHOD - A storage controlling apparatus includes a command decoder and command processing section. The command decoder decides whether or not a plurality of access object addresses of different commands included in a command string correspond to words different from each other in a same one of blocks of a memory cell array which have a common plate. The command processing section collectively and successively executes, when it is decided that the access object addresses of the commands correspond to the words different from each other in the same block of the memory cell array, those of operations in processing of the commands in which an equal voltage is applied as a drive voltage between the plate and a bit line. | 10-31-2013 |
20130339637 | MEMORY CONTROL APPARATUS, MEMORY APPARATUS, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHOD FOR USE THEREWITH - There is provided a memory control apparatus including: a pre-read processing section reading pre-read data from a data area to be written to before a write process in a predetermined data area of a memory cell array; a conversion determination section which, upon selectively allowing the pre-read data to transition to either a first conversion candidate or a second conversion candidate of the write data to be written in the write process, generates a determination result for selecting either of the candidates based on the larger of two values of which one is the number of bits transitioning from the first value to the second value and of which the other is the number of bits transitioning from the second value to the first value; and a conversion control section selecting either of the candidates in accordance with the determination result. | 12-19-2013 |
20140009996 | STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHOD THEREOF - There is provided a storage control device including a read processing unit that reads data and inversion state information indicating whether the data is in an inverted state or a non-inverted state from a specific region of a memory cell array that stores the data and the inversion state information with first intensity in association, and a write processing unit that writes data obtained by inverting the data and a state obtained by changing a state indicated by the inversion state information to an opposite state in the specific region with second intensity that is different from the first intensity. | 01-09-2014 |
20140025907 | STORAGE CONTROL APPARATUS, STORAGE APPARATUS, AND PROCESSING METHODS THEREOF - There is provided a storage control apparatus including a memory state acquisition unit acquiring a storage state of a memory associated with a write target, and an operation instruction generation unit generating an operation instruction of at least 2 bits per cell of the memory associated with the write target, from the acquired storage state and write data. | 01-23-2014 |
20140059268 | MEMORY CONTROL DEVICE, NON-VOLATILE MEMORY, AND MEMORY CONTROL METHOD - Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written. | 02-27-2014 |
20140059404 | MEMORY CONTROL DEVICE, MEMORY DEVICE, INFORMATION PROCESSING SYSTEM AND MEMORY CONTROL METHOD - There is provided a memory control device, including a request determining unit that determines a type of a request, and a control unit that writes read data read from a memory cell array in the memory cell array in units of predetermined pages of the memory cell array when the request is a refresh request, and divides the page of write data into units of groups and writes the page of the write data in the memory cell array over twice or more when the request is a write request. | 02-27-2014 |
20140122972 | STORAGE CONTROL APPARATUS, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM, AND STORAGE CONTROL METHOD - A storage control apparatus includes a standard read request unit, an error correcting unit, and a high-accuracy read request unit. The standard read request unit is configured to issue a request for a read with standard accuracy to a read address in a memory. The error correcting unit is configured to perform error correction on the basis of an error correcting code and data returned by the memory in response to the read request with the standard accuracy. The high-accuracy read request unit is configured to issue, when an error incapable of being corrected by the error correction is caused, a request again for a read with higher accuracy than the standard accuracy to the read address. | 05-01-2014 |
20140129904 | ERROR DETECTION AND CORRECTION APPARATUS, MISMATCH DETECTION APPARATUS, MEMORY SYSTEM AND ERROR DETECTION AND CORRECTION METHOD - An error detection and correction apparatus includes a code word read-out unit to execute read processing to read out a code word including a plurality of code elements by detection of an erasure position as read data from a memory address and to execute re-read processing to read out the code word as re-read data from the memory address after a predetermined time is elapsed from the time to read out the read data; a timing control erasure position detection unit to detect a position of the code element having a value not matched as the erasure position in the code word by determining whether or not the value is matched per the code word in the read data and the re-read data; and an error correction unit to correct an error based on the erasure position in the code word where the erasure position is detected. | 05-08-2014 |
20140208182 | CONTROLLER, INFORMATION PROCESSING SYSTEM, METHOD OF CONTROLLING CONTROLLER, AND PROGRAM - A controller includes: a low-level error correction section configured to execute low-level error correction in which an error in a code word is corrected with use of a predetermined decoding algorithm; and a high-level soft-decision error correction section configured to execute high-level soft-decision error correction in which the error in the code word is corrected with use of a high-level algorithm when the error correction by the low-level error correction section has failed, the high-level algorithm being a soft-decision decoding algorithm having higher error correction capability than error correction capability of the predetermined decoding algorithm. | 07-24-2014 |
20140223256 | ERROR DETECTION AND CORRECTION UNIT, ERROR DETECTION AND CORRECTION METHOD, INFORMATION PROCESSOR, AND PROGRAM - An error detection and correction unit includes: a first-code error detection section configured to detect whether or not each of a plurality of first code words in a second code word has an error, the second code word generated by encoding the plurality of first code words in chains and being a code word containing a plurality of partial data; and a second-code error correction section configured to correct the error in one partial data containing the first code word in which the error is detected of the plurality of partial data in the second code word, based on adjacent partial data adjacent to the one partial data. | 08-07-2014 |
20140258606 | STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND STORAGE CONTROL METHOD - A storage control device includes: a partial unit buffer configured to hold at least one data assigned to a partial unit, in which the partial unit is one of a plurality of partial units that are each a division of a write unit for a memory; and a request generation section configured to generate, upon indication of a busy state in the memory for any of the partial units, a write request for the write unit of the memory when the holding of the data assigned to that partial unit is possible in the partial unit buffer. | 09-11-2014 |
20140301132 | STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHOD THEREOF - Provided is a storage control device including a history information holding unit configured to hold history information in a predetermined data area of a memory cell holding either a first value or a second value for each bit, the history information indicating which mode of a first mode or a second mode is employed upon a previous write operation, the first mode setting all bits to the first value and then setting any bit to the second value, the second mode setting all bits to the second value and then setting any bit to the first value, and a bitwise operation unit configured to perform a write operation in the second mode if the history information indicates the first mode and to perform a write operation in the first mode if the history information indicates the second mode. | 10-09-2014 |
20140372791 | INTERFACE CONTROL CIRCUIT, MEMORY SYSTEM, AND METHOD OF CONTROLLING AN INTERFACE CONTROL CIRCUIT - Disclosed is an interface control circuit including an error detection unit, an error correction unit, and an adjustment control unit. The error detection unit is configured to detect whether an error occurs in error correction coded data transmitted via an interface. The error correction unit is configured to execute error correction processing of correcting the error when the error occurs. The adjustment control unit is configured to start adjustment processing of adjusting a transmission characteristic of the interface when the error occurs. | 12-18-2014 |
20150026538 | STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM AND STORAGE CONTROL METHOD - An error detection-correction unit reads system information for operating a system from a first memory and performs error detection-correction processing. A control unit supplies the system information to a host computer in a case where the error detection-correction processing is successful. In addition, the control unit reads a backup of the system information from a second memory that is different from the first memory and supplies the backup of the system information to the host computer in a case where the detection-correction processing fails. | 01-22-2015 |
20150049538 | STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND STORAGE CONTROL METHOD - Provided is a storage control device including: a detection unit which detects a first timing for performing a first rewriting process of performing only a first operation from among the first operation and a second operation, in a memory cell array in which each bit transitions to a first storage state by the first operation and transitions to a second storage state by the second operation; and a request unit which makes a request for the first rewriting process with respect to the memory cell array, when the first timing is detected. | 02-19-2015 |
20150052329 | MEMORY CONTROL DEVICE, HOST COMPUTER, INFORMATION PROCESSING SYSTEM AND METHOD OF CONTROLLING MEMORY CONTROL DEVICE - A memory control device includes an address translation information holding portion that holds a portion of entries that are selected from address translation information containing a plurality of entries that associate a logical address with a physical address of a memory device; an address translation information acquisition unit that, when the entry containing the logical address specified by a host computer is not held in the address translation information holding portion, acquires the entry that is not held from the host computer and causes the address translation information holding portion to hold the entry; an address translation unit that translates the specified logical address into the physical address on the basis of the entries that are held in the address translation information holding portion; and a data transfer unit that executes a data transfer process in which transfer data is transferred using the translated physical address. | 02-19-2015 |