Patent application number | Description | Published |
20080291763 | MEMORY DEVICE - A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status. | 11-27-2008 |
20090010080 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells. | 01-08-2009 |
20090016142 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells. | 01-15-2009 |
20090154257 | MEMORY SYSTEM AND CONTROL METHOD FOR MEMORY - The memory system comprises: a semiconductor memory that includes an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit, which is coupled to the internal circuit and operates according to a second power supply voltage; a first control unit that includes a control input/output circuit, which is coupled to the memory input/output circuit and operates according to the second power supply voltage; a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal; a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal; and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit. | 06-18-2009 |
20090161468 | SEMICONDUCTOR MEMORY, MEMORY SYSTEM, AND MEMORY ACCESS CONTROL METHOD - A semiconductor memory is provided, the semiconductor memory including a memory core that includes a plurality of memory cells, a refresh generation unit that generates a refresh request for refreshing the memory cell, a core control unit that performs an access operation in response to an access request, a latency determination unit that activates a latency extension signal upon a conflict between activation of a chip enable signal and the refresh request and that deactivates the latency extension signal in response to deactivation of the chip enable signal, a latency output buffer that outputs the latency extension signal, and a data control unit that changes a latency from the access request to a transfer of data to a data terminal during the activation of the latency extension signal. | 06-25-2009 |
20090207682 | SEMICONDUCTOR MEMORY DEVICE - A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost. | 08-20-2009 |
20100110818 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation. | 05-06-2010 |
20100302879 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells. | 12-02-2010 |
20100322072 | Packet Transfer System, Network Management Apparatus, and Edge Node - A packet transport system to which the present invention is applied includes an edge node accommodating an access network at an edge, and a core node of carrying out a processing of assorting a frame gathered from a plurality of the edge nodes, the edge node provides a label to the frame flowing in from the access network, and the packet transport system transmits the frame in reference to the label. The edge node includes a priority information providing portion of changing a piece of priority information provided to the frame flowing in from the access network in accordance with a congested state of the core node, and a priority previously set to a path specified by the label. | 12-23-2010 |
20110243554 | PASSIVE OPTICAL NETWORK SYSTEM - When a neighbor ONU receives a signal with light intensity high enough to secure communication between an OLT and a remote ONU, the light intensity may be excessively high to damage a receiver of the neighbor ONU. In order to avoid such a problem, each ONU is notified of a downstream signal transmission plan (downstream light intensity map) prior to transmission of a downstream signal. Each ONU receives the downstream light intensity map (light intensity transmission schedule of downstream signal) in advance. Thus, the neighbor ONU can block or attenuate an optical signal addressed to the remote ONU, and the remote ONU can determine normal operation even when the remote ONU cannot receive a signal addressed to the neighbor ONU. Thus, the remote ONU can be prevented from issuing a wrong error signal. | 10-06-2011 |
20120087662 | PASSIVE OPTICAL NETWORK AND SUBSCRIBER LINE TERMINAL - The OLT manages information of optical intensity and communication bit rate receivable by each ONU, and transmits a signal at suitable optical intensity and a bit rate. The OLT decides a signal transmission plan for each ONU according to a status of accumulated information waiting to be transmitted in the OLT's own device buffer, and inserts the signal transmission plan in a header or payload of a downlink frame, thereby notifying the ONUs of the information prior to transmitting accumulated information (primary signal). The ONU recognizes the signal transmission plan of the OLT according to the time information in a downlink intensity map, receives only a signal having the optical intensity and bit rate suitable for the ONU's own device, and blocks other signals. | 04-12-2012 |
20120331043 | TRANSFER APPARATUS, TRANSFER NETWORK SYSTEM, AND TRANSFER METHOD - When data is disclosed to a plurality of users by using a transfer network and a transfer apparatus, data disclosure time control which cannot be adversely affected by the users is performed to reduce the difference in data disclosure time among the users. A transfer network system includes a distribution server serving as a data-distribution-source transfer apparatus, and a network terminal connected to distribution-destination user equipment. The distribution server and the network terminal each have a time keeping function and a time synchronization function for matching the time of the time keeping function with a master clock. The distribution server sends in advance disclosure data and disclosure time to the network terminal. When the time of the time keeping function of the network terminal matches the disclosure time, the network terminal sends the disclosure data to the user equipment. | 12-27-2012 |
20130182559 | TRANSMISSION NETWORK AND TRANSMISSION NETWORK MANAGEMENT SYSTEM - A transmission network is comprised of a network management system for collectively managing and controlling a plurality of transmission devices coupled mutually through transmission routes and the transmission network as well. The network management system includes a plane management table adapted to manage transmission planes defined as a set of paths in the transmission network, and the plane management table has the function to set and manage a transmission plane (working plane) applied during normal operation and besides, a single or a plurality of transmission planes (protection planes) applicable in the event of occurrence of a fault in the transmission network. Then, when a fault occurs in the transmission network, the network management system changes the applied plane to a suitable transmission plane. | 07-18-2013 |
20140085960 | SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC DEVICE - A semiconductor memory device including a plurality of memory blocks MBA0, MBA1, MBB0, MBB1; a plurality of bus lines | 03-27-2014 |
20140169071 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a plurality of memory blocks each including a first command generating circuit which generates a first command; a control circuit which controls the memory core based on the first command or based on a second command inputted via the input/output port; and an arbitration circuit which outputs a first delay signal to the control circuit of one memory block of the plurality of memory blocks, the first delay signal which delays a start of an execution of the first command, in a first case when the first command generated by the first command generating circuit of the one memory block and the second command inputted via the input/output port of another memory block of the plurality of memory blocks are overlapped. | 06-19-2014 |