Patent application number | Description | Published |
20080285368 | METHOD FOR NROM ARRAY WORD LINE RETRY ERASING AND THRESHOLD VOLTAGE RECOVERING - A method for erasing and recovering a memory array is disclosed. The memory array includes a plurality of sectors of memory cells. After erasing a sector of the memory array, all of the memory cells of the memory array are checked to find programmed memory cells in the other un-erased sectors of the memory array. If a programmed memory cell is found, the programmed memory cell will be programmed and verified until the threshold voltage of the programmed memory cell reaches a program verify voltage. | 11-20-2008 |
20080291722 | Charge trapping memory and accessing method thereof - An accessing method for a charge trapping memory including memory cells and tracking cells for storing expected data. The method includes the following steps. In a specific time first, the expected data is written into the tracking cells and the memory cells are not being programmed, read or erased. Next, the data stored in the tracking cells is sensed as read data according to a present reference current. Then, the present reference current is adjusted to an adjusted reference current according to a difference between the read data and the expected data so that the data stored in tracking cells is sensed as corresponding with the expected data according to the adjusted reference current. Thereafter, the memory cells are read according to the adjusted reference current. | 11-27-2008 |
20080304337 | METHOD FOR ACCESSING MEMORY - A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2 | 12-11-2008 |
20080307163 | METHOD FOR ACCESSING MEMORY - A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2 | 12-11-2008 |
20090003054 | DOUBLE PROGRAMMING METHODS OF A MULTI-LEVEL-CELL NONVOLATILE MEMORY - A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word line (a segment in a word line, a page in a word line, a program unit or a memory unit) of the charge trapping memory. A program unit can be defined by input data in a wide variety of ranges. For example, a program unit can be defined as a portion (such as a page, a group, or a segment) in one word line in which each group is selected for pre-program and pre-program-verify, either sequentially or in parallel with other groups in the same word line. | 01-01-2009 |
20090022004 | Charge recycling method and driving circuit and low power memory using the same - A driving circuit includes a first switch, a first driver and a second driver. The first switch has a first terminal coupled to a first voltage. The first driver includes a second switch and a third switch. The second switch has a first terminal coupled to a second terminal of the first switch, and a second terminal coupled to a first capacitor. The third switch has a first terminal coupled to the second terminal of the second switch, and a second terminal coupled to a second voltage. The second driver includes a fourth switch and a fifth switch. The fourth switch has a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to a second capacitor. The fifth switch has a first terminal coupled to the second terminal of the fourth switch, and a second terminal coupled to the second voltage. | 01-22-2009 |
20090027108 | Multiple-stage charge pump circuit with charge recycle circuit - A multiple-stage charge pump circuit includes first and second pump capacitors, a charge recycle circuit, and first and second transfer circuits. The charge recycle circuit includes first and second driving circuits and a switch circuit turning off to make a node floating and to couple first terminals of the first and second pump capacitors to the node in a first time period. The switch circuit and first and second driving circuits provide a specific voltage to the node and control voltages at the first terminals of the first and second pump capacitors in second and third time periods, respectively. The first and second transfer circuits provide a high voltage to a second terminal of the first pump capacitor in the second time period, and provide the voltage of the second terminal of the first pump capacitor to a second terminal of the second pump capacitor in the third time period. | 01-29-2009 |
20090046529 | Biasing and shielding circuit for source side sensing memory - A shielding circuit for preventing a sense current of a target cell from the influence of a source current of first adjacent cell includes a pre-discharge device, first and second biasing units, first and second voltage pull-down units, and a connection units. The pre-discharge device is for setting the voltage of the sense node to a negative voltage. The first and second biasing units are for biasing the source voltage of the target and the first adjacent cell equal to a biasing voltage, respectively. The first and second voltage pull-down units are for pulling down the source voltage of the target and the first adjacent cell closing to a ground level, respectively. The connection unit is for receiving and outputting the sense current passing through the first biasing unit to the sense node. | 02-19-2009 |
20090059668 | Virtual ground array memory and programming method thereof - A method for programming a virtual ground array memory, which includes a first cell and a second cell adjacent to first cell, includes the following steps. First, the first cell is selected as a target cell, wherein the second cell has been programmed to have data. Next, the second cell is read and the data is recorded in a register. Then, the target cell is programmed. Next, a program verifying operation is performed on the second cell. Afterwards, the data recorded in the register is programmed back to the second cell when the program verifying operation performed on the second cell fails. | 03-05-2009 |
20090059698 | METHOD FOR TESTING MEMORY - A method for testing a memory includes the following steps. First, data is read from the memory and stored to a first temporary memory. Meanwhile, expected data corresponding to the data from the memory is written into a second temporary memory from a tester. Thereafter, the data in the first temporary memory and the expected data in the second temporary memory are compared with each other to judge whether the memory has an enough operation window. | 03-05-2009 |
20090089526 | MEMORY DEVICES WITH DATA PROTECTION - A memory device comprises a memory array, a status register coupled with the memory array, and a security register coupled with the memory array and the status register. The memory array contains a number of memory blocks configured to have independent access control. The status register includes at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit. The security register includes at least one register-protection bit. The register-protection bit is programmable to a memory-protection state for preventing a state change of at least the protection bit of the status register. The register-protection bit is configured to remain in the memory-protection state until the resetting of the memory device. | 04-02-2009 |
20090116293 | Memory and method for charging a word line thereof - A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage. | 05-07-2009 |
20090154233 | NAND TYPE MEMORY AND PROGRAMMING METHOD THEREOF - A memory includes many memory regions. The memory regions have multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The first bit line is coupled to a first column of the multi-level cells. The second bit line is coupled to a second column of the multi-level cells. The data buffer is coupled to the first bit line and the second bit line and for storing data to be programmed into the multi-level cells. The protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error from occurring. | 06-18-2009 |
20090177817 | METHOD AND SYSTEM FOR ENHANCED READ PERFORMANCE IN SERIAL PERIPHERAL INTERFACE - A method for reading data in an integrated circuit includes receiving a read command, which is associated with an enhanced data read, and receiving a first address from a plurality of input/output pins. The method includes receiving a first performance enhancement indicator and determining whether an enhanced read operation is to be performed based on at least information associated with the first performance enhancement indicator. The method includes waiting n clock cycles, where n is an integer, then outputting data from a memory array in the integrated circuit using the plurality of input/output pins concurrently. The method also includes performing an enhanced read operation, if it is determined that the enhanced read operation is to be performed. In an embodiment of the method, performing an enhanced read operation includes receiving a second address and a second performance enhance indicator without receiving a read command. | 07-09-2009 |
20090196104 | MEMORY AND METHOD OPERATING THE MEMORY - A memory comprises a memory array, a sense unit, and a biasing and shielding circuit. The biasing and shielding circuit is coupled to the memory array and the sense unit, wherein the biasing and shielding circuit comprises a first transistor, a second transistor, and a capacitor. The first transistor has a gate coupled to a biasing voltage and a first terminal coupled to the sense unit. The second transistor has a gate coupled to the biasing voltage and a first terminal coupled to a first potential. The capacitor is coupled to the sense unit and the first transistor. | 08-06-2009 |
20090201060 | CLOCK SYNCHRONIZING CIRCUIT - A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit. | 08-13-2009 |
20090201725 | MULTI-LEVEL MEMORY CELL PROGRAMMING METHODS - A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied to the first memory cell upon reaching the predetermined threshold voltage is recorded. A second memory cell is programmed to a second threshold state by applying an initial bias voltage to the second memory cell which is function of the recorded bias voltage. | 08-13-2009 |
20090219759 | DOUBLE PROGRAMMING METHODS OF A MULTI-LEVEL-CELL NONVOLATILE MEMORY - A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word line (a segment in a word line, a page in a word line, a program unit or a memory unit) of the charge trapping memory. A program unit can be defined by input data in a wide variety of ranges. For example, a program unit can be defined as a portion (such as a page, a group, or a segment) in one word line in which each group is selected for pre-program and pre-program-verify, either sequentially or in parallel with other groups in the same word line. | 09-03-2009 |
20090231920 | PROGRAMMING METHOD AND MEMORY DEVICE USING THE SAME - A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command. | 09-17-2009 |
20090268543 | MEMORY CONTROL CIRCUIT AND MEMORY ACCESSING METHOD - A control circuit applied in a memory that comprises a first memory block and a second memory block, and each of the first and the second memory blocks includes a boundary cell. The control circuit comprises an address decoder, a first Y-multiplexer, and a second Y-multiplexer. The address decoder provides a plurality of column selection signals capable of being a boundary value. The first Y-multiplexer corresponds to the first memory block and provides a first boundary data channel for a boundary cell of the first memory block. The second Y-multiplexer corresponds to the second memory block and provides a second boundary data channel for a boundary cell of the second memory block. The first and the second boundary data channels are enabled simultaneously in response to the boundary value for outputting boundary data stored in the boundary cell of the first memory block and that of the second memory block. | 10-29-2009 |
20090295419 | MEMORY CHIP AND METHOD FOR OPERATING THE SAME - A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip. | 12-03-2009 |
20090296496 | METHOD AND CIRCUIT FOR TESTING A MULTI-CHIP PACKAGE - A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells. | 12-03-2009 |
20100027331 | MEMORY AND READING METHOD THEREOF - A method for reading a memory, which includes a memory cell having a first half cell and a second half cell, includes the following steps. A first voltage is applied to the memory cell to determine whether a threshold voltage of the first half cell is higher than a predetermined value or not. If the threshold voltage of the first half cell is higher than the predetermined value, a second voltage higher than the first voltage is applied to the memory cell to read data stored in the second half cell, otherwise a third voltage lower than the first voltage is applied to the memory cell to read the data stored in the second half cell. | 02-04-2010 |
20100027339 | PAGE BUFFER AND METHOD OF PROGRAMMING AND READING A MEMORY - A page buffer and method of programming and reading a memory are provided. The page buffer includes a first latch, a second latch, a data change unit and a program control unit. The first latch includes a first terminal for loading data of the lower page and the upper page. The second latch includes a first terminal for storing the data of the lower page and the upper page from the first latch. The data change unit is coupled to a second terminal of the first latch for changing a voltage of the second terminal of the first latch to a low level. The program control unit is coupled to the first terminal of the second latch and the cells, and controlled by the voltage of the first terminal of the first latch for respectively programming the data of the lower page and the upper page to a target cell. | 02-04-2010 |
20100122043 | MEMORY AND METHOD APPLIED IN ONE PROGRAM COMMAND FOR THE MEMORY - A memory and a method applied in one program command for the memory are provided. The memory includes a buffer and at least one program unit. The method includes the following steps. First, enter the program command to the memory. Next, enter user data to the buffer. Read the data of the program unit. Determine whether the user data fill the buffer. Fill the part of the buffer unoccupied by the user data with the data of the program unit if the user data do not fill the buffer. Erase the program unit if the program unit is not empty. Finally, program the data of the buffer into the program unit. | 05-13-2010 |
20100124136 | TEMPERATURE COMPENSATION CIRCUIT AND METHOD FOR SENSING MEMORY - A temperature compensation circuit includes a voltage generator, a comparator and an emulation cell array. The voltage generator provides a predetermined voltage and a reference voltage. The comparator has a first terminal for receiving the predetermined voltage, and a second terminal for receiving the reference voltage. The emulation cell array is coupled to the first terminal of the comparator. When a voltage of the first terminal of the comparator is discharged, via the emulation cell array, to be lower than the reference voltage, the comparator outputs a read timing control signal to control a sense amplifier to perform a sensing operation. | 05-20-2010 |
20100180183 | CIRCUIT FOR REDUCING THE READ DISTURBANCE IN MEMORY - A memory includes an internal data block and a temporary storing unit. The internal data block stores internal data of the memory. The temporary storing unit temporarily stores the internal data of the memory after the memory is powered on. | 07-15-2010 |
20100182833 | MEMORY AND BOUNDARY SEARCHING METHOD THEREOF - A memory and a boundary searching method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely. | 07-22-2010 |
20100192039 | MEMORY DEVICE AND OPERATION METHOD THEREOF - A method for operating a memory device is provided and includes the following steps. A first error correction code is generated according to user data. Then, the user data is written to the memory device. Moreover, the user data in the memory device is read, and a second error correction code is generated according to the read user data. Further, the first and the second error correction codes are written to the memory device. | 07-29-2010 |
20100219881 | Multiple-Stage Charge Pump with Charge Recycle Circuit - A multiple-stage charge pump circuit comprises first and second pump capacitors, first and second transfer circuits, first and second driving circuits, and a charge recycle circuit. The first pump capacitor, the first transfer circuit, and the first driving circuit form a first stage circuit, and the second pump capacitor, the second transfer circuit and the second driving circuit form a second stage circuit. The first and the second stage circuits operate 180 degree out of phase with each other. The charge recycle circuit transfers the charge at the second end of the first pump capacitor to the second end of the second pump capacitor in a first time interval, and transferring the charge at the second end of the second pump capacitor to the second end of the first pump capacitor in a second time interval. | 09-02-2010 |
20100299473 | SERIAL PERIPHERAL INTERFACE AND METHOD FOR DATA TRANSMISSION - A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circuit for inputting multiple timing pulses. The plurality of pins transmit the instruction, the address or the read out data at rising edges, falling edges or both edges of the timing pulses. | 11-25-2010 |
20100322018 | Temperature Compensation Circuit and Method for Sensing Memory - A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot. | 12-23-2010 |
20110016288 | Serial Flash Memory and Address Transmission Method Thereof - A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length. If the first memory space is addressed according to the first address length, a first memory address is completely received within an address time duration so that data corresponding to the first memory address is initially outputted from a starting clock. In the address transmission method, if the second memory space is addressed according to the second address length, a portion of a second memory address is received within the address time duration. The other portion of the second memory address is received within a waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock. | 01-20-2011 |
20110038218 | Memory Chip and Method for Operating the Same - A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip. | 02-17-2011 |
20110055670 | Programming Method and Memory Device Using the Same - A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command. | 03-03-2011 |
20110068837 | APPARATUS AND METHOD TO TOLERATE FLOATING INPUT PIN FOR INPUT BUFFER - An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch. | 03-24-2011 |
20110085378 | Memory and Operation Method Therefor - In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage. | 04-14-2011 |
20110085380 | Method of Programming a Memory - A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an n | 04-14-2011 |
20110085383 | CURRENT SINK SYSTEM FOR SOURCE SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell. | 04-14-2011 |
20110085384 | CURRENT SINK SYSTEM FOR SOURCE-SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell. | 04-14-2011 |
20110087838 | Memory Device and Operation Method Therefor - Provided is a MLC (Multi-level cell) memory device, comprising: a memory array, including a plurality of groups each storing a plurality of bits; and an inverse bit storage section, storing a first inverse bit data including a plurality of inverse bits, the plurality of bits in the same group in the memory array being related to a respective inverse bit. | 04-14-2011 |
20110115551 | CHARGE PUMP UTILIZING EXTERNAL CLOCK SIGNAL - A method of generating a pumping voltage in an integrated circuit includes receiving an external clock signal from outside of the integrated circuit. The frequency of the received external clock signal is changed according to one or more modulation ratios, resulting in one or more respective modulated external clock signal. The external clock signal or one of the modulated external clock signals is then selected for use as a pump clock signal. The pump clock signal is used for driving the pump capacitance of a pump circuit for generating the pumping voltage. | 05-19-2011 |
20110128786 | MEMORY DEVICE - A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines, wherein a first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source. | 06-02-2011 |
20110128791 | Method and Apparatus of Performing an Erase Operation on a Memory Integrated Circuit - Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines. | 06-02-2011 |
20110128809 | Method and Apparatus of Addressing A Memory Integrated Circuit - A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes. | 06-02-2011 |
20110149675 | Local Word Line Driver - A two transistor word line driver is disclosed. An example disclosed word line driver is simplified with common signals on the gates of the p-type and the n-type transistors. An example disclosed word line driver consumes less power by applying a negative voltage to a word line driver selected from multiple word line drivers. | 06-23-2011 |
20110157951 | 3D CHIP SELECTION FOR SHARED INPUT PACKAGES - A multi-chip package with die having shared input and unique access IDs. A unique first ID is assigned and stored on die in a die lot. A set of die is mounted in a multi-chip package. Free access IDs are assigned by applying a sequence of scan IDs on the shared input. On each die, the scan ID on the shared input is compared with the unique first ID stored on the die. Upon detecting a match, circuitry on the die is enabled for a period of time to write an access ID in nonvolatile memory, whereby one of the die in the multi-chip package is enabled at a time. Also, the shared input is used to write a free access ID in nonvolatile memory on the one enabled die in the set. The unique first IDs can be stored during a wafer level sort process. | 06-30-2011 |
20110157986 | MEMORY AND OPERATING METHOD THEREOF - A memory and an operating method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely. | 06-30-2011 |
20110164461 | Memory Device - A memory device comprises first memory block having first boundary cell and second memory block having second boundary cell. Data of the first and the second boundary cells are outputted simultaneously corresponding to a plurality of column selection signals. | 07-07-2011 |
20110176378 | Memory Program Discharge Circuit - A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation. | 07-21-2011 |
20110216601 | CURRENT SINK SYSTEM BASED ON SAMPLE AND HOLD FOR SOURCE SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to a magnitude of an operating voltage between first and second nodes. During a first time interval, the operating voltage is set in response to a magnitude of the reference current using a feedback path. During a second time interval following the first time interval, the operating voltage is held independent of the feedback path. The data value stored in the memory cell is determined based on a difference in current between the read current and the sink current during the second time interval. | 09-08-2011 |
20110227552 | Apparatus of Supplying Power and Method Therefor - A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing. | 09-22-2011 |
20110238939 | MEMORY DEVICES WITH DATA PROTECTION - A memory device comprises a memory array, a status register, a status-register write-protect bit and a security register. The memory array contains a number of memory blocks. The status register includes at least one protection bit indicative of a protection status of at least one corresponding block of the memory blocks. The status-register write-protect bit is coupled with the status register for preventing a state change of the at least one protection bit. The security register includes at least one register-protection bit for preventing the state change in one of the at least one protection bit of the status register and the status-register write-protect bit. | 09-29-2011 |
20110273936 | ERASE PROCESS FOR USE IN SEMICONDUCTOR MEMORY DEVICE - A method of erasing memory cells of a memory device includes programming memory cells if the erasing procedure is suspended. The erasing procedure can include pre-programming, erasing, and soft-programming of memory cells in a selected memory unit. If a suspend command is received, for example to allow for a read operation of memory cells of another unit of memory, the erasing procedure stops the pre-programming, erasing, or soft-programming, and proceeds with programming one or more memory cells of the memory unit that was being erased. | 11-10-2011 |
20110317493 | Method and Apparatus of Performing An Erase Operation on a Memory Integrated Circuit - Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. | 12-29-2011 |
20120011300 | METHOD AND APPARATUS FOR HIGH-SPEED BYTE-ACCESS IN BLOCK-BASED FLASH MEMORY - Techniques utilizing an erase-once, program-many progressive indexing structure manage data in a flash memory device which avoids the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. Consequently, block-based flash memory can be used for high-speed byte access. | 01-12-2012 |
20120033518 | CURRENT SINK SYSTEM FOR SOURCE-SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell. | 02-09-2012 |
20120057410 | Method and Apparatus for the Erase Suspend Operation - Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector. | 03-08-2012 |
20120063228 | DATA SENSING ARRANGEMENT USING FIRST AND SECOND BIT LINES - Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers. | 03-15-2012 |
20120063236 | Method and Apparatus for Reducing Read Disturb in Memory - Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution. | 03-15-2012 |
20120069671 | MEMORY AND OPERATION METHOD THEREFOR - An operation method for a memory device having a plurality of memory cells includes: reading the plurality of memory cells by a first word line voltage to get a first number of a first logic state; reading the plurality of memory cells by a second word line voltage to get a second number of the first logic state, the second word line voltage different from the first word line voltage; and using the second word line voltage as a target word line voltage if the first number of the first logic state is equal to the second number of the first logic state. | 03-22-2012 |
20120131227 | SERIAL PERIPHERAL INTERFACE AND METHOD FOR DATA TRANSMISSION - A serial peripheral interface of an integrated circuit including multiple pins is provided. The pins are coupled to the integrated circuit. The integrated circuit receives an instruction through only one of the plurality of pins. The integrated circuit receives an address through the plurality of pins. The integrated circuit sends a read out data through the plurality of pins. | 05-24-2012 |
20120155181 | Method and Apparatus for Reducing Read Disturb in Memory - Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage. | 06-21-2012 |
20120182802 | Memory Architecture of 3D Array With Improved Uniformity of Bit Line Capacitances - A 3D integrated circuit memory array has a plurality of plane positions. Multiple bit line structures have a multiple sequences of multiple plane positions. Each sequence characterizes an order in which a bit line structure couples the plane positions to bit lines. Each bit line is coupled to at least two different plane positions to access memory cells at two or more different plane positions. | 07-19-2012 |
20120182804 | ARCHITECTURE FOR A 3D MEMORY ARRAY - Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines. | 07-19-2012 |
20120268987 | System and Method for Detecting Disturbed Memory Cells of a Semiconductor Memory Device - A method of detecting a disturb condition of a memory cell includes application of multiple sets of conditions to the memory cell and determining whether the memory cell behaves as a programmed memory cell in response to the sets of conditions. A disturbed memory cell can be detected if the memory cell responds as a programmed memory cell in response to one of the sets of conditions, but responds as an erased memory cell in response to another of the sets of conditions. | 10-25-2012 |
20120281478 | THERMALLY ASSISTED FLASH MEMORY WITH DIODE STRAPPING - A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines. | 11-08-2012 |
20120300562 | METHOD AND CIRCUIT FOR TESTING A MULTI-CHIP PACKAGE - A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells. | 11-29-2012 |
20130058181 | MEMORY WITH TEMPERATURE COMPENSATION - A memory element in which the temperature coefficient of a memory cell substantially matches the temperature coefficient of a reference cell and tuning either the temperature coefficient of a memory cell to substantially match the temperature coefficient of the reference cell provides for improved precision of sensing or reading memory element states, particularly so as to minimize the affect of temperature variations on reading and sensing states. | 03-07-2013 |
20130086294 | Serial Peripheral Interface and Method for Data Transmission - A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circuit for inputting multiple timing pulses. The plurality of pins transmit the instruction, the address or the read out data at rising edges, falling edges or both edges of the timing pulses. | 04-04-2013 |
20130127436 | APPARATUS OF SUPPLYING POWER AND METHOD THEREFOR - A power supply apparatus and a method for supplying power are provided. The method includes: providing a first power supply for outputting a first power signal; providing a second first power supply for outputting a second power signal; and selectively charging the second power supply by using the first power supply. | 05-23-2013 |
20130242665 | Method and Apparatus for Shortened Erase Operation - A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures. | 09-19-2013 |
20130279265 | Method and Apparatus for Reducing Erase Time of Memory By Using Partial Pre-Programming - Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells. | 10-24-2013 |
20140028367 | SELF-CALIBRATION OF OUTPUT BUFFER DRIVING STRENGTH - An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay. | 01-30-2014 |
20140062543 | DYNAMIC DRIVER CIRCUIT - A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage. | 03-06-2014 |
20140132309 | SELF-CALIBRATION OF OUTPUT BUFFER DRIVING STRENGTH - An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay. | 05-15-2014 |
20140198576 | PROGRAMMING TECHNIQUE FOR REDUCING PROGRAM DISTURB IN STACKED MEMORY STRUCTURES - A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence. Each iteration includes applying inhibit voltages to all of the cells in others of the plurality of sets. Also, each set of layers includes subsets of one or two, and there are at least two layers from other sets separating each of the subsets in one set. | 07-17-2014 |
20140219026 | METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS - Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state. | 08-07-2014 |
20140266105 | LOW DROP OUT REGULATOR AND CURRENT TRIMMING DEVICE - A regulator comprises an amplifier, a bias circuit, and a current trimming circuit. The bias circuit is coupled to the amplifier and supplies a first bias current to the amplifier in a first mode of a system including the regulator. The current trimming circuit is coupled to the bias circuit to adjust the first bias current. | 09-18-2014 |
20140281768 | RETENTION LOGIC FOR NON-VOLATILE MEMORY - An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state characterized by a minimum threshold exceeding a selected read bias. A controller includes a stand-by mode, a write mode and a read mode. Retention check logic executes on power-up, or during the stand-by mode, to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells. | 09-18-2014 |
20140376311 | METHOD AND APPRATUS FOR SHORTENED ERASE OPTION - A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures. | 12-25-2014 |
20150036436 | METHOD AND APPARATUS FOR REDUCING ERASE TIME OF MEMORY BY USING PARTIAL PRE-PROGRAMMING - Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells. | 02-05-2015 |