Patent application number | Description | Published |
20080205148 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device having a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers, each amplifier being connected to one of the plurality of bit lines respectively and a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each of the memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of the plurality of word lines respectively, the plurality of memory strings being connected to a corresponding bit line of the plurality of bit lines respectively, and at the time of programming all of the plurality of bit lines are selected, the number of the storage states being different in two of the memory cells which are adjacent on the same bit line. | 08-28-2008 |
20080291716 | METHOD OF PROGRAMMING A NON-VOLATILE MEMORY DEVICE - A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line. | 11-27-2008 |
20090010039 | NON-VOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation. | 01-08-2009 |
20090052227 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO - The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged. | 02-26-2009 |
20090103376 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device related to an embodiment of the present invention includes a memory cell array including a plurality of memory cells, a first interface part having a predetermined number of pins, a second interface part having a smaller number of the pins than the first interface part, a data pattern latch part which stores an externally input data pattern, a comparison part which compares the data pattern input or preliminarily set from the data pattern latch part with data which is read from the memory cell array, and a comparison result output part arranged in the second interface part, and which outputs a comparison result of the comparison part. | 04-23-2009 |
20090265591 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed. | 10-22-2009 |
20100246280 | SEMICONDUCTOR DEVICE HAVING RESET COMMAND - A semiconductor device includes a reset sequence circuit, a latch circuit, and a reset control circuit. The reset sequence circuit is activated by receiving an externally input signal when a reset operation is started and outputs a first trigger signal. The latch circuit is capable of holding selection information on circuits capable of being reset. The selection information is externally input. The reset control circuit outputs a reset signal on the basis of the selection information held in the latch circuit in response to a power-on reset signal and the first trigger signal output from the reset sequence circuit. | 09-30-2010 |
20110063887 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF TESTING DIODES AND MANUFACTURING METHOD THEREOF - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, and a control circuit. The memory cell array includes plural memory cells arranged in rows and columns and each including a diode and resistance-change element. The control circuit tests the diodes for the respective memory cells. The control circuit tests the diode at least at one of times before and after one of a write operation, erase operation and read operation with respect to the memory cell is performed. | 03-17-2011 |
20110103135 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO - The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged. | 05-05-2011 |
20110141794 | SEMICONDUCTOR MEMORY DEVICE AND INSPECTING METHOD OF THE SAME - According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells, lines provided to correspond to the memory cells, a first decoder configured to select a first line as an inspection target from the lines, a second decoder configured to select a second line for generating a reference voltage from the lines, a driver configured to charge the first and second lines, a discharging circuit configured to simultaneously discharge the first and second lines, and a sense amplifier configured to compare a voltage of the first line with a voltage of the second line to detect a defect of the first line while the first line is discharged. | 06-16-2011 |
20110264969 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed. | 10-27-2011 |
20120002457 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME - According to one embodiment, a semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, and a data input/output circuit includes a first address buffer and a second address buffer configured to store a first address and a second address of the plurality of memory cells, and a controller configured to perform control to time-divisionally output the first address and the second address to a first address bus and a second address bus in data input/output. | 01-05-2012 |
20120069530 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip. | 03-22-2012 |
20120235218 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a device includes a semiconductor substrate, a first region including a first well which is formed in substrate, a second well which is formed in substrate and on first well, and a memory cell which is formed on second well, and a second region including a third well which is formed in substrate, and a first transistor which is formed on third well. The device includes a third region including a second transistor which is formed on semiconductor substrate, and a fourth region including a fourth well which is formed in semiconductor substrate, a fifth well which is formed in substrate and on fourth well, and a third transistor which is formed on fifth well. Bottoms of first well and fourth well are lower than a bottom of third well, and bottom of third well is lower than bottoms of second well and fifth well. | 09-20-2012 |
20120243365 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF SETTING OPERATION ENVIRONMENT THEREIN - A semiconductor memory device comprises: a memory cell array including a plurality of memory cells; an internal circuit having a function required in a storage operation of the memory cell array; a parameter storage unit configured to store a certain parameter and to have a storage place specified by a parameter address, the certain parameter designating an operation of the internal circuit; a command register configured to store a command instructing an operation of the internal circuit; and a converting circuit configured to adjust at least one of the parameter address and the command that differ between products or between standards to the internal circuit. | 09-27-2012 |