Patent application number | Description | Published |
20090092255 | Dynamic Authentication in Secured Wireless Networks - Systems and methods for authentication using paired dynamic secrets in secured wireless networks are provided. Each authenticated user is assigned a random secret generated so as to be unique to the user. The secret is associated with a wireless interface belonging to the user, so that no other wireless interface may use the same secret to access the network. The secret may be updated either periodically or at the request of a network administrator, and reauthentication of the wireless network may be required. | 04-09-2009 |
20110055898 | Dynamic Authentication in Secured Wireless Networks - Systems and methods for authentication using paired dynamic secrets in secured wireless networks are provided. Each authenticated user is assigned a random secret generated so as to be unique to the user. The secret is associated with a wireless interface belonging to the user, so that no other wireless interface may use the same secret to access the network. The secret may be updated either periodically or at the request of a network administrator, and reauthentication of the wireless network may be required. | 03-03-2011 |
20110087766 | APPARATUS AND METHODS FOR MANAGING NETWORK RESOURCES - Apparatus and methods are provided for managing network resources. A central unified services and device management framework is operated to simultaneously manage various types of resources on behalf of multiple organizations. Within the framework, a common management layer provides services (e.g., account management, event logging) common to multiple different services and devices. Within a specific management layer, separate subsystems are implemented for different devices or types of devices. The device-specific subsystems invoke device-independent functional modules through primitives exposed by the common management layer. A given organization may establish tiered logical constructs to group resources deployed at different physical locations (e.g., cities, offices) or within different subdivisions of the organizations (e.g., subsidiaries, departments). | 04-14-2011 |
20110087882 | APPARATUS AND METHODS FOR PROTECTING NETWORK RESOURCES - Apparatus and methods are provided for protecting network resources, particularly in association with automatic provisioning of new client devices. A global PKI (Public Key Infrastructure) scheme is rooted at a globally available server. Roots of PKIs for individual organizations also reside at this server or another globally available resource. To enable access to an organization's network, one or more authenticators are deployed, which may be co-located with access points or other network components. After a client device enabler (CDE) and an authenticator perform mutual authentication with certificates issued within the global PKI, the CDE is used to provision a new client device for the organization. After the client is provisioned, it and an authenticator use certificates issued within the per-organization PKI to allow the client access to the network. | 04-14-2011 |
20120317625 | Dynamic Authentication in Secured Wireless Networks - Systems and methods for authentication using paired dynamic secrets in secured wireless networks are provided. Each authenticated user is assigned a random secret generated so as to be unique to the user. The secret is associated with a wireless interface belonging to the user, so that no other wireless interface may use the same secret to access the network. The secret may be updated either periodically or at the request of a network administrator, and reauthentication of the wireless network may be required. | 12-13-2012 |
20140068724 | DYNAMIC AUTHENTICATION IN SECURED WIRELESS NETWORKS - Systems and methods for authentication using paired dynamic secrets in secured wireless networks are provided. Each authenticated user is assigned a random secret generated so as to be unique to the user. The secret is associated with a wireless interface belonging to the user, so that no other wireless interface may use the same secret to access the network. The secret may be updated either periodically or at the request of a network administrator, and reauthentication of the wireless network may be required. | 03-06-2014 |
20140112305 | DISTRIBUTED SEAMLESS ROAMING IN WIRELESS NETWORKS - One embodiment of the present invention provides a system for configuring an access point in a wireless network. During operation, the access point discovers one or more existing access points associated with the wireless network. The access point then obtains a set of configuration information from one existing access point, and synchronizes a local timestamp counter to a selected existing access point, thereby allowing the access point to be configured without using a centralized management station. | 04-24-2014 |
20140112311 | DISTRIBUTED SEAMLESS ROAMING IN WIRELESS NETWORKS - One embodiment of the present invention provides a system for configuring an access point in a wireless network. During operation, the access point discovers one or more existing access points associated with the wireless network. The access point then obtains a set of configuration information from one existing access point, and synchronizes a local timestamp counter to a selected existing access point, thereby allowing the access point to be configured without using a centralized management station. | 04-24-2014 |
20140115354 | WIRELESS GATEWAY ADAPTER FOR A POWER-OVER-ETHERNET PORT - A PoE-enabled wireless device facilitates providing wireless access to a local area network (LAN) by receiving power from an Ethernet cable. The device includes a first Ethernet port that can receive a power signal. The device also includes a second Ethernet port that facilitates coupling the apparatus to the LAN, and includes a wireless module to provide a wireless network connection to the LAN. Specifically, the wireless module receives power from the power signal of the first Ethernet port to provide the wireless network connection. The wireless device can also include a third Ethernet port for providing power and a network connection to a remote network device. The wireless device can use the third Ethernet port to send an external-reset signal to the remote network device, which facilitates remotely resetting a configuration of the remote network device without having to physically access the remote network device. | 04-24-2014 |
20140329522 | DISTRIBUTED SEAMLESS ROAMING IN WIRELESS NETWORKS - One embodiment of the present invention provides a system for configuring an access point in a wireless network. During operation, the access point discovers one or more existing access points associated with the wireless network. The access point then obtains a set of configuration information from one existing access point, and synchronizes a local timestamp counter to a selected existing access point, thereby allowing the access point to be configured without using a centralized management station. | 11-06-2014 |
Patent application number | Description | Published |
20090136530 | Influenza Hemagglutinin and Neuraminidase Variants - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising (avian pandemic) influenza hemagglutinin and neuraminidase variants are provided. | 05-28-2009 |
20090175898 | Influenza Hemagglutinin And Neuraminidase Variants - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising influenza hemagglutinin and neuraminidase variants are provided. | 07-09-2009 |
20090175908 | Influenza Hemagglutinin And Neuraminidase Variants - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising influenza hemagglutinin and neuraminidase variants are provided. | 07-09-2009 |
20090175909 | Influenza Hemagglutinin And Neuraminidase Variants - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising (avian pandemic) influenza hemagglutinin and neuraminidase variants are provided. | 07-09-2009 |
20110002960 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising influenza hemagglutinin and neuraminidase variants are provided. | 01-06-2011 |
20110052618 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising (avian pandemic) influenza hemagglutinin and neuraminidase variants are provided. | 03-03-2011 |
20110070263 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising influenza hemagglutinin and neuraminidase variants are provided. | 03-24-2011 |
20110182936 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising (avian pandemic) influenza hemagglutinin and neuraminidase variants are provided. | 07-28-2011 |
20110212117 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising influenza hemagglutinin and neuraminidase variants are provided. | 09-01-2011 |
20120009215 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising (avian pandemic) influenza hemagglutinin and neuraminidase variants are provided. | 01-12-2012 |
20120034264 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising (avian pandemic) influenza hemagglutinin and neuraminidase variants are provided. | 02-09-2012 |
20120034265 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising influenza hemagglutinin and neuraminidase variants are provided. | 02-09-2012 |
20120135023 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising influenza hemagglutinin and neuraminidase variants are provided. | 05-31-2012 |
20120301503 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising influenza hemagglutinin and neuraminidase variants are provided. | 11-29-2012 |
20130156810 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising influenza hemagglutinin and neuraminidase variants are provided. | 06-20-2013 |
20130189293 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising (avian pandemic) influenza hemagglutinin and neuraminidase variants are provided. | 07-25-2013 |
20130243816 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, methods, compositions, and vaccines comprising influenza hemagglutinin and neuraminidase variants are provided. | 09-19-2013 |
Patent application number | Description | Published |
20090166321 | SELF-ASSEMBLY STRUCTURES USED FOR FABRICATING PATTERNED MAGNETIC MEDIA - Methods of defining servo patterns and data patterns for forming patterned magnetic media are described. For one method, a lithographic process is performed to define a servo pattern in servo regions on a substrate. The lithographic process also defines a first data pattern in data regions of the substrate. The first data pattern is then transferred to (i.e., etched into) the data regions. Self-assembly structures are then formed on the data pattern in the data regions to define a second data pattern. The servo pattern is then transferred to the servo regions and the second data pattern is transferred to the data regions. Thus, the servo pattern is defined through lithographic processes while the data pattern is defined by a combination of lithographic processes and self-assembly. | 07-02-2009 |
20090310256 | METHOD FOR MAKING A MASTER MOLD WITH HIGH BIT-ASPECT-RATIO FOR NANOIMPRINTING PATTERNED MAGNETIC RECORDING DISKS, MASTER MOLD MADE BY THE METHOD, AND DISK IMPRINTED BY THE MASTER MOLD - A method for making a master mold to be used for nanoimprinting patterned-media magnetic recording disks results in a master mold having topographic pillars arranged in a pattern of annular bands of concentric rings. The ratio of circumferential density of the pillars to the radial density of the concentric rings in a band is greater than 1. The method uses sidewall lithography to first form a pattern of generally radially-directed pairs of parallel lines on the master mold substrate, with the lines being grouped into annular zones or bands. The sidewall lithography process can be repeated, resulting in a doubling of the number of lines each time the process is repeated. Conventional lithography is used to form concentric rings over the radially-directed pairs of parallel lines. After etching and resist removal, the master mold has pillars arranged in circular rings, with the rings grouped into annular bands. The master mold may be used to nanoimprint the disks, resulting in disks having a BAR greater than 1, wherein BAR is the ratio of data track spacing in the radial direction to the data island spacing in the circumferential direction. | 12-17-2009 |
20100147797 | SYSTEM AND METHOD FOR PATTERNING A MASTER DISK FOR NANOIMPRINTING PATTERNED MAGNETIC RECORDING DISKS - A system and method for patterning a master disk or “stamper” to be used for nanoimprinting magnetic recording disks uses an air-bearing slider that supports an aperture structure within the optical near-field of a resist layer on a rotating master disk substrate. Laser pulses directed to the input side of the aperture are output to the resist layer. The aperture structure includes a metal film reflective to the laser radiation with the aperture formed in it. The aperture has a size less than the wavelength of the incident laser radiation and is maintained by the air-bearing slider near the resist layer to within the radiation wavelength. The timing of the laser pulses is controlled to form a pattern of exposed regions in the resist layer, with this pattern ultimately resulting in the desired pattern of data islands and nondata islands in the magnetic recording disks when they are nanoimprinted by the master disk. | 06-17-2010 |
20110132867 | METHOD AND SYSTEM FOR IMPRINT LITHOGRAPHY - A method and apparatus of imprint lithography wherein the method includes depositing a material on a patterned surface of a conductive substrate, and pressing a transparent substrate and the conductive substrate together, wherein the pressing causes the material to conform to the patterned surface. Energy is applied to the material to form patterned material from the material. The transparent substrate and the conductive substrate are separated, wherein the patterned material adheres to the transparent substrate. | 06-09-2011 |
20110215070 | SELF-ASSEMBLY STRUCTURES USED FOR FABRICATING PATTERNED MAGNETIC MEDIA - Methods of defining servo patterns and data patterns for forming patterned magnetic media are described. For one method, a lithographic process is performed to define a servo pattern in servo regions on a substrate. The lithographic process also defines a first data pattern in data regions of the substrate. The first data pattern is then transferred to (i.e., etched into) the data regions. Self-assembly structures are then formed on the data pattern in the data regions to define a second data pattern. The servo pattern is then transferred to the servo regions and the second data pattern is transferred to the data regions. Thus, the servo pattern is defined through lithographic processes while the data pattern is defined by a combination of lithographic processes and self-assembly. | 09-08-2011 |
20110258841 | Planarization Methods For Patterned Media Disks - A method is provided for forming a plurality of regions of magnetic material in a substrate having a first approximately planar surface. The method comprises the steps of fabricating projections in the first surface of the substrate, depositing onto the first surface a magnetic material in such a way that the tops of the projections are covered with magnetic material, and depositing filler material atop the substrate so produced. The filler material may then be planarized, for example by chemical-mechanical polishing. In an alternative embodiment magnetic material is deposited on a substrate and portions of it are removed, leaving islands of material. Filler material is then deposited, which may be planarized. | 10-27-2011 |
20140113064 | METHOD AND SYSTEM FOR OPTICAL CALIBRATION - A system and method of calibrating optical measuring equipment includes optically measuring discrete objects of a first known predictable pattern from a calibration apparatus, wherein the first known predictable pattern is a bit pattern. A recording surface optical reader is calibrated based on the optically measuring. Using the first known predictable pattern, contamination is filtered from the results of the optically measuring. | 04-24-2014 |
Patent application number | Description | Published |
20090004873 | HYBRID ETCH CHAMBER WITH DECOUPLED PLASMA CONTROLS - A dielectric etch chamber and method for improved control of plasma parameters. The plasma chamber comprises dual-frequency bias source that capacitively couples the RF energy to the plasma, and a single or dual frequency source that inductively couples the RF energy to the plasma. The inductive source may be modulated for improved etch uniformity. | 01-01-2009 |
20090277587 | FLOWABLE DIELECTRIC EQUIPMENT AND PROCESSES - Substrate processing systems are described that may include a processing chamber having an interior capable of holding an internal chamber pressure different from an external chamber pressure. The systems may also include a remote plasma system operable to generate a plasma outside the interior of the processing chamber. In addition, the systems may include a first process gas channel operable to transport a first process gas from the remote plasma system to the interior of the processing chamber, and a second process gas channel operable to transport a second process gas that is not treated by the remote plasma system. The second process gas channel has a distal end that opens into the interior of the processing chamber, and that is at least partially surrounded by the first process gas channel. | 11-12-2009 |
20090280650 | FLOWABLE DIELECTRIC EQUIPMENT AND PROCESSES - Methods of depositing and curing a dielectric material on a substrate are described. The methods may include the steps of providing a processing chamber partitioned into a first plasma region and a second plasma region, and delivering the substrate to the processing chamber, where the substrate occupies a portion of the second plasma region. The methods may further include forming a first plasma in the first plasma region, where the first plasma does not directly contact with the substrate, and depositing the dielectric material on the substrate to form a dielectric layer. One or more reactants excited by the first plasma are used in the deposition of the dielectric material. The methods may additional include curing the dielectric layer by forming a second plasma in the second plasma region, where one or more carbon-containing species is removed from the dielectric layer. | 11-12-2009 |
20100013572 | APPARATUS FOR MULTIPLE FREQUENCY POWER APPLICATION - Apparatus and methods are provided for a power matching apparatus for use with a processing chamber. In one aspect of the invention, a power matching apparatus is provided including a first RF power input coupled to a first adjustable capacitor, a second RF power input coupled to a second adjustable capacitor, a power junction coupled to the first adjustable capacitor and the second adjustable capacitor, a receiver circuit coupled to the power junction, a high voltage filter coupled to the power junction and the high voltage filter has a high voltage output, a voltage/current detector coupled to the power junction and a RF power output connected to the voltage/current detector. | 01-21-2010 |
20100098882 | PLASMA SOURCE FOR CHAMBER CLEANING AND PROCESS - Apparatus and methods for processing a substrate and processing a process chamber are provided. In one embodiment, an apparatus is provided for processing a substrate including a power source, a switch box coupled to the power source and the switch box having a switch interchangeable between a first position and a second position, a first match box coupled to the switch box, a plasma generator coupled to the first match box, a second match box coupled to the switch box, and a remote plasma source coupled to the second match box. | 04-22-2010 |
20110011338 | FLOW CONTROL FEATURES OF CVD CHAMBERS - Apparatus and methods for gas distribution assemblies are provided. In one aspect, a gas distribution assembly is provided comprising an annular body comprising an annular ring having an inner annular wall, an outer wall, an upper surface, and a bottom surface, an upper recess formed into the upper surface, and a seat formed into the inner annular wall, an upper plate positioned in the upper recess, comprising a disk-shaped body having a plurality of first apertures formed therethrough, and a bottom plate positioned on the seat, comprising a disk-shaped body having a plurality of second apertures formed therethrough which align with the first apertures, and a plurality of third apertures formed between the second apertures and through the bottom plate, the bottom plate sealingly coupled to the upper plate to fluidly isolate the plurality of first and second apertures from the plurality of third apertures. | 01-20-2011 |
20110045676 | REMOTE PLASMA SOURCE SEASONING - Methods of seasoning a remote plasma system are described. The methods include the steps of flowing a silicon-containing precursor into a remote plasma region to deposit a silicon containing film on an interior surface of the remote plasma system. The methods reduce reactions with the seasoned walls during deposition processes, resulting in improved deposition rate, improved deposition uniformity and reduced defectivity during subsequent deposition. | 02-24-2011 |
20110114601 | PLASMA SOURCE DESIGN - Embodiments of the present invention generally provide a plasma source apparatus, and method of using the same, that is able to generate radicals and/or gas ions in a plasma generation region that is symmetrically positioned around a magnetic core element by use of an electromagnetic energy source. In general, the orientation and shape of the plasma generation region and magnetic core allows for the effective and uniform coupling of the delivered electromagnetic energy to a gas disposed in the plasma generation region. In general, the improved characteristics of the plasma formed in the plasma generation region is able to improve deposition, etching and/or cleaning processes performed on a substrate or a portion of a processing chamber that is disposed downstream of the plasma generation region. | 05-19-2011 |
20110115378 | PLASMA SOURCE DESIGN - Embodiments of the present invention generally provide a plasma source apparatus, and method of using the same, that is able to generate radicals and/or gas ions in a plasma generation region that is symmetrically positioned around a magnetic core element by use of an electromagnetic energy source. In general, the orientation and shape of the plasma generation region and magnetic core allows for the effective and uniform coupling of the delivered electromagnetic energy to a gas disposed in the plasma generation region. In general, the improved characteristics of the plasma formed in the plasma generation region is able to improve deposition, etching and/or cleaning processes performed on a substrate or a portion of a processing chamber that is disposed downstream of the plasma generation region. | 05-19-2011 |
20110165347 | DIELECTRIC FILM FORMATION USING INERT GAS EXCITATION - Methods of forming a silicon-and-nitrogen-containing layers and silicon oxide layers are described. The methods include the steps of mixing a carbon-free silicon-containing precursor with plasma effluents, and depositing a silicon-and-nitrogen-containing layer on a substrate. The silicon-and-nitrogen-containing layers may be made flowable or conformal by selection of the flow rate of excited effluents from a remote plasma region into the substrate processing region. The plasma effluents are formed in a plasma by flowing inert gas(es) into the plasma. The silicon-and-nitrogen-containing layer may be converted to a silicon-and-oxygen-containing layer by curing and annealing the film. | 07-07-2011 |
20110291771 | APPARATUS FOR MULTIPLE FREQUENCY POWER APPLICATION - Apparatus and methods are provided for a power matching apparatus for use with a processing chamber. In one aspect of the invention, a power matching apparatus is provided including a first RF power input coupled to a first adjustable capacitor, a second RF power input coupled to a second adjustable capacitor, a power junction coupled to the first adjustable capacitor and the second adjustable capacitor, a receiver circuit coupled to the power junction, a high voltage filter coupled to the power junction and the high voltage filter has a high voltage output, a voltage/current detector coupled to the power junction and a RF power output connected to the voltage/current detector. | 12-01-2011 |
20120180954 | SEMICONDUCTOR PROCESSING SYSTEM AND METHODS USING CAPACITIVELY COUPLED PLASMA - Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit. | 07-19-2012 |
20130082197 | SEMICONDUCTOR PROCESSING SYSTEM AND METHODS USING CAPACITIVELY COUPLED PLASMA - Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit. | 04-04-2013 |
20130153148 | SEMICONDUCTOR PROCESSING SYSTEM AND METHODS USING CAPACITIVELY COUPLED PLASMA - Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit. | 06-20-2013 |
20140057447 | SEMICONDUCTOR PROCESSING WITH DC ASSISTED RF POWER FOR IMPROVED CONTROL - Semiconductor processing systems are described including a process chamber. The process chamber may include a lid assembly, grid electrode, conductive insert, and ground electrode. Each component may be coupled with one or more power supplies operable to produce a plasma within the process chamber. Each component may be electrically isolated through the positioning of a plurality of insulation members. The one or more power supplies may be electrically coupled with the process chamber with the use of switching mechanisms. The switches may be switchable to electrically couple the one or more power supplies to the components of the process chamber. | 02-27-2014 |
20140097270 | CHEMICAL CONTROL FEATURES IN WAFER PROCESS EQUIPMENT - Gas distribution assemblies are described including an annular body, an upper plate, and a lower plate. The upper plate may define a first plurality of apertures, and the lower plate may define a second and third plurality of apertures. The upper and lower plates may be coupled with one another and the annular body such that the first and second apertures produce channels through the gas distribution assemblies, and a volume is defined between the upper and lower plates. | 04-10-2014 |
20140141621 | DRY-ETCH SELECTIVITY - A method of etching exposed patterned heterogeneous structures is described and includes a remote plasma etch formed from a reactive precursor. The plasma power is pulsed rather than left on continuously. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents selectively remove one material faster than another. The etch selectivity results from the pulsing of the plasma power to the remote plasma region, which has been found to suppress the number of ionically-charged species that reach the substrate. The etch selectivity may also result from the presence of an ion suppression element positioned between a portion of the remote plasma and the substrate processing region. | 05-22-2014 |
20150013793 | FLOW CONTROL FEATURES OF CVD CHAMBERS - Apparatus and methods for gas distribution assemblies are provided. In one aspect, a gas distribution assembly is provided comprising an annular body comprising an annular ring having an inner annular wall, an outer wall, an upper surface, and a bottom surface, an upper recess formed into the upper surface, and a seat formed into the inner annular wall, an upper plate positioned in the upper recess, comprising a disk-shaped body having a plurality of first apertures formed therethrough, and a bottom plate positioned on the seat, comprising a disk-shaped body having a plurality of second apertures formed therethrough which align with the first apertures, and a plurality of third apertures formed between the second apertures and through the bottom plate, the bottom plate sealingly coupled to the upper plate to fluidly isolate the plurality of first and second apertures from the plurality of third apertures. | 01-15-2015 |
Patent application number | Description | Published |
20090301896 | PROCESS FOR DERIVATIZING CARBON NANOTUBES WITH DIAZONIUM SPECIES AND COMPOSITIONS THEREOF - Methods for the chemical modification of carbon nanotubes involve the derivatization of multi- and single-wall carbon nanotubes, including small diameter (ca. 0.7 nm) single-wall carbon nanotubes, with diazonium species. The method allows the chemical attachment of a variety of organic compounds to the side and ends of carbon nanotubes. These chemically modified nanotubes have applications in polymer composite materials, molecular electronic applications, and sensor devices. The methods of derivatization include electrochemical induced reactions, thermally induced reactions, and photochemically induced reactions. Moreover, when modified with suitable chemical groups, the derivatized nanotubes are chemically compatible with a polymer matrix, allowing transfer of the properties of the nanotubes (such as, mechanical strength or electrical conductivity) to the properties of the composite material as a whole. Furthermore, when modified with suitable chemical groups, the groups can be polymerized to form a polymer that includes carbon nanotubes. | 12-10-2009 |
20090318664 | LOW PROFILE LUBRICANT WITH CYCLOPHOSPHAZENE RING ATTACHED - A compound comprising a backbone with a perfluoropolyether chain. The compound also has one or more cyclophosphazene rings attached to or incorporated into the backbone. The compound further includes at least two functional groups attached to the backbone, attached to the one or more cyclophosphazene rings, or a combination thereof. | 12-24-2009 |
20100006595 | VACUUM SPRAY COATING OF LUBRICANT FOR MAGNETIC RECORDING MEDIA - Processing equipment for manufacturing magnetic recording medium comprising a chamber, a micro-dispensing valve that can open for a minimum time of less than a few microseconds and can dispense a liquid in an amount of a micro-liter or less each time that the micro-dispensing valve is opened, wherein the liquid comprising a lubricant and a solvent different from the lubricant is dispensed through the micro-dispensing valve. | 01-14-2010 |
20100035083 | MIXTURE OF LOW PROFILE LUBRICANT AND CYCLOPHOSPHAZENE COMPOUND - A composition comprising a mixture of a low profile lubricant and a compound comprising one or more cyclophosphazene rings. The low profile lubricant comprises a perfluoropolyether backbone, at least one functional group on each end of the backbone and at least one functional group located in a region of the backbone between the ends. Also a device comprising a magnetic disk and the composition on the magnetic disk. | 02-11-2010 |
20110117386 | MEDIA LUBRICANT FOR HIGH TEMPERATURE APPLICATION - A lubricant layer for a magnetic recording medium may include a perfluoropolyether having monomer units and end groups selected to provide high thermal stability and good reliability. | 05-19-2011 |
20110205665 | COVALENTLY BOUND MONOLAYER FOR A PROTECTIVE CARBON OVERCOAT - A magnetic data storage medium may include a substrate, a magnetic recording layer, a protective carbon overcoat, and a monolayer covalently bound to carbon atoms adjacent a surface of the protective carbon overcoat. According to this aspect of the disclosure, the monolayer comprises at least one of hydrogen, fluorine, nitrogen, oxygen, and a fluoro-organic molecule. In some embodiments, a surface of a read and recording head may also include a monolayer covalently bound to carbon atoms of a protective carbon overcoat. | 08-25-2011 |
20110262633 | LUBRICANT DEPOSITION ONTO MAGNETIC MEDIA - A method, in one embodiment, can include pumping a gas into a reservoir that includes a lubricant. In addition, the method can include changing the gas into a supercritical fluid that extracts lubricant molecules from the lubricant resulting in a mixture of the supercritical fluid and the lubricant molecules. Furthermore, the method can include utilizing the mixture to deposit a lubricant molecule onto a magnetic media. | 10-27-2011 |
20120219826 | LUBRICANT FOR HEAT ASSISTED MAGNETIC RECORDING - Compositions for use in lubricating thin film storage media are provided, as well as storage media formed using the compositions, the compositions including one or more central cores having a cyclic group, and a plurality of arms extending from the central cores, wherein each arm comprises phenol or piperonyl. Methods of preparing the compositions are also provided. Methods of preparing storage media that incorporate the compositions therein are further provided. | 08-30-2012 |
20120251843 | LUBRICANT COMPOSITIONS - Compositions including one or more a central cores having a cyclic group, and a plurality of arms extending from the central cores, wherein the arms comprise perfluoropolyethers (PFPEs) or its derivatives. Methods of preparing the compositions are also provided. Methods of preparing storage media that incorporate the compositions therein are further provided. | 10-04-2012 |
20130337194 | COVALENTLY BOUND MONOLAYER FOR A PROTECTIVE CARBON OVERCOAT - A magnetic data storage medium may include a substrate, a magnetic recording layer, a protective carbon overcoat, and a monolayer covalently bound to carbon atoms adjacent a surface of the protective carbon overcoat. According to this aspect of the disclosure, the monolayer comprises at least one of hydrogen, fluorine, nitrogen, oxygen, and a fluoro-organic molecule. In some embodiments, a surface of a read and recording head may also include a monolayer covalently bound to carbon atoms of a protective carbon overcoat. | 12-19-2013 |
20140141284 | LUBRICANT COMPOSITIONS - A compound of Formula (I) includes: [L] | 05-22-2014 |
Patent application number | Description | Published |
20120110244 | COPYBACK OPERATIONS - Methods and systems for copyback operations are described. One or more methods include reading data from a first memory unit of a memory device responsive to a copyback command, performing signal processing on the data using a signal processing component local to the memory device, and programming the data to a second memory unit of the memory device. | 05-03-2012 |
20130268701 | MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS - The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels. | 10-10-2013 |
20130283124 | DATA INTEGRITY IN MEMORY CONTROLLERS AND METHODS - The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface. | 10-24-2013 |
20140059405 | SOLID-STATE DRIVE RETENTION MONITOR USING REFERENCE BLOCKS - A solid-state storage retention monitor determines whether user data in a solid-state device is in need of a scrubbing operation. One or more reference blocks may be programmed with a known data pattern, wherein the reference block(s) experiences substantially similar P/E cycling, storage temperature, storage time, and other conditions as the user blocks. The reference blocks may therefore effectively represent data retention properties of the user blocks and provide information regarding whether/when a data refreshing operation is needed. | 02-27-2014 |
20140133220 | METHODS AND DEVICES FOR AVOIDING LOWER PAGE CORRUPTION IN DATA STORAGE DEVICES - A data storage device may comprise a plurality of Multi-Level Cell (MLC) non-volatile memory devices comprising a plurality of lower pages and a corresponding plurality of higher-order pages. A controller may be configured to write data to and read data from the plurality of lower pages and the corresponding plurality of higher-order pages. A buffer may be coupled to the controller, which may be configured to accumulate data to be written to the MLC non-volatile memory devices, allocate space in the buffer and write the accumulated data to the allocated space. At least a portion of the accumulated data may be written in a lower page of the MLC non-volatile memory devices and the space in the buffer that stores data written to the lower page may be de-allocated when all higher-order pages corresponding to the lower page have been written in the MLC non-volatile memory devices. | 05-15-2014 |
20140164870 | SYSTEM AND METHOD FOR LOWER PAGE DATA RECOVERY IN A SOLID STATE DRIVE - In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller performs a method that efficiently resolves the lower page corruption problem. In one embodiment, the method selects programmed lower page(s) for which paired upper page(s) have not been programmed, reads data from those selected lower page(s), corrects the read data, and reprograms the read data into those lower page(s). Since the number of lower pages in this condition is typically low (e.g., several pages in a block with hundreds or thousands of pages), this is a much more efficient method than reprogramming the entire block. In another embodiment, a similar reprogramming method is applied as a data recovery scheme in situations in which only lower pages are programmed (e.g., SLC memory, MLC memory in SLC mode, etc.). | 06-12-2014 |
20140169102 | LOG-LIKELIHOOD RATIO AND LUMPED LOG-LIKELIHOOD RATIO GENERATION FOR DATA STORAGE SYSTEMS - An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) for upper and lower pages of memory cells in MLC solid-state media. Disclosed are systems and methods for generating lumped-LLR for upper pages, wherein at least some voltage threshold reads are linked together in order to reduce the number of reads. Efficiency and reliability are thereby improved. | 06-19-2014 |
20140310431 | MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS - The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels. | 10-16-2014 |
Patent application number | Description | Published |
20090066597 | Substrate Integrated Waveguide Antenna Array - A substrate integrated waveguide (SIW) slot full-array antenna fabricated employing printed circuit board technology. The SIW slot full-array antenna using either single or multi-layer structures greatly reduces the overall height and physical steering requirements of a mobile antenna when compared to a conventional metallic waveguide slot array antenna. The SIW slot full-array antenna is fabricated using a low-loss dielectric substrate with top and bottom metal plating. An array of radiating cross-slots is etched in to the top plating to produce circular polarization at a selected tilt-angle. Lines of spaced-apart, metal-lined vias form the sidewalls of the waveguides and feeding network. In multi-layer structures, the adjoining layers are coupled by transverse slots at the interface of the two layers. | 03-12-2009 |
20110025566 | NEAR-HORIZON ANTENNA STRUCTURE AND FLAT PANEL DISPLAY WITH INTEGRATED ANTENNA STRUCTURE - A near-horizon antenna structure includes an upper radiating element having a straight conductive trace disposed on a planar surface of a non-conductive substrate, a rectangular lower radiating element serving as a ground plane disposed on the planar surface, and a feed point provided between the upper and lower radiating elements. When the planar surface is positioned vertically, the far-field effects of horizontal current flowing in opposite directions on the radiating elements cancel to provide an antenna pattern with increased gain in horizontal directions and reduced gain in vertical directions. A flat panel display and a portable communication device are also provided with one or more near-horizon antenna structures integrated therein. | 02-03-2011 |
20110032157 | MULTIPROTOCOL ANTENNA STRUCTURE AND METHOD FOR SYNTHESIZING A MULTIPROTOCOL ANTENNA PATTERN - Embodiments of a planar asymmetric antenna structure with shifted feed position for multi-protocol operations are disclosed The antenna structure includes two elliptically tapering right and left arms, each with a different radius, and an off-center feed point positioned between the right and left arms. One arm has a smaller elliptical tapering than the other arm and the feed point is positioned closer to one arm than the other arm. A method of synthesizing a multiprotocol antenna pattern is also disclosed. The method includes providing substantially equally surface currents on both arms of an antenna structure to generate a near-horizontal pattern in far-field at a lower frequency band, providing greater surface currents on the right arm to generate a far-field pattern with a large horizontal component at a higher frequency band, and providing greater surface currents on the left arm to generate an asymmetric far-field pattern at a middle frequency band. | 02-10-2011 |
20110034130 | METHOD AND SYSTEM FOR DETERMINING TOTAL ISOTROPIC SENSITIVITY USING RSSI MEASUREMENTS FOR WIMAX DEVICE CERTIFICATION - Embodiments of a system and method of determining total isotropic sensitivity (TIS) of a wireless broadband client device are described herein. A received signal strength indicator (RSSI) reported at an embedded radio module of the device is logged for each of a plurality of antenna polarizations and for each of a plurality of platform orientations. A single point measurement of module sensitivity is performed at a reference orientation and polarization the transmit antenna. The TIS is calculated as a correction to the single point measurement of module sensitivity. A correction factor to correct the TIS may be based on the difference between an average of the logged RSSIs and an RSSI at the reference orientation and polarization of the transmit antenna. | 02-10-2011 |
20110111709 | Radio frequency filtering in coaxial cables within a computer system - Embodiments and methods and means for filtering radio frequencies (RF) via coaxial cables with a computer system are provided. Such embodiments generally include modifying an RF coaxial cables communicatively coupling an antenna to a wireless radio module within a mobile computing device allow an RF signal within certain frequency band(s) to pass with minimal attenuation while other frequencies, the RF signal is either reflected or attenuated. Modifying the RF coaxial cable entails inserting sections of varied impedance into the uniform impedance of the RF coaxial cable by altering the mechanical structure of the RF coaxial cable. | 05-12-2011 |
20110154656 | SYSTEMS AND METHODS FOR MANUFACTURING MODIFIED IMPEDANCE COAXIAL CABLES - Systems and methods for manufacturing modified impedance coaxial cables including providing a coaxial cable having an inner conductor, a dielectric layer at least partially covering an outer surface of the inner conductor, and an outer conductor at least partially covering an outer surface of the dielectric layer. The coaxial cable may include a first section having a first impedance configured to allow a first frequency band to pass. A discontinuity section may be formed in at least one of the inner conductor, the dielectric layer, and the outer conductor. The discontinuity section may have an impedance different than the first impedance and a length which is configured to attenuate a second frequency band. | 06-30-2011 |
20120082068 | APPARATUSES, SYSTEMS AND METHODS USING MULTI-FUNCTIONAL ANTENNAS INCORPORATING IN-LINE-FILTER ASSEMBLIES - Embodiments herein may provide an apparatus, comprising an antenna, the antenna including a same radiating element fed by more than one in-line-filter cables with complimentary pass and rejection bands, wherein the more than one in-line-filter cables have periodically inserted discontinuities in coaxial cables to create band rejection filter functionalities. | 04-05-2012 |
20120133561 | METHOD AND APPARATUS FOR IN-MOLD LAMINATE ANTENNAS - Embodiments of systems and methods for providing in-mold laminate antennas are generally described herein. Other embodiments may be described and claimed. | 05-31-2012 |
20120133565 | CABLE ANTENNA APPARATUS AND SYSTEM - Embodiments of an apparatus and system are described for a coaxial antenna. An apparatus may comprise, for example, an integrated circuit and a coaxial cable coupled to the integrated circuit and arranged to operate as an antenna, the coaxial cable comprising an inner conductor layer and at least one insulator layer, wherein one or more portions of the inner conductor layer are exposed to allow the exposed inner conductor layer to operate as a radiating element for the antenna. Other embodiments are described and claimed. | 05-31-2012 |
20120153739 | RANGE ADAPTATION MECHANISM FOR WIRELESS POWER TRANSFER - In accordance with various aspects of the disclosure, a method and apparatus is disclosed that includes features of a switching mechanism coupled to a wireless power transmitting device, wherein the switching mechanism is configured to selectively control operation of a transmitting coil in the wireless power transmitting device. | 06-21-2012 |
20120154687 | Multi-band tunable antenna for integrated digital television service on mobile devices - A multi-band tunable antenna is implemented on device, where the multi-band tunable antenna supports both VHF and UHF frequencies at the same time, and particularly digital television frequencies. The multi-band tunable antenna includes a tunable component that connects metallic radiating elements. Changing the electrical property, such as capacitance, of the tunable component, changes the ability to receive particular frequencies. | 06-21-2012 |
20120162024 | INTEGRATED ANTENNA ASSEMBLY - An antenna assembly comprises a computer expansion card comprising a metallic layer which forms a radiating element or a metallic shield which forms the radiating element and a feed line coupled to the radiating element. Other embodiments may be described. | 06-28-2012 |
20120162032 | ANTENNA INTEGRATED INTO A TOUCH SENSOR OF A TOUCHSCREEN DISPLAY - A touch sensor with a transparent conductive layer and a metalized border area at least partially bordering the transparent conductive layer and forming a far-field antenna. | 06-28-2012 |
20120248883 | RECONFIGURABLE COIL TECHNIQUES - Techniques are disclosed involving reconfigurable coils. Such coils may be used in applications, including (but not limited to) wireless charging and near field communications (NFC). For instance, a reconfigurable coil may include a first conductive portion and a second conductive portion. Two or more configurations may be established. These configurations may correspond to particular current paths. For example, in a circular configuration, a path is provided having the same rotational sense in both first and second conductive portions. However, in a figure eight configuration, a path is provided having a first rotational sense in the first conductive portion and a second rotational sense in the second conductive portion. A switch coupled between these portions may set the coil's configuration. Configurations may be selected based on one or more operating conditions involving the coil. | 10-04-2012 |
20120250539 | TECHNIQUES TO DETERMINE USER PRESENCE - An embodiment of the present invention provides a method of detecting user presence, comprising registering a client associated with the user on a host associated with the user and setting up a wireless communication pairing, wherein while setting up the pairing, the client measures the host wireless communication power and uses it as calibration threshold for distance detection, and wherein the client measures a beacon power of the host radio and when the beacon power is above a threshold, the client is determined to be proximate to the host. | 10-04-2012 |
20130163453 | PRESENCE SENSOR WITH ULTRASOUND AND RADIO - An ultrasound and radio frequency technology is used to implement presence sensor capability for wireless devices such as, a laptap device. For example, the laptap device connects to a station device through a WiFi signal. In this example, the WiFi signal may include a data packet that synchronizes internal clocks of the laptap device with the station device. Further, the data packet may include transmitting time information for an ultrasound audio signal generated by the station device. The ultrasound audio signal is received by the laptap device that calculates time of flight (TOF) of the ultrasound audio signal. The TOF may be used to determine actual distance of the wireless device (e.g., laptap device) to the station device. | 06-27-2013 |
20130271073 | COIL TECHNIQUES - Techniques are disclosed involving coils that may be used to exchange wireless energy between devices. For instance, a device may include a coil having a plurality of turns arranged along an arc. Further, the coil may have first and second ends that are substantially normal to the arc. The coil may be arranged within a casing of the device. This casing may have first and second non-parallel surfaces. In embodiments, the first end of the coil may be directed to (be substantially parallel with and proximate to) the first surface, while the second end of the coil may be directed to the substantially parallel with and proximate to) the second surface. The coil may be employed in wireless power transfer and/or near field communication applications. | 10-17-2013 |
20130335284 | EDGE-EMITTING ANTENNAS FOR ULTRA SLIM WIRELESS MOBILE DEVICES - Described herein are techniques related to near field coupling and wireless power transfers. A mobile device may include an edge-emitting antenna that offers ultra slim, all-metallic chassis packaging option with no cutout, uses lesser area, has robust mechanical strength, and provides EMI/ESD protection. In one example, an inductor coil is wrapped around a magnetic core and a pair of conductive layers is configured to interpose the magnetic core and the inductor coil between them to expose an edge of the magnetic core. The inductor coil being operable in a transmit mode to generate a magnetic field in response to a current passing through it. The edge is configured to enhance outward radiation of the magnetic field. Based on simulation results, the edge-emitting antenna occupies less space and provides an acceptable level of performance for coupling coefficients compared to conventional antenna. | 12-19-2013 |
20140002225 | SPIRAL NEAR FIELD COMMUNICATION (NFC) COIL FOR CONSISTENT COUPLING WITH DIFFERENT TAGS AND DEVICES | 01-02-2014 |
20140002305 | PATCH-BASED PROXIMITY SENSORS, ANTENNAS, AND CONTROL SYSTEMS TO CONTROL ANTENNAS BASED ON CORRESPONDING PROXIMITY MEASURES | 01-02-2014 |
20140002313 | THIN CHASSIS NEAR FIELD COMMUNICATION (NFC) ANTENNA INTEGRATION | 01-02-2014 |
20140065956 | NEAR FIELD COUPLING SOLUTIONS FOR WI-FI BASED WIRELESS DOCKING - Described herein are techniques related one or more systems, apparatuses, methods, etc. for a wireless fidelity (Wi-Fi) based wireless docking in an enterprise environment. In an implementation, a separate low radiating antenna is constructed and installed at a bottom surface of a wireless device and at a docking surface of a docking station. In this implementation, the low radiating antenna is configured to provide local wireless communication (i.e., Wi-Fi based communication) between a docking pair that includes the wireless device and the docking station. | 03-06-2014 |
20140078094 | CO-EXISTENCE OF TOUCH SENSOR AND NFC ANTENNA - When threshold values for the capacitive sensors in a touch pad are periodically updated to allow for drift in these values, the updating process may be suspended while a nearby radio antenna is transmitting. Such transmissions from an antenna that is located next to the touch pad could otherwise significantly alter the effective capacitance in these sensors and thereby make the touch pad unreliable for registering a touch. Even though the capacitance may return to normal fairly quickly after the transmission stops, the moving average technique typically used to smooth out short term variation may incorporate the period of changed capacitance and thereby extend the period of unreliability, but suspending the update process during a transmission can avoid this problem. | 03-20-2014 |
20140080411 | INTEGRATION OF A NEAR FIELD COMMUNICATION COIL ANTENNA BEHIND A SCREEN DISPLAY FOR NEAR FIELD COUPLING - Described herein are architectures, platforms and methods for integrating near field communication (NFC) coil antenna behind a screen display of devices and more particularly, to improve near field coupling capabilities of the devices by configuring the screen display to implement a context based software logo to guide a user. The context based software logo displays a tapping area location during NFC related functions. The NFC related functions include wireless power transfer (WPT) and/or near field communications (NFC) capabilities of the devices | 03-20-2014 |
20140092543 | KEYBOARD INTEGRATED NFC ANTENNA - A metal baseboard with a planar shape which is placed close to a Near Field Communication (NFC) radio antenna may be configured with a number of slots in the metal. These slots may disrupt the eddy current that would otherwise be induced in the metal by magnetic emissions emanating from the NFC antenna. The reduction in eddy current that results from these slots may reduce the severe attenuation of the signal that would otherwise be caused by the metal. In general, each slot may run approximately perpendicular to the direction of the expected eddy current. This may be approximated by having many of the slots each run perpendicular to the nearest part of the antenna wiring. | 04-03-2014 |
20140129425 | DYNAMIC BOOST OF NEAR FIELD COMMUNICATIONS (NFC) PERFORMANCE/COVERAGE IN DEVICES - Described herein are architectures, platforms and methods for dynamic amplification/boosting of near field communications (NFC) antenna transmission power in a device during NFC related functions that require increase in an NFC antenna transmission power such as a payment transaction. For example, to comply with Europay MasterCard and Visa (EMVco) standards with regard to higher NFC antenna transmission power during the EMVco transactions, the NFC antenna transmission power may be dynamically controlled to maximize efficiency of a battery/power supply of the device. | 05-08-2014 |
20140159848 | CASCADED COILS FOR MULTI-SURFACE COVERAGE IN NEAR FIELD COMMUNICATION - Described herein are techniques related to near field coupling and wireless power transfers. A device may include a cascaded coil antenna to include a first coil antenna that is connected in series with a second coil antenna. The first and second coil antennas are independent antennas prior to cascading and are located in different surfaces of the device to establish near field coupling through front side, top side, bottom side, or corner side of the portable device. Furthermore, a flux guide may be placed in the cascaded coil antenna to facilitate magnetic flux at the first coil antenna and the second coil antenna to induce current of the same phase during receive mode. During transmit mode, the flux guide facilitates the magnetic flux at the first coil antenna and the second coil antenna to generate magnetic fields of the same direction. | 06-12-2014 |
20140176054 | WIRELESS CHARGING OPTIMIZATION - Described herein are techniques related to near field coupling and wireless charging or wireless power transfer (WPT). More particularly, an induced current at a receiving coil antenna is measured and utilized as a basis for re-alignment with a transmitting coil antenna is described. | 06-26-2014 |
20140195198 | AGGREGATING AND PROCESSING DISTRIBUTED DATA ON ULTRA-VIOLET (UV) EXPOSURE MEASUREMENT - The present application discloses devices, systems and methods for establishing and utilizing a UV sensing network to harness the efficacy of distributed UV sensing to produce improved accuracy of UV exposure measurement using mobile devices. This may be accomplished by “crowd sourcing”, i.e. having multiple devices work collaboratively to measure the UV exposure. The collaboration can be implemented in many potential ways, such as, using a server based architecture where devices connect to a specific “UV measurements server” to provide measurements and receive aggregate estimated exposure levels, and/or by using a peer-to-peer architecture, where devices in a specific region creates a local ad-hoc UV sensing network. | 07-10-2014 |
20140203988 | INTEGRATED ANTENNAS FOR NEAR FIELD COUPLING INTEGRATION - Described herein are techniques related to near field coupling and wireless power transfers. In an implementation, a portable device may include full metallic chassis devices. The full metallic chassis devices may include a keyboard and/or trackpad that include a plastic keycap. The plastic keycap may integrate a booster component to increase near field communications (NFC) range of a coil antenna that is integrated onto a surface plane above a circuit board of a switch that is connected to the plastic keycap. In an implementation, a ferrite material is inserted between the coil antenna and the circuit board to protect the coil antenna from Eddy currents that may be induced on a metallic chassis that lie underneath the circuit board. | 07-24-2014 |
20140203990 | DISSYMMETRIC COIL ANTENNA TO FACILITATE NEAR FIELD COUPLING - Described herein are techniques related to near field coupling and wireless power transfers. For example, a coil antenna configuration is the same in all portable devices; however, when the portable devices are arranged in back to back position with one another, the coil antenna configuration defines a dissymmetric and antenna configuration. | 07-24-2014 |
20140220887 | NEAR FIELD COMMUNICATIONS (NFC) AND PROXIMITY SENSOR FOR PORTABLE DEVICES - Described herein are techniques related to near field coupling and proximity sensing operations. For example, a proximity sensor uses a coil antenna that is utilized for near field communications (NFC) functions. The proximity sensor may be integrated into an NFC module to form a single module. | 08-07-2014 |
20140232334 | RECONFIGURABLE COIL TECHNIQUES - Techniques are disclosed involving reconfigurable coils. Such coils may be used in applications, including (but not limited to) wireless charging and near field communications (NFC). For instance, a reconfigurable coil may include a first conductive portion and a second conductive portion. Two or more configurations may be established. These configurations may correspond to particular current paths. For example, in a circular configuration, a path is provided having the same rotational sense in both first and second conductive portions. However, in a figure eight configuration, a path is provided having a first rotational sense in the first conductive portion and a second rotational sense in the second conductive portion. A switch coupled between these portions may set the coil's configuration. Configurations may be selected based on one or more operating conditions involving the coil. | 08-21-2014 |
20140269977 | WIRELESS DEVICE AND METHOD FOR ANTENNA SELECTION - Embodiments, such as apparatus or techniques may include circuitry for a portable wireless device. In an embodiment, a tissue proximity detection circuit may be configured to provide information indicative of a presence or absence of human tissue within a specified range of a first antenna, and an antenna control circuit may be configured to controllably inhibit transmission by the first antenna, and to permit transmission by a second antenna, in response to information provided by the tissue proximity detection circuit that tissue is present within the specified range of the first antenna. | 09-18-2014 |
20140333489 | METHOD AND APPARATUS FOR IN-MOLD LAMINATE ANTENNAS - Embodiments of systems and methods for providing in-mold laminate antennas are generally described herein. Other embodiments may be described and claimed. | 11-13-2014 |
20140346886 | ANTENNA CONFIGURATION TO FACILITATE NEAR FIELD COUPLING - Described herein are techniques related to near field coupling and wireless power transfers. A portable device may include a coil antenna that includes an upper loop and a lower loop to form a figure-eight arrangement. The figure-eight coil antenna arrangement is wrapped against top and bottom surfaces of a component to establish near field coupling through front side, top side, bottom side, or corner side of the portable device. Further, a flux guide may be placed between the coil antenna and the component to facilitate magnetic flux at the upper loop and the lower loop to induce current of the same phase during receive mode. During transmit mode, the flux guide facilitates the magnetic flux at the upper loop and the lower loop to generate magnetic fields of the same direction. | 11-27-2014 |
20140362837 | ANTENNA COUPLER FOR NEAR FIELD WIRELESS DOCKING - Described herein are techniques related to one or more systems, apparatuses, methods, etc. for a wireless fidelity (Wi-Fi) based wireless docking station arrangement. | 12-11-2014 |
20150035474 | INTEGRATION OF WIRELESS CHARGING UNIT IN A WIRELESS DEVICE - Described herein are techniques related to one or more systems, apparatuses, methods, etc. for implementing a wireless charging and a wireless connectivity in a device. | 02-05-2015 |
20150044963 | NEAR FIELD COMMUNICATIONS (NFC) COIL WITH EMBEDDED WIRELESS ANTENNA - Described herein are techniques related to near field coupling and WLAN dual-band operations. For example, a WLAN dual-band utilizes the same coil antenna that is utilized for near field communications (NFC) functions. The WLAN dual-band may be integrated into an NFC module to form a single module. | 02-12-2015 |
Patent application number | Description | Published |
20080266926 | TRANSFER OF NON-ASSOCIATED INFORMATION ON FLASH MEMORY DEVICES - Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are active based on if the bitlines are associated with the currently used storage unit. | 10-30-2008 |
20090147587 | CIRCUIT PRE-CHARGE TO SENSE A MEMORY LINE - Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement as a variable resistor that modifies value to compensate for temperature. The leakage component can include a capacitor configuration that allows voltage to pass. | 06-11-2009 |
20100215139 | COUNTERS AND EXEMPLARY APPLICATIONS - Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C | 08-26-2010 |
20100259311 | LEVEL SHIFTERS, INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR OPERATING THE LEVEL SHIFTERS - A level shifter includes an input end being capable of receiving an input voltage signal. The input voltage signal includes a first state transition from a first voltage state to a second voltage state. An output end can output an output voltage signal having a second state transition from a third voltage state to the second voltage state corresponding to the first state transition of the input voltage signal. A driver stage is coupled between the input end and the output end. The driver stage includes a first transistor and a second transistor. Substantially immediately from a time corresponding to about a mean of voltage levels of the first voltage state and the second voltage state, the second voltage state is substantially free from being applied to a gate of the first transistor so as to substantially turn off the first transistor. | 10-14-2010 |
20110001557 | VOLTAGE REFERENCE CIRCUIT WITH TEMPERATURE COMPENSATION - A voltage reference circuit with temperature compensation includes a power supply, a reference voltage supply, a first PMOS transistor with its source connected to the power supply voltage, a second PMOS transistor with its source connected to the power supply and its gate and drain connected to the first PMOS gate, a first NMOS transistor with its gate and drain connected the first PMOS drain, a second NMOS transistor with its drain connected to the second PMOS drain and its gate connected with the first NMOS gate to the reference voltage supply, a resistor connected to the second NMOS source and ground, and an op-amp with its inverting input and its output connected the first NMOS source and its non-inverting input connected to the ground. In another aspect, a voltage reference circuit output is coupled to an NMOS gate in saturation mode connected to another voltage reference circuit. | 01-06-2011 |
20110199152 | INTEGRATED CIRCUITS INCLUDING A CHARGE PUMP CIRCUIT AND OPERATING METHODS THEREOF - An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node. | 08-18-2011 |
20110199154 | AUTOMATIC LEVEL CONTROL - Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage. | 08-18-2011 |
20110199845 | REDUNDANCY CIRCUITS AND OPERATING METHODS THEREOF - A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third input/output (IO) interface and a fourth memory array coupled with a fourth IO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays. | 08-18-2011 |
20110267139 | AUTOMATIC LEVEL CONTROL - Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage. | 11-03-2011 |
20110310690 | VOLTAGE REGULATORS, MEMORY CIRCUITS, AND OPERATING METHODS THEREOF - A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator. | 12-22-2011 |
20120013374 | PHASE-LOCK ASSISTANT CIRCUITRY - Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock. | 01-19-2012 |
20120032731 | CHARGE PUMP DOUBLER - An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor. | 02-09-2012 |
20120182058 | NEGATIVE CHARGE PUMP - A charge pump includes a first node configured to receive a first voltage and a second node coupled to the first node through a first transistor. The second node is configured to output a voltage having a greater voltage magnitude than the first voltage. A first capacitor is coupled to a third node, and a fourth node is configured to receive a first clock signal. The third node is disposed between a drain of the first transistor and the fourth node. A leaky circuit device is coupled in parallel with the first capacitor for draining charges of a first polarity away from the second node. | 07-19-2012 |
20120194263 | CHARGE PUMP AND METHOD OF BIASING DEEP N-WELL IN CHARGE PUMP - A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), and is coupled to at least one capacitor, an input node, and an output node. The input node is arranged to receive an input signal. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the output node, and the DNW is arranged to float for a positive pump operation. | 08-02-2012 |
20120200323 | PHASE-LOCK ASSISTANT CIRCUITRY - A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal. | 08-09-2012 |
20120201084 | OPERATING METHODS OF FLASH MEMORY AND DECODING CIRCUITS THEREOF - A FLASH memory cell includes a control gate over a floating gate over a substrate. A wall line and an erase gate each is disposed adjacent to a respective sidewall of the control gate. A first source/drain (S/D) region is disposed in the substrate and adjacent to a sidewall of the wall line. A second S/D region is disposed in the substrate and adjacent to the sidewall of the floating gate. A method of operating the FLASH memory cell includes applying a first voltage level to the control gate. A second voltage level is applied to the word line. The second voltage level is lower than the first voltage level. A third voltage level is applied to the first S/D region. A fourth voltage level is applied to the second S/D region. The fourth voltage level is higher than the third voltage level. The erase gate is electrically floating. | 08-09-2012 |
20120223766 | INTEGRATED CIRCUITS WITH BI-DIRECTIONAL CHARGE PUMPS - Integrated circuits such as memory arrays are coupled to a bi-directional charge pump that includes an input circuit and output circuit, and one or more pump stages coupled between the input circuit and the output circuit of the bi-directional charge pump. The output circuit includes a diode having an input and output and a transistor connected to the output of the diode and a ground potential. The input of the diode is electrically connected to the pump stages in a configuration that allows the charge pump to apply a positive or negative voltage to the memory array or other load. | 09-06-2012 |
20120275249 | REDUNDANCY CIRCUITS AND OPERATING METHODS THEREOF - A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit line is configured to selectively repair the group of memory arrays. | 11-01-2012 |
20130064017 | CONCURRENT OPERATION OF PLURAL FLASH MEMORIES - A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed. | 03-14-2013 |
20130106475 | METHOD OF OPERATING PHASE-LOCK ASSISTANT CIRCUITRY | 05-02-2013 |
20130214853 | INTEGRATED CIRCUITS WITH BI-DIRECTIONAL CHARGE PUMPS - A method includes receiving a first voltage at a first input circuit of a bi-directional charge pump circuit, selectively turning on a first switch of a switching circuit that is coupled electrically to a deep N-well transistor of a first set of one or more intermediate pump stages that are coupled between the first input circuit and a first output circuit, and providing a third voltage from the first output circuit in response to receiving a second voltage at an input of a first diode of the output circuit from the first set of the one or more intermediate pump stages. | 08-22-2013 |
20140003141 | CONCURRENT OPERATION OF PLURAL FLASH MEMORIES | 01-02-2014 |
20140035553 | VOLTAGE REFERENCE CIRCUIT WITH TEMPERATURE COMPENSATION - A voltage reference circuit with temperature compensation includes a power supply, a first reference voltage supply, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a resistor connected to the second NMOS source and ground. The voltage reference circuit also includes a second reference voltage supply, a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor with a drain connected to the source of the fourth NMOS transistor, a source connected to the ground, and a gate connected to the first reference voltage output. | 02-06-2014 |
20140103967 | LEVEL SHIFTERS, METHODS FOR MAKING THE LEVEL SHIFTERS AND METHODS OF USING INTEGRATED CIRCUITS - A method of making a level shifter includes coupling a driver stage between an input end and an output end, the driver stage comprising a first transistor and a second transistor. An inverter having an input is coupled with the input end. A third transistor having a gate end is coupled with an output of the inverter, the third transistor having a terminal coupled to a pumped voltage (VPP). Additionally, the method includes coupling a fourth transistor with the output end, the fourth transistor having a terminal coupled to the pumped voltage. A fifth transistor is coupled with the input end, the fifth transistor having a terminal coupled to the third and fourth transistors. A sixth transistor is coupled with the input end, the sixth transistor having a terminal. | 04-17-2014 |
20140146613 | OPERATING METHOD OF MEMORY HAVING REDUNDANCY CIRCUITRY - In a method of operating a memory circuit, which includes a plurality of memory arrays each coupled with a corresponding input/output (IO) interface and a redundancy memory page a failing address of a failing bit cell is determined. The failing address is located in a memory page of one of the memory arrays. The method further includes repairing the failing bit cell by replacing the memory page with the redundancy memory page. | 05-29-2014 |
20140185401 | SENSING CIRCUIT, MEMORY DEVICE AND DATA DETECTING METHOD - A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage. | 07-03-2014 |
20140197881 | CHARGE PUMP AND METHOD OF BIASING DEEP N-WELL IN CHARGE PUMP - A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), a gate and a drain, and is coupled to at least one capacitor, a first node, a second node and a switch. For the at least one NMOS device, the gate is capable of receiving a different signal from the drain. The first node is arranged to receive an input signal. The switch is coupled between the at least one NMOS device and a ground. A drain of the switch is coupled to a deep N-well of the switch. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the second node. The DNW is coupled to the ground for a negative pump operation. | 07-17-2014 |
20150071002 | DYNAMIC REFERENCE CURRENT SENSING - A circuit comprises a first path, a second path, a current generating circuit, and a sense amplifier. The first path has a first current having a first current value. The second path has a second current having a second current value. The current generating circuit is configured to generate a reference current having a reference current value based on the first current value and the second current value. The sense amplifier is configured to receive a third current having a third current value and to generate a logical value based on the reference current value and the third current value. | 03-12-2015 |
Patent application number | Description | Published |
20100220730 | EFFICIENT PRUNING OF VIRTUAL SERVICES IN BRIDGED COMPUTER NETWORKS - In one embodiment, a bridge in a computer network may execute a spanning tree protocol (STP) for network topology and a registration protocol for traffic control of virtual connections (e.g., EVCs) at the bridge. For any gateway ports of the bridge inter-connected with a provider network, the bridge may generate “fake” received registration protocol join messages for a particular virtual connection at the gateway port. The bridge may then either i) propagate the join messages, in response to the gateway port being in a forwarding state according to the STP, on other forwarding ports of the bridge, or ii) in response to the gateway port not being in a forwarding state, block propagation of the join messages to other ports of the bridge. | 09-02-2010 |
20100220737 | MULTIPLE SPANNING TREE EXTENSIONS FOR TRUNK PORTS CARRYING MORE THAN 4K VIRTUAL SERVICES - In one embodiment, bridges in a computer network maintain a per-port mapping table for each of its ports, where each mapping table maps, for each virtual connection (of more than 4K) at a respective port, i) frame encapsulation fields that uniquely identify a particular virtual connection at the respective port to ii) a particular multiple spanning tree (MST) instance. The bridges may then compute a checksum of a particular mapping table for a particular port, and share the checksum with a corresponding port interconnected with the particular port (e.g., of another bridge). Upon determining that the mapping tables at the corresponding ports match in response to the checksums matching, frames may then be forwarded between the ports based on the particular mapping table. | 09-02-2010 |
20120327766 | LEVEL OF HIERARCHY IN MST FOR TRAFFIC LOCALIZATION AND LOAD BALANCING - In one embodiment, a multiple spanning tree (MST) region is defined in a network, where the MST region includes a plurality of network nodes interconnected by links. A MST cluster is defined within the MST region, where the MST cluster includes a plurality of network nodes selected from the plurality of network nodes of the MST region. A network node of the MST cluster generates one or more MST bridge protocol data units (BPDUs) that present the MST cluster as a single logical entity to network nodes of the MST region that are not included in the MST cluster, yet enables per-multiple spanning tree instance (per-MSTI) load balancing of traffic across inter-cluster links that connect network nodes included in the MST cluster and network nodes of the MST region that are not included in the MST cluster. | 12-27-2012 |
20130024580 | Transient Unpruning for Faster Layer-Two Convergence - In one embodiment, a method includes detecting a change in network topology and broadcasting a transient unconditional unpruning message to all nodes in the network. The message is configured to instruct each network element receiving the message to start a phase timer in response to the broadcast message; unprune its operational ports; and, upon expiration of the phase timer, prune its ports in accordance with the results of a pruning protocol. | 01-24-2013 |
20130242757 | INTERCONNECTING SEGMENTED LAYER TWO NETWORK FOR CLOUD SWITCHING - In one embodiment, a layer-2 network that includes a cloud switch is partitioned into a plurality of segments, each segment including one or more cloud switch domains that are coupled via a logical port to a corresponding one of a plurality of internal logical shared media links. One of the internal logical shared media links is provisioned as a hub. One or more remaining internal logical shared media links are defaulted to be spokes. A spanning tree protocol (STP) is executed within each segment. The logical port of each cloud switch domain advertises a pseudo root bridge identifier (ID) to cause the internal logical shared media link to appear attached to a Root. The advertised pseudo root bridge ID of the hub is chosen to have a higher priority than the pseudo root bridge ID of the spokes to establish a hub and spoke relationship among the segments. | 09-19-2013 |
20130287038 | SYNCHRONIZATION OF TRAFFIC MULTIPLEXING IN LINK AGGREGATION - Synchronization of traffic multiplexing in link aggregation is described. In an embodiment, a first link aggregator and a second link aggregator are associated with a plurality of links. The first link aggregator maintains an identifier for each link indicating at least a state of enabled or disabled. A synchronized clock is established between the first link aggregator and the second link aggregator. A particular link of the plurality of links is transitioned. Wherein, the transitioning is performed by the first link aggregator sending, to the second link aggregator, a first message identifying a particular time to transition the particular link. The first link aggregator receives, from the second link aggregator, a second message indicating that the particular time is acceptable. In response to a determination that the second message indicates that the particular time is acceptable and that the synchronized clock has reached the particular time, transitioning the link. | 10-31-2013 |
20130301407 | METHOD AND APPARATUS FOR ADAPTIVE FAST START IN LINK AGGREGATION - In one embodiment, a period between periodic transmissions of protocol data units (PDUs) used to form or maintain a link aggregation group is initially set to a fixed value. When a stress condition is detected, the period between periodic transmissions of PDUs is increased from the initial value. When the stress condition is determined to have eased, the period between periodic transmissions of PDUs is reduced back toward the fixed value. | 11-14-2013 |
20130301427 | GRACE STATE AND PACING IN LINK AGGREGATION - In one embodiment, one or more indicia of stress are monitored. Based on the one or more indicia of stress, it is determined a stress condition exists. In response to the stress condition, one or more link aggregation actors and partners are caused to enter a grace state for a grace period. While the one or more link aggregation actors and partners are in the grace state, link aggregation formation is paced on a plurality of links by delaying formation of one or more new link aggregation groups on the plurality of links until a hold is released. Upon expiration of the grace period, the grace state is exited. | 11-14-2013 |
20130336164 | SYSTEM AND METHOD FOR VIRTUAL PORTCHANNEL LOAD BALANCING IN A TRILL NETWORK - An example method includes storing a portion of virtual PortChannel (vPC) information in a TRansparent Interconnect of Lots of Links network environment, deriving, from the portion of vPC information, a physical nickname of an edge switch to which a frame can be forwarded, and rewriting an egress nickname in a TRILL header of the frame with the physical nickname. In example embodiments, the vPC information can include respective vPC virtual nicknames, EtherChannel hash algorithms, hash values, and physical nicknames of edge switches associated with vPCs in the network environment. In some embodiments, the portion of vPC information can be derived from an Interested vPC Type Length Value (TLV) information of an Intermediate System to Intermediate System (IS-IS) routing protocol data unit (PDU). | 12-19-2013 |
20140050077 | HITLESS PRUNING PROTOCOL UPGRADE ON SINGLE SUPERVISOR NETWORK DEVICES - In Service Software Upgrade (ISSU) permits administrators to upgrade the control plane software of a network device without any disruption to the traffic passing through the data plane of the network device. However, because the control plane is unavailable, the network device is unable to transmit periodic messages to re-subscribe to specific VLANs. This may result in a service outage in end devices that rely on the network device to receive data assigned to those VLANs. To prevent the network device from being unsubscribed from the VLANs while the control plane is unavailable, the network device may transmit a control plane message before starting ISSU. Once a neighboring network device receives the message, the neighboring device delays unsubscribing the network device until the control plane is again available. Thus, the network device may perform ISSU without the possibility of data traffic not reaching end devices. | 02-20-2014 |
20140050116 | Techniques for Generic Pruning in a Trill Network - Techniques are provided for managing and distributing communications in a network. At a first switch device arranged in a first configuration in a network, a set of one or more network attributes are determined, which are associated with network communications that the first switch device is interested in receiving from other network devices. The first switch device sends to a controller device an attribute interest message that informs the controller device of the set of network attributes. The first switch device receives a mapping of the network attributes in to one or more identifiers. The identifiers are included in a header of subsequent frames sent in the network. An identifier interest message is then sent to a second switch device arranged in a second network configuration in the network to inform the second switch device of identifiers of the network attributes of which the first device has an interest. | 02-20-2014 |
20140056178 | TRILL OPTIMAL FORWARDING AND TRAFFIC ENGINEERED MULTIPATHING IN CLOUD SWITCHING - In one embodiment, a plurality of leaf switches that include host facing ports are configured as a cloud switch. An indication of connectivity between the leaf switches of the cloud switch and routing bridges (RBridges) external to the cloud switch may be added to link state packets (LSPs) sent over the at least one logical shared media link. A lookup table may be generated that specifies next hop leaf switches. The generated lookup table may be used to forward frames to one or more particular nexthop leaf switches. Further, traffic engineering parameters may be collected. Equal cost multipath (ECMP) nexthop leaf switches and distribution trees to reach one or more destinations may be examined. Traffic may be distributed across ones of them based on the traffic engineering parameters. | 02-27-2014 |
20140064150 | MST EXTENSIONS FOR FLEXIBLE AND SCALABLE VN-SEGMENT LOOP PREVENTION - In one embodiment, a first number of multiple spanning tree instances (MSTIs) are defined within a network. A second number of network segments associated with segmentation identifier (IDs) are also configured, where the first number of MSTIs is less than the second number of segmentation IDs. Segmentation ID to MSTI mappings are maintained that map each defined segmentation ID of the second number of network segments to one of the first number of MSTIs. A segmentation mapping digest is computed of the segmentation ID to MSTI mappings. Multiple spanning tree (MST) bridge protocol data units (BPDUs) are broadcast that include the digest of the segmentation ID to MSTI mappings. | 03-06-2014 |
20140092780 | METHODS AND APPARATUSES FOR RAPID TRILL CONVERGENCE THROUGH INTEGRATION WITH LAYER TWO GATEWAY PORT - Methods and apparatuses for rapid TRILL convergence are disclosed herein. The methods can be implemented in a network including a plurality of RBridges or in a cloud network environment including a plurality of cloud switch domains. An example method for rapid TRILL convergence can include: Executing a spanning tree protocol (STP) for network topology in a network; and executing a Hello protocol for control and forwarding at the RBridge. The Hello protocol can be configured to elect a designated RBridge and assign an appointed forwarder. The method can also include assigning a transient appointed forwarder during a period of time between convergence of the STP and convergence of the Hello protocol. The transient appointed forwarder can be configured to forward frames in the network during the period of time between convergence of the STP and convergence of the Hello protocol. | 04-03-2014 |
20140101302 | Techniques for Scalable and Foolproof Virtual Machine Move Handling with Virtual Port Channels - Techniques are provided for managing movements of virtual machines in a network. At a first switch, a virtual machine (VM) is detected. The VM is hosted by a physical server coupled to the first switch. A message is sent to other switches and it indicates that the VM is hosted by the physical server. When the first switch is paired with a second switch as a virtual port channel (vPC) pair, the message includes a switch identifier that identifies the second switch. A receiving switch receives the message from a source switch in the network comprising a route update associated with the VM. A routing table of the receiving switch is evaluated to determine whether the host route is associated with a server facing the physical port. The message is examined to determine it contains the switch identifier. | 04-10-2014 |
20140101336 | SYSTEM AND METHOD FOR IMPLEMENTING A MULTILEVEL DATA CENTER FABRIC IN A NETWORK ENVIRONMENT - A method is provided in one example embodiment and includes determining whether a first network element with which a second network element is attempting to establish an adjacency is a client type element. If the first network element is determined to be a client type element, the method further includes determining whether the first and second network elements are in the same network area. If the first network element is a client type element and the first and second network elements are determined to be in the same network area, the adjacency is established. Subsequent to the establishing, a determination is made whether the first network element includes an inter-area forwarder (IAF). | 04-10-2014 |
20140161131 | Flexible and Scalable Virtual Network Segment Pruning - A segment within a virtual network is identified as being supported by a segment bundling device. The segment within the virtual network supports a first host connected to a first bridging device and a second host connected to a second bridging device. The segment bundling device is used to receive virtual network address information describing the virtual network segmentation identifier (ID) for the segment used for receiving virtual network traffic for the first and second host. A segment bundling table associating a bundle ID with the virtual network segmentation identifier based on the upper ID and the lower ID of the virtual network ID is generated by the segment bundling device. The segment bundling device is used to distribute the segment bundling table to traffic forwarding devices in the virtual network that interface with the first bridging device and the second bridging device. | 06-12-2014 |
20140177640 | Intelligent Host Route Distribution for Low Latency Forwarding and Ubiquitous Virtual Machine Mobility in Interconnected Data Centers - Techniques are presented for distributing host route information of virtual machines to routing bridges (RBridges). A first RBridge receives a routing message that is associated with a virtual machine and is sent by a second RBridge. The routing message comprises of mobility attribute information associated with a mobility characteristic of the virtual machine obtained from an egress RBridge that distributes the routing message. The first RBridge adds a forwarding table attribute to the routing message that indicates whether or not the first RBridge has host route information associated with the virtual machine in a forwarding table of the first RBridge. The first RBridge also distributes the routing message including the mobility attribute information and the forwarding table attribute, to one or more RBridges in the network. | 06-26-2014 |
20140254590 | SCALABLE MULTICAST ROUTE DISTRIBUTION IN A MULTITENANT DATA CENTER FABRIC IN A NETWORK ENVIRONMENT - A method is provided in one example embodiment and includes determining a route target (“RT”) membership for a network element; determining at least one attribute for the RT membership; and advertising the RT membership with the at least one attribute to other network elements. The at least one attribute may include an RT membership type attribute for indicating whether the RT membership is due to a local virtual network connection, transit support, or both. Additionally or alternatively, the at least one attribute may include a distribution tree binding attribute for indicating a distribution tree for the RT membership. | 09-11-2014 |
20140258485 | EFFICIENT HANDLING OF MULTI-DESTINATION TRAFFIC IN AN INTERNET PROTOCOL FABRIC DATA CENTER - A method is provided in one example embodiment and includes establishing at least one fixed topology distribution tree in a network, where the fixed topology distribution tree comprises one root node and a plurality of leaf nodes connected to the root node; maintaining at the root node an indication of multicast group interests advertised by the leaf nodes; and pruning traffic at the root node based on the advertised multicast group interests of the leaf nodes. In one embodiment, the root node is a spine switch and each of the leaf nodes is a leaf switch and each of the leaf nodes is connected to the root node by a single hop. | 09-11-2014 |
20140269695 | System for Conversational Link Aggregation Resolution in a Network Switch - Some implementations provide a method that includes: (i) receiving a list of logic link aggregations (LAGs) within a computer network, the list identifying a single physical egress port associated with each LAG; (ii) receiving a data unit; (iii) identifying that the data unit is addressed to a remote LAG included in the list of logic link aggregations; (iv) establishing a connection with the remote LAG; (v) downloading a detailed data describing the remote LAG from a control plane, the detailed data including a list of multiple available physical egress ports associated with the remote LAG, and; (vi) upon downloading the detailed data, incorporating the detailed data into the list of LAGs in association with an entry identifying the remote LAG. | 09-18-2014 |
20140344426 | Transient Unpruning for Faster Layer-Two Convergence - In one embodiment, a method includes detecting a change in network topology and broadcasting a transient unconditional unpruning message to multiple nodes in the network. The message is configured to instruct each of the nodes receiving the message to start a phase timer in response to the broadcast message; unprune its operational ports; and, upon expiration of the phase timer, prune its ports in accordance with the results of a pruning protocol. | 11-20-2014 |
20140348166 | OPTIMAL FORWARDING FOR TRILL FINE-GRAINED LABELING AND VXLAN INTERWORKING - An example method for determining an optimal forwarding path across a network having VxLAN gateways configured to implement both FGL networking and VxLAN capabilities can include learning RBridge nicknames associated with the VxLAN gateways in the network. Additionally, the method can include determining a path cost over the FGL network between each of the VxLAN gateways and a source node and a path cost over the VxLAN between each of the VxLAN gateways and a destination node. Further, the method can include determining an encapsulation overhead metric associated with the VxLAN and selecting one of the VxLAN gateways as an optimal VxLAN gateway. The selection can be based on the computed path costs over the FGL network and the VxLAN and the encapsulation overhead metric. | 11-27-2014 |
20140355475 | SYSTEM, DEVICES AND METHODS FOR FACILITATING COEXISTENCE OF VLAN LABELING AND FINE-GRAINED LABELING RBRIDGES - An example method for calculating a constrained distribution tree in a TRILL network including a plurality of VL and FGL RBridges can include learning an FGL multi-destination frame filtering capability of at least one of the FGL RBridges in the TRILL network, constructing a sub-graph including the FGL RBridges and associated links and calculating at least one sub-tree based on the sub-graph. The method can also include constructing a graph including VL RBridges, the FGL RBridges and associated links by adding links between the VL RBridges and the FGL RBridges. The FGL RBridge to which the VL RBridge is linked can have sufficient FGL multi-destination frame filtering capability. Further, the method can include calculating a constrained distribution tree based on the graph by treating the sub-tree as a logical node. | 12-04-2014 |
20140369345 | METHOD AND APPARATUS FOR SCALING INTERCONNECTED IP FABRIC DATA CENTERS - Techniques which provide scalable techniques for managing multicast traffic in interconnected IP fabric data centers. More specifically, embodiments presented herein disclose an aggregated source technique used to address scalability issues for interconnected IP fabric data centers as well as disclose a secondary rendezvous point technique used to address backbone network (S, G) multicast state scalability. Additionally, embodiments disclosed herein include an approach for border leaf load balancing based on group destination addresses used by VTEPs. | 12-18-2014 |
20150016300 | SUPPORT FOR VIRTUAL EXTENSIBLE LOCAL AREA NETWORK SEGMENTS ACROSS MULTIPLE DATA CENTER SITES - A method is provided in one example embodiment and includes establishing a virtual trunk link between a first network element and a second network element. The first and second network elements are located at a first site and the first site and a second site comprise at least a portion of an overlay network. The method further includes receiving data traffic at the first network element, which data traffic is associated with a segment of the overlay network, and mapping a first network identifier allocated to the overlay network segment at the first network element to a virtual trunk link and a VLAN ID. The method additionally includes forwarding the data traffic from the first network element to the second network element via the virtual trunk link with the VLAN ID. | 01-15-2015 |
20150016301 | Flexible and Scalable Monitoring in a TRILL Network - A monitoring session associated with a virtual nickname may be established in a TRILL network. A monitoring station may be connected to an edge switch of the TRILL network specifying the virtual nickname for the monitoring session. The monitoring station is set as a destination for the monitoring session and the virtual nickname is flooded throughout the TRILL network. A source may then be configured to the monitoring session by specifying the virtual nickname of the monitoring session without knowing the destination tied to the monitoring session. Network traffic through the source may then be forwarded to the destination tied to the monitoring session. | 01-15-2015 |
20150063353 | IMPLEMENTATION OF VIRTUAL EXTENSIBLE LOCAL AREA NETWORK (VXLAN) IN TOP-OF-RACK SWITCHES IN A NETWORK ENVIRONMENT - An example method for implementation of virtual extensible local area network (VXLAN) in top-of-rack (ToR) switches in a network environment is provided and includes receiving a packet encapsulated with a VXLAN header having an unknown virtual tunnel endpoint (VTEP) Internet Protocol (IP) address in a network environment, and installing an entry at an index location of a forwarding table. The index location includes an encoding of the VTEP-IP address as a VTEP index (VTEP-IDX), and the entry maps a VXLAN interface to an IP address associated with a VXLAN network interface (VNI). In specific embodiments, the VTEP-IDX is logN bits, where N is a size of the forwarding table. The forwarding table indicates a destination VTEP IP address when encapsulating the packet, and the source VTEP IP address when decapsulating the packet. | 03-05-2015 |
20150071286 | SYSTEM AND METHOD FOR UTILIZATION OF A SEGMENTATION IDENTIFICATION TO SUPPORT TRANSMISSION OF DATA TO A DESTINATION NODE - A method is provided in one example and includes receiving, at a receiving node, a packet that comprises information indicative of an internet protocol address and a segmentation identification, selecting a virtual routing and forwarding table corresponding with the segmentation identification, identifying a destination node based, at least in part, on the internet protocol address and the virtual routing and forwarding table, and transmitting the packet to the destination node. | 03-12-2015 |