Patent application number | Description | Published |
20080238486 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS - A semiconductor integrated circuit design method includes a step (L) of providing layout information for laying out elements making up a logical circuit on a semiconductor substrate; a step (P) of providing logical circuit information; a step (a) of classifying logical circuits in response to the logical circuit propagation route of a signal based on the logical circuit information and a step (b) of isolating the logical circuits forming the route obtained in the classifying step (a) for each number of stages; a step (c) of classifying the elements making up the logical circuit according to substrate voltage for each number of stages of the logical circuit; and a layout correction step (d) of correcting the layout information so that each element with the larger stage number of the logical circuit is placed at a point closer to a substrate contact. | 10-02-2008 |
20080290946 | Semiconductor integrated circuit device - To save power consumption in a semiconductor integrated circuit | 11-27-2008 |
20080297204 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N | 12-04-2008 |
20080315933 | PULSE SYNTHESIS CIRCUIT - A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node. | 12-25-2008 |
20090039985 | ELECTRONIC DEVICE, AND INFORMATION APPARATUS, COMMUNICATIONS APPARATUS, AV APPARATUS, AND MOBILE APPARATUS USING THE SAME - An electronic device includes a transmitter circuit, a receiver circuit, a first conductor, and a second conductor of a return path being a grounded line. The first conductor is surrounded by a dielectric. A plurality of resistive elements are connected in parallel between the first conductor and the second conductor. The first conductor transfers therethrough a transmission signal from the transmitter circuit. The length of the line of the first conductor is set to be greater than or equal to one half of the product between the inverse of the signal transfer rate of the first conductor and the velocity of light traveling through the dielectric. The resistive elements are provided along the line of the first conductor for every unit distance being equal to one half of the product between the signal transfer rate of the first conductor and the velocity of light traveling through the dielectric. Thus, it is possible to reduce the signal waveform distortion along the transmission line. | 02-12-2009 |
20090085616 | SEMICONDUCTOR INTEGRATED CIRCUIT, COMMUNICATION APPARATUS, INFORMATION PLAYBACK APPARATUS, IMAGE DISPLAY APPARATUS, ELECTRONIC APPARATUS, ELECTRONIC CONTROL APPARATUS AND MOBILE APPARATUS - The semiconductor integrated circuit having a transmitter circuit for transmitting a supplied external data signal DIN. The transmitter circuit includes: a transmitter flip-flop circuit having a reference clock CK as an input for holding the external data signal DIN in synchronization with the reference clock CK; a frequency divider circuit for multiplying the frequency of the reference clock CK by n/m (m and n are integers equal to or more than 2 and m>n); a data signal buffer circuit for transmitting a data signal held by the transmitter flipflop circuit; and a clock buffer circuit for transmitting the output of the frequency divider circuit. | 04-02-2009 |
20090102528 | SEMICONDUCTOR INTEGRATED CIRCUIT - During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator. | 04-23-2009 |
20090129138 | Semiconductor Integrated Circuit - It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing. | 05-21-2009 |
20090206880 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S | 08-20-2009 |
20090206881 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different from the first polarity. The first substrate is insulated from a power source or ground to which a source of a MOSFET formed on the substrate is connected. The third substrate is disposed between the first and second substrates in adjacent relation to the first and second substrates. A circuit element is formed on the third substrate. | 08-20-2009 |
20100097128 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit ( | 04-22-2010 |
20100165705 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor integrated circuit having a register file of a multiport configuration, a first holding circuit | 07-01-2010 |
20110010682 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS - A semiconductor integrated circuit design method includes a step (L) of providing layout information for laying out elements making up a logical circuit on a semiconductor substrate; a step (P) of providing logical circuit information; a step (a) of classifying logical circuits in response to the logical circuit propagation route of a signal based on the logical circuit information and a step (b) of isolating the logical circuits forming the route obtained in the classifying step (a) for each number of stages; a step (c) of classifying the elements making up the logical circuit according to substrate voltage for each number of stages of the logical circuit; and a layout correction step (d) of correcting the layout information so that each element with the larger stage number of the logical circuit is placed at a point closer to a substrate contact. | 01-13-2011 |
20110012641 | CELL ARRANGEMENT METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - Logic circuit information in which flip-flops of a semiconductor integrated circuit subjected to designing and a logic circuit between flip-flops are defined is input. The logic circuit information is analyzed to detect a logic circuit sandwiched by two flip-flops. The number of logic stages of the detected logic circuit is counted. It is determined, according to the counted number of logic stages, to which substrate potential a cell used for the logic circuit is to be connected. | 01-20-2011 |
20110012656 | SEMICONDUCTOR INTEGRATED CIRCUIT - During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator. | 01-20-2011 |
20110063008 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S | 03-17-2011 |
20110090015 | SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC DEVICE - A semiconductor integrated circuit includes a first ring oscillator to which a stress voltage is applied; a second ring oscillator to which the stress voltage is not applied; and a phase comparator configured to receive an output of the first ring oscillator and an output of the second ring oscillator, and to compare phases of the outputs. The first ring oscillator includes a switch circuit configured to switch between a first connection state in which ring connection of the first ring oscillator is disconnected to connect a predetermined node of the second ring oscillator to a predetermined node of the first ring oscillator, and a second connection state in which connection between the first ring oscillator and the second ring oscillator is disconnected to connect the first ring oscillator in a ring. | 04-21-2011 |