Patent application number | Description | Published |
20090167792 | ASSEMBLY AND IMAGE RECORDING APPARATUS - An assembly includes a frame having a first wall and a second wall, a support shaft, an elastic member, and an engaging member. The engaging member has a first engaging portion, the first wall has a recessed portion, the second wall has a second engaging portion, and the support shaft has an insertion portion. The first engaging portion and the second engaging portion are engaged with each other in a state in which the insertion portion is fitted into the recessed portion and the elastic member is compressed by the engaging member. | 07-02-2009 |
20110074874 | IMAGE RECORDING APPARATUS - An image recording apparatus wherein a first rack gear is not meshed with a second pinion gear when the second pinion gear faces a first moving end of a slide cam or when the second pinion gear faces a second moving end of the cam, and is meshed with the second pinion gear when a portion of the cam which faces the second pinion gear is displaced between the first and second moving ends, wherein a second rack gear is meshed with a third pinion gear over an area of the cam between the first and second moving ends, wherein teeth of a tooth chipped gear are partly chipped such that the second pinion gear faces the area of the cam, and wherein the second pinion gear is rotated relative to the third pinion gear due to play at least until the tooth chipped gear is meshed with a drive gear. | 03-31-2011 |
20110242205 | LIQUID-JETTING APPARATUS - A liquid-jetting apparatus includes: a liquid-jetting head which has a liquid-jetting surface provided with first and second nozzles and which jets liquids of different types from the first and second nozzles respectively; a cap which is driven between a capping position and a retracted position; a cap driving member which moves in a first direction to drive the cap; first and second gas discharge valves via which bubble is discharged from first and second liquid supply members connected to the liquid-jetting head respectively; first and second valve opening/closing members which open/close the first and second gas discharge valves respectively; first and second gas discharge driving members arranged in the first direction, which move in a second direction intersecting the first direction to drive the first and second valve opening/closing members respectively; and a driving source which moves the first and second gas discharge driving members in the second direction. | 10-06-2011 |
20120327159 | LIQUID JETTING APPARATUS - There is provided a liquid jetting apparatus including: a liquid jetting head which has a liquid jetting surface on which a plurality of nozzles are open to jet the liquid; a wiper which moves, relative to the liquid jetting surface, in a wiping direction along the liquid jetting surface, while being brought in contact with the liquid jetting surface, to wipe the liquid adhered on the liquid jetting surface; a wiper moving mechanism which moves the wiper in a direction orthogonal to the liquid jetting surface to approach to or separate from the ink jetting surface; a stopper which makes contact with the wiper which is separated from the ink jetting surface; and an impact-absorbing member which is formed in the wiper or the stopper and absorbs impact generated in a case that the wiper collides with the stopper. | 12-27-2012 |
20140184689 | LIQUID EJECTION APPARATUS - A liquid ejection apparatus of the invention comprises a switcher configured to connect or disconnect a sucker with suction tubes individually. The switcher comprises a case and a rotator. The case comprises an internal space and holes each causing the internal space to communicate with an outside of the case. The rotator is accommodated in the internal space and is rotatable along an inner surface defining the internal space in the case. The suction tubes are respectively connected to the holes. The rotator comprises a passage formed therein. The passage is configured to cause the sucker to communicate with two or more holes without causing the sucker to communicate with the holes other than the two or more holes, depending on a rotational position of the rotator in the internal space. | 07-03-2014 |
20140247303 | LIQUID EJECTION APPARATUS, METHOD, AND NON-TRANSITORY, COMPUTER-READABLE MEDIUM FOR CONTROLLING LIQUID EJECTION APPARATUS - A liquid ejection apparatus includes a liquid ejection head having a plurality of nozzle units, a plurality of capping devices, a movement mechanism, a plurality of suctioning tubes, a suctioning mechanism, a connection device, and a control device. The control device controls the suctioning mechanism to suction fluid in the capping device corresponding to one of the nozzle units and the capping device corresponding to a different one of the nozzle units. In response to expiration of a predetermined time period, which is a predetermined amount of time that the suctioning mechanism generates a suctioning force, the control device controls to disconnect the capping device corresponding to the one of the nozzle units from the suctioning mechanism. | 09-04-2014 |
Patent application number | Description | Published |
20080290852 | POWER SUPPLY CIRCUIT AND SEMICONDUCTOR MEMORY - A power supply circuit that outputs a set voltage from an output terminal, has a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first detecting signal when the voltage outputted from the boosting circuit is not lower than a first detection voltage set lower than the set voltage, and outputs a second detecting signal when the voltage outputted from the boosting circuit is not lower than the set voltage; and a clock signal generating circuit that outputs, based on a reference clock signal, a clock signal and an inverted clock signal obtained by inverting the clock signal, and stops outputs of the clock signal and the inverted clock signal in response to the second detecting signal. | 11-27-2008 |
20090040834 | SEMICONDUCTOR MEMORY DEVICE - A memory cell array forms a plurality of control areas in a direction orthogonal to the direction of extension of a bit line. A sense amplifier initially charges a bit line in each control area in the memory cell array with a charging voltage controlled by a respective individual bit-line control signal. Bit-line control signal generator circuits are provided plural in accordance with the control areas in the memory cell array. Each bit-line control signal generator circuit receives the potential on a cell source line in a corresponding control area, individually generates and provides the bit-line control signal in the each control area in accordance with the received voltage on the cell source line in each control area. | 02-12-2009 |
20090040835 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells connected to a bit line, and a sense amplifier of the current sense type. The sense amplifier includes an initial charging circuit capable of initially charging the bit line with a suppressed value of current only for a certain starting period during an initial charging period. The sense amplifier detects a value of current flowing in the bit line to decide data read out of each of the memory cells. | 02-12-2009 |
20090067255 | NONVOLATILE SEMICONDUCTOR MEMORY INCLUDING MEMORY CELL FOR STORING MULTILEVEL DATA HAVING TWO OR MORE VALUES - A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage. | 03-12-2009 |
20090103368 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles. | 04-23-2009 |
20100165744 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles. | 07-01-2010 |
20100329017 | SEMICONDUCTOR DEVICE FOR SHORT-CIRCUITING OUTPUT TERMINALS OF TWO OR MORE VOLTAGE GENERATOR CIRCUITS AT READ TIME AND CONTROL METHOD FOR THE SAME - According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first MOS transistor is capable of short-circuiting the first node and second node. The controller performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor. The controller controls a period in which the first MOS transistor is kept in an on state based on time. | 12-30-2010 |
20110176364 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a semiconductor substrate which includes a well. A memory cell array includes memory cells each including a floating gate electrode above the well and a control gate electrode above the floating gate electrode, and is configured to write data in units of pages each including memory cells connected in series and to erase data in units of blocks each includes a plurality of the pages. A control gate line is selectively electrically connected to the control gate electrodes of at least one of the blocks. A first switching element includes a current path having ends connected to the control gate line and a ground end. The well is charged, and the first switching element is turned off before the end of the discharge of the well. | 07-21-2011 |