Patent application number | Description | Published |
20080290514 | Semiconductor device package and method of fabricating the same - In a semiconductor device, a package including the semiconductor device and a method of forming the same, the semiconductor device package includes a semiconductor device, a wiring board, and an underfill material layer. The semiconductor device includes a semiconductor chip, a metal layer, and solder balls for bump contacts. The semiconductor chip includes an active surface having bonding pads and a rear surface opposite the active surface and having concave portions corresponding to the bonding pads. The metal layer fills the concave portions and covers the rear surface. The solder balls for bump contacts are provided on the bonding pads. The wiring board includes an upper surface to which the semiconductor device is mounted and a lower surface opposite the upper surface. The underfill material layer fills a space between the active surface of the semiconductor device and the upper surface of the wiring board. The semiconductor device and the wiring board are electrically connected to each other by the solder balls for bump contacts of the semiconductor device and bonding electrodes included in the upper surface of the wiring board. | 11-27-2008 |
20090096071 | SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE HAVING THE SAME - A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved. | 04-16-2009 |
20090239336 | Semiconductor packages and methods of fabricating the same - A semiconductor package and module, and methods of fabricating the same are provided. A method of fabricating a semiconductor package may include bonding rear surfaces of first and second semiconductor chips to each other, each of the semiconductor chips having chip pads exposed on front surfaces. The method may also include forming an encapsulation portion configured to encapsulate side surfaces of the bonded semiconductor chips, forming via plugs configured to pass through the encapsulation portion, forming an insulating layer configured to expose surfaces of the chip pads and the via plugs on the exposed surfaces of the two semiconductor chips and surfaces of the encapsulation portion, and forming package pads on the exposed surfaces of the chip pads and the surfaces of the via plugs. | 09-24-2009 |
20090289359 | SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package and a method of manufacturing the semiconductor package are provided. A semiconductor package according to the present general inventive concept may include a base substrate having one surface on which a connection terminal is formed and a first package substrate having a molding layer covering the base substrate. The molding layer faces a circumference of the connection terminal and includes a side surface having first and second surfaces having a circumference of a different size, respectively. | 11-26-2009 |
20100013076 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device package includes a semiconductor chip having a top surface on which a conductive pad is disposed, a bottom surface opposite to the top surface, and a side surface connecting the top and bottom surfaces to each other; a first insulating layer covering the top surface of the semiconductor chip and laterally extending to the outside of the semiconductor chip; a fillet member covering a boundary where the side surface of the semiconductor chip and the first insulating layer meet each other; and a molding layer covering the bottom surface of the semiconductor chip, the fillet member, and the first insulating layer. | 01-21-2010 |
20100081236 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH EMBEDDED INTERPOSER - A method of manufacturing a semiconductor device includes forming printed circuit board (PCB) having an embedded interposer. A semiconductor chip or a semiconductor package is mounted onto the embedded interposer using a conductive adhesive agent. The embedded interposer has substantially the same coefficient of thermal expansion (CTE) as the semiconductor chip. The embedded interposer is formed using a semiconductor wafer. | 04-01-2010 |
20100096754 | Semiconductor package, semiconductor module, and method for fabricating the semiconductor package - Provided is a semiconductor package, a semiconductor module and a method for fabricating the semiconductor package. The method provides a substrate including a bonding pad. The method forms a dielectric layer for exposing the bonding pad on the substrate. The method forms a redistribution line which is electrically connected to the bonding pad, on the dielectric layer. The method forms an external terminal which is electrically connected to the bonding pad without using a solder mask which limits a position of the external terminal, on the redistribution line. | 04-22-2010 |
Patent application number | Description | Published |
20090045513 | SEMICONDUCTOR CHIP PACKAGE, ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR CHIP PACKAGE AND METHODS OF FABRICATING THE ELECTRONIC DEVICE - A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other. | 02-19-2009 |
20090065919 | SEMICONDUCTOR PACKAGE HAVING RESIN SUBSTRATE WITH RECESS AND METHOD OF FABRICATING THE SAME - In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first recess and covering a side surface of the first semiconductor chip. The first semiconductor chip is electrically connected to the first interconnection. | 03-12-2009 |
20090134528 | SEMICONDUCTOR PACKAGE, ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - Provided are a semiconductor package, an electronic device including the semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes semiconductor chips mounted on a carrier, a first insulating layer sealing the semiconductor chips, first via-holes which are formed in the first insulating layer and expose a portion of each of the semiconductor chips, a first conductive pattern which is filled in the first via-holes and electrically connected to each of the semiconductor chips, and an external terminal which is electrically connected to the first conductive pattern. The semiconductor package is manufactured by performing an encapsulating process and a via-hole process. | 05-28-2009 |
20150014860 | SEMICONDUCTOR CHIP CONNECTING SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate including a substrate connection pad. At least one semiconductor chip includes at least one redistribution layer. The at least one redistribution layer covers at least a portion of a chip connection pad and extends along an upper surface of the at least one semiconductor chip in a first direction in which the chip connection pad faces toward an edge of the at least one semiconductor chip. At least one interconnection line disposed on a side of the at least one semiconductor chip electrically connects the substrate connection pad to the at least one redistribution layer. The at least one redistribution layer includes a protruding portion protruding from the edge of the at least one semiconductor chip to contact the at least one interconnection line. | 01-15-2015 |
Patent application number | Description | Published |
20130020720 | SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME - A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips. | 01-24-2013 |
20130161784 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate; first and second pads that are disposed separate from each other on the substrate; and a solder resist that allows a portion of the substrate in a region between the first and second pads and to be exposed while covering a portion of the first and second pads in a region other than the region between the first and second pads. | 06-27-2013 |
20150028474 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package. | 01-29-2015 |