Patent application number | Description | Published |
20110032677 | DISTRIBUTED COMPUTING - On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems. | 02-10-2011 |
20110032688 | DISTRIBUTED COMPUTING - On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems. | 02-10-2011 |
20110035177 | DISTRIBUTED COMPUTING - On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems. | 02-10-2011 |
20110035612 | DISTRIBUTED COMPUTING - On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems. | 02-10-2011 |
20110035626 | DISTRIBUTED COMPUTING - On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems. | 02-10-2011 |
20130314888 | DISTRIBUTED COMPUTING - On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems. | 11-28-2013 |
Patent application number | Description | Published |
20090209179 | PNEUMATIC TOOL HAVING A ROTOR WITH A WEAR-RESISTANT VANE SLOT - This invention relates generally to an improved rotor for a pneumatic abrading or polishing tool, such as an orbital abrading or polishing tool, and more particularly to such a rotor having a wear-resistant vane slot. A power abrading or polishing tool, such as a pneumatic orbital abrading or polishing tool, includes a motor having a rotor that transmits a rotational force to a carrier part having an abrading or polishing head attached thereto. The rotor is contained in a motor housing which includes an inlet passage and one or more exhaust passages. Compressed air or other suitable gas enters the motor housing through the inlet passage and causes the rotor to rotate within the motor housing. As the rotor rotates, vanes slide in and out of slots in the rotor, creating sealed chambers or compartments between adjacent vanes. As the compressed gas expands within these compartments, it pushes on the vanes, causing the rotor to rotate and the vanes to slide in and out of their vane slots. The rotor includes a metal clip lining the inside surface of the vane slots to prevent wear on the slots due to the repeated movement of the vanes in and out of the slots. | 08-20-2009 |
20120289136 | ABRADING OR POLISHING TOOL WITH IMPROVED MOTOR CHAMBER - The present invention relates to an abrading or polishing tool with an improved motor chamber, and more particularly to a tool with a motor chamber having a sleeve or liner lining the inside surface of the motor chamber. In one embodiment, an abrading or polishing tool includes a body defining an internal motor chamber with an inner surface, a liner lining the inner surface of the motor chamber, a rotor contained within the motor chamber for rotation against the liner, and an abrading or polishing head coupled to the rotor for rotation. | 11-15-2012 |
Patent application number | Description | Published |
20080204461 | Auto Software Configurable Register Address Space For Low Power Programmable Processor - A configurable graphics pipeline has more than one possible process flow of pixel packets through elements of the graphics pipeline. In one embodiment, a data packet triggers an element of the graphics pipeline to discover an identifier. | 08-28-2008 |
20080246764 | Early Z scoreboard tracking system and method - Early Z scoreboard tracking systems and methods in accordance with the present invention are described. Multiple pixels are received and a pixel depth raster operation is performed on the pixels. The pixel depth raster operation comprises discarding a pixel that is occluded. In one exemplary implementation, the depth raster operation is done at a faster rate than a color raster operation. Pixels that pass the depth raster operation are checked for screen coincidence. Pixels with screen coincidence are stalled and pixels without screen coincidence are forwarded to lower stages of the pipeline. The lower stages of the pipeline are programmable and pixel flight time can vary (e.g., can include multiple passes through the lower stages). Execution through the lower stages is directed by a program sequencer which also directs notification to the pixel flight tracking when a pixel is done processing. | 10-09-2008 |
20090046103 | Shared readable and writeable global values in a graphics processor unit pipeline - An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented. | 02-19-2009 |
20090049276 | Techniques for sourcing immediate values from a VLIW - Sourcing immediate values from a very long instruction word includes determining if a VLIW sub-instruction expansion condition exists. If the sub-instruction expansion condition exists, operation of a portion of a first arithmetic logic unit component is minimized. In addition, a part of a second arithmetic logic unit component is expanded by utilizing a block of a very long instruction word, which is normally utilized by the first arithmetic logic unit component, for the second arithmetic logic unit component if the sub-instruction expansion condition exists. | 02-19-2009 |
20090147012 | Parallelogram unified primitive description for rasterization - In a graphics pipeline of a graphics processor, a method for a unified primitive description for rasterization. The method includes receiving a group of primitives from a graphics application, wherein the group includes different types of primitives and the types of primitives include line primitives, point primitives and triangle primitives. For each of the types of primitives, the method includes generating a corresponding parallelogram, wherein the parallelogram has four sides disposed along an x-axis and a y-axis, and computing an inside y-axis mid point and an outside y-axis mid point based on the four sides. The parallelogram is controlled to represent to each of the primitive types respectively by adjusting a location of the inside y-axis mid point or the outside y-axis mid point. | 06-11-2009 |
20110254848 | Buffering deserialized pixel data in a graphics processor unit pipeline - An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs. | 10-20-2011 |
20120176386 | REDUCING RECURRENT COMPUTATION COST IN A DATA PROCESSING PIPELINE - Briefly, in accordance with one or more embodiments of graphics processing, a current data signature is generated based at least in part on current input data, and the current data signature is compared with a prior cycle data signature. If the current data signature at least partially matches the prior cycle data signature, a prior cycle result may be fetched and processing of at least part of the current input data may be skipped. | 07-12-2012 |
20120206447 | RECONFIGURABLE 3D GRAPHICS PROCESSOR - Briefly, in accordance with one or more embodiments, a reconfigurable 3D graphics processor includes a pipeline configuration manager, a rasterizer, and a memory coupled to the triangle rasterizer. The pipeline configuration manager is capable of configuring the graphics processor to operate in a direct rasterizing mode or a tiling mode to process a sequence of drawing commands received from a processing unit. | 08-16-2012 |
20130093766 | INTERPOLATION OF VERTEX ATTRIBUTES IN A GRAPHICS PROCESSOR - Vertex data can be accessed for a graphics primitive. The vertex data includes homogeneous coordinates for each vertex of the primitive. The homogeneous coordinates can be used to determine perspective-correct barycentric coordinates that are normalized by the area of the primitive. The normalized perspective-correct barycentric coordinates can be used to determine an interpolated value of an attribute for the pixel. These operations can be performed using adders and multipliers implemented in hardware. | 04-18-2013 |
Patent application number | Description | Published |
20120167849 | Engine Emissions Control System Green Engine Development - High Temperature application Linear Actuator with control system to regulate emissions in an internal combustion engine through variable valve opening and valve duration. | 07-05-2012 |
20130327969 | LINEAR VALVE ACTUATOR SYSTEM AND METHOD FOR CONTROLLING VALVE OPERATION - The system, according to one embodiment of the present invention, comprises a stationary coil linear motor to drive a valve with a stem comprising a ferromagnetic property. The linear motor moves the valve in response to control governed by an electronic valve control computer. The valve is movable between a closed position at a selectable rate of both acceleration and speed for a selectable distance (“lift”) to a second selectable open position, including all position variations between the fully open and fully closed states. Valve position, velocity and acceleration can be varied both during a valve stroke and from one stroke to the next, as controlled by the logic programmed on a non-transitive memory of the electronic valve control computer. | 12-12-2013 |
20150240736 | LINEAR VALVE ACTUATOR SYSTEM AND METHOD FOR CONTROLLING VALVE OPERATION - The system, according to one embodiment of the present invention, comprises a stationary coil linear motor to drive a valve with a stem comprising a ferromagnetic property. The linear motor moves the valve in response to control governed by an electronic valve control computer. The valve is movable between a closed position at a selectable rate of both acceleration and speed for a selectable distance (“lift”) to a second selectable open position, including all position variations between the fully open and fully closed states. Valve position, velocity and acceleration can be varied both during a valve stroke and from one stroke to the next, as controlled by the logic programmed on a non-transitive memory of the electronic valve control computer. | 08-27-2015 |