Ofner
Bernd Ofner, Hebertshausen DE
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20100031936 | Supercharged Internal Combustion Engine and Method for Monitoring Whether the Crankcase Vent Has Been Connected - A supercharged internal combustion engine in a motor vehicle includes a venting device for the crankcase of the internal combustion engine and a compressor for supercharging the internal combustion engine. A discharge opening for discharging the crankcase gas is provided upstream of the compressor and a sensor for determining the charge pressure of the compressor is provided downstream of the compressor. The discharge opening is connected to the crankcase by a first connection for the airflow, in particular a hose connection. In order to cost-effectively monitor the venting of the crankcase of the internal combustion engine, an opening, to which the charge pressure of the compressor is applied, is provided downstream of the compressor. The first connection for the airflow includes a closing device for closing the opening to which the charge pressure is applied, wherein the closing device closes the opening if the first connection is connected to the discharge opening. | 02-11-2010 |
Bertram Ofner, Kapfenberg AT
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20110214830 | METHOD AND APPARATUS FOR PRODUCING HOLLOW FUSING BLOCKS - To produce hollow ingots, at least two consumable electrodes having a diameter of at least 1.0 times the wall thickness of the hollow ingots are melted in a short, water-cooled mold that is flared particularly in a T-shape in the area of the consumable electrodes, wherein the inner wall of the hollow ingot is formed by a mandrel with a conicity of at least 1.5% that is installed in the mold from above, and the level of the liquid heel is maintained below the T-shaped flaring of the mold. | 09-08-2011 |
Gerald Ofner US
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20110020985 | Integrated Circuit Package and a Method for Forming an Integrated Circuit Package - A method of forming an integrated circuit package, such as a Flip Chip package, in which a void is provided in the underfill material in the central region of the package between the chip or die and the substrate on which the chip or die is mounted. This reduces delamination of the package as a result of moisture. | 01-27-2011 |
Gerald Ofner, Singapore SG
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20100314721 | Semiconductor Package and Method for Producing the Same - A semiconductor package includes a rewiring substrate and a semiconductor chip. The semiconductor chip includes: a first face with an active surface including integrated circuit devices and chip contact pads, a second face lying in a plane essentially parallel to the first face and side faces. Each side face of the semiconductor chip lies in a plane essentially perpendicular to the first and second faces. At least one edge between two mutually essentially perpendicular faces of the semiconductor chip includes a surface. | 12-16-2010 |
Gerald Ofner, Regensburg DE
Patent application number | Description | Published |
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20080265367 | Magnetically Alignable Integrated Circuit Device - An integrated circuit device includes a semiconductor chip having an active surface with a plurality of chip contact pads, a rewiring substrate and an electrically conductive inductor coil for magnetically aligning the semiconductor chip with the rewiring substrate. | 10-30-2008 |
20100001396 | REPAIRABLE SEMICONDUCTOR DEVICE AND METHOD - Repairable semiconductor device and method. In one embodiment a method, provides a first body having a first semiconductor chip and a first metal layer. A second body includes a second semiconductor chip and a second metal layer. Metal of the first metal layer is removed. The first semiconductor chip is removed from the first body. The second body is attached to the first body. The first metal layer is electrically coupled to the second metal layer. | 01-07-2010 |
20110241218 | Electronic Device and Manufacturing Method - A semiconductor package includes a semiconductor chip, an encapsulant embedding the semiconductor chip, first contact pads on a first main face of the semiconductor package and second contact pads on a second main face of the semiconductor package opposite to the first main face. The diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧(8/25)x+142 μm, wherein x is the pitch of the second contact pads in micrometers. | 10-06-2011 |
20120038063 | REPAIRABLE SEMICONDUCTOR DEVICE AND METHOD - Repairable semiconductor device and method. In one embodiment a method, provides a first body having a first semiconductor chip and a first metal layer. A second body includes a second semiconductor chip and a second metal layer. Metal of the first metal layer is removed. The first semiconductor chip is removed from the first body. The second body is attached to the first body. The first metal layer is electrically coupled to the second metal layer. | 02-16-2012 |
20120208319 | Packaged Semiconductor Device with Encapsulant Embedding Semiconductor Chip that Includes Contact Pads - A method of manufacturing a semiconductor package includes embedding a semiconductor chip in an encapsulant. First contact pads are formed on a first main face of the semiconductor package and second contact pads are formed on a second main face of the semiconductor package opposite the first main face. A diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧(8/25)x+142 μm, where x is a pitch of the second contact pads in micrometers. | 08-16-2012 |
20130175686 | Enhanced Flip Chip Package - A flip chip package structure is proposed in which a redistribution layer (RDL) is disposed on a surface of both a semiconductor chip and one or more lateral extensions of the semiconductor chip surface. The lateral extensions may be made using, e.g., a reconstituted wafer to implement a fanout region lateral to one or more sides of the semiconductor chip. One or more electrical connectors such as solder bumps or copper cylinders may be applied to the RDL, and an interposer such as a PCB interposer may be connected to the electrical connectors. In this way, a relatively tight semiconductor pad pitch may be accommodated and translated to an appropriate circuit board pitch without necessarily requiring a silicon or glass interposer. | 07-11-2013 |
20130328191 | CTE ADAPTION IN A SEMICONDUCTOR PACKAGE - A device such as a wafer-level package (WLP) device is proposed in which a dielectric layer is disposed between a surface of a semiconductor device and a surface of a redistribution layer (RDL). The dielectric layer may have at least one interconnect extending through the dielectric layer. The dielectric layer may have a coefficient of thermal expansion (CTE) value in a direction perpendicular to the surface of the semiconductor device that is less than a threshold value, and a Young's modulus that is greater than another threshold value. The dielectric layer may have a CTE value in a direction parallel to the surface of the semiconductor device at a surface of the dielectric layer facing the RDL that is greater than another threshold value | 12-12-2013 |
20140015131 | STACKED FAN-OUT SEMICONDUCTOR CHIP - A stacked semiconductor device and method of manufacturing a stacked semiconductor device are described. The semiconductor device may include a reconstituted base layer having a plurality of embedded semiconductor chips. A first redistribution layer may contact the electrically conductive contacts of the embedded chips and extend beyond the boundary of one or more of the embedded chips, forming a fan-out area. Another chip may be stacked above the chips embedded in the base layer and be electrically connected to the embedded chips by a second redistribution layer. Additional layers of chips may be included in the semiconductor device. | 01-16-2014 |
20140138827 | ENHANCED FLIP CHIP PACKAGE - According to various embodiments, a flip chip package structure is provided in which a redistribution layer (RDL) is disposed on a surface of both a semiconductor chip and one or more lateral extensions of the semiconductor chip surface. The lateral extensions may be made using, e.g., a reconstituted wafer to implement a fanout region lateral to one or more sides of the semiconductor chip. One or more electrical connectors such as solder bumps or copper cylinders may be applied to the RDL, and an interposer such as a PCB interposer may be connected to the electrical connectors. In this way, a relatively tight semiconductor pad pitch may be accommodated and translated to an appropriate circuit board pitch without necessarily requiring a silicon or glass interposer. | 05-22-2014 |
20140306355 | CHIP INTERPOSER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A chip interposer may include: a first interconnect level including a first pad; and a second interconnect level including a second pad, wherein the second pad may face in the same direction as the first pad. | 10-16-2014 |
20140361387 | CHIP ARRANGEMENT AND METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - A chip arrangement may include: a mold compound; and a microelectromechanical systems device at least partially embedded in the mold compound. | 12-11-2014 |
20150028478 | SEMICONDUCTOR DEVICES - A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion. | 01-29-2015 |
Gerald Ofner, Schierling DE
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20090160053 | METHOD OF MANUFACTURING A SEMICONDUCOTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. One embodiment provides a carrier. Semiconductor chips are placed over the carrier. The semiconductor chips include contact elements. A polymer material is applied over the semiconductor chips and the carrier. The polymer material is removed until the contact elements are exposed. The carrier is removed from the semiconductor chips. | 06-25-2009 |
20110291274 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. One embodiment provides a carrier. Semiconductor chips are placed over the carrier. The semiconductor chips include contact elements. A polymer material is applied over the semiconductor chips and the carrier. The polymer material is removed until the contact elements are exposed. The carrier is removed from the semiconductor chips. | 12-01-2011 |
Hanspeter Ofner, Pucking AT
Patent application number | Description | Published |
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20080289450 | Conveyor System, Composite System and Method For Coupling Metallurgical Methods - A conveying system comprising elements for conveying lumpy, particularly hot, conveying stock and a cover for shielding the conveying stock. Disclosed are measures for inerting the conveying stock. A combined system encompasses a reduction plant for reducing oxides in a continuous process and processing unit for producing liquid metal in a discontinuous process. The reduction product is deliverable from the reduction plant to the processing unit. A method for coupling a reduction method used for reducing oxides in a continuous process and a method used for producing liquid metal in a discontinuous process. A reduction product from the reduction method is fed to the liquid metal production method for processing. | 11-27-2008 |
20110101577 | CONVEYOR SYSTEM, COMPOSITE SYSTEM AND METHOD FOR COUPLING METALLURGICAL METHODS - A conveying system comprising elements for conveying lumpy, particularly hot, conveying stock and a cover for shielding the conveying stock. Disclosed are measures for inerting the conveying stock. A combined system encompasses a reduction plant for reducing oxides in a continuous process and processing unit for producing liquid metal in a discontinuous process. The reduction product is deliverable from the reduction plant to the processing unit. A method for coupling a reduction method used for reducing oxides in a continuous process and a method used for producing liquid metal in a discontinuous process. A reduction product from the reduction method is fed to the liquid metal production method for processing. | 05-05-2011 |
Silvio Ofner, Muenchenstein CH
Patent application number | Description | Published |
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20080242698 | Organic Compounds - The invention relates to novel diamines of the formula | 10-02-2008 |
20120010263 | ACETYLENE DERIVATIVES HAVING MGLUR 5 ANTAGONISTIC ACTIVITY - The invention provides compounds of formula I | 01-12-2012 |
20120101110 | Diaza-spiro[5.5]undecanes - The invention relates to compound of the formula I | 04-26-2012 |
20120165331 | Di/tri-aza-spiro-C9-C11alkanes - The invention relates to compounds of the formula I | 06-28-2012 |
20120264748 | DIAZA-SPIRO[5.5]UNDECANES - The invention relates to compound of the formula (I), in which the substituents are as defined in the specification; in free form or in salt form; to its preparation, to its use as medicament and to medicaments comprising it. | 10-18-2012 |
20130274294 | 4-(Hetero)Aryl-Ethynyl-Octahydro-Indole-1-Esters - The invention relates to compound of the formula (I) or a salt thereof, wherein the substituents are as defined in the specification; to its preparation, to its use as medicament and to medicaments comprising it. | 10-17-2013 |
20130281463 | DIAZA-SPIRO[5.5]UNDECANES USEFUL AS OREXIN RECEPTOR ANTAGONISTS - The invention relates to compound of the formula (I), in which the substituents are as defined in the specification; in free form or in salt form; to its preparation, to its use as medicament and to medicaments comprising it. | 10-24-2013 |
20130331568 | ACETYLENE DERIVATIVES HAVING MGLUR 5 ANTAGONISTIC ACTIVITY - The invention provides compounds of formula I | 12-12-2013 |
Silvio Ofner, Basel CH
Patent application number | Description | Published |
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20110288057 | SALICYLIC ACID DERIVATIVES BEING FARNESYL PYROPHOSPHATE SYNTHASE ACTIVITY INHIBITORS - The invention relates to the use of and mainly novel compounds of the formula I | 11-24-2011 |
20120094958 | QUINOLINES AS INHIBITORS OF FARNESYL PYROPHOSPHATE SYNTHASE - The invention relates to a compound of formula (I) wherein the substituents are as described in the specification, which are useful as farnesyl pyrophosphate synthase modulators, e.g. in the treatment of proliferative diseases, to methods of manufacturing such compounds and to intermediates thereof. | 04-19-2012 |