Patent application number | Description | Published |
20100277989 | INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS - Providing increased capacity in heterogeneous storage elements including a method for storing data including a write process writing to a memory and a read process reading from the memory. Physical characteristics of memory cells in the memory support different sets of data levels. The write process takes into account the different sets of data levels when writing to the memory. The read process first obtains data in the memory and subsequently determines how to interpret the data. | 11-04-2010 |
20100281340 | ADAPTIVE ENDURANCE CODING OF NON-VOLATILE MEMORIES - Adaptive endurance coding including a method for storing data that includes receiving write data and a write address. A compression algorithm is applied to the write data to generate compressed data. An endurance code is applied to the compressed data to generate a codeword. The endurance code is selected and applied in response to the amount of space saved by applying the compression to the write data. The codeword is written to the write address. | 11-04-2010 |
20110019002 | Method and System for Low Complexity Analysis of Multiple Signals Using a Combined Sparse Set of Samples - A method of and system for signal analysis includes acquiring multiple signals from the environment by using multiple sensor elements, applying a transform which combines the multiple acquired signals into a single combined signal, and reduces the number of samples in the combined signal, applying a single signal analysis and event detection operation on the resultant combined, sparse signal, and performing a complete signal analysis using multiple analysis elements for the multiple input signals only in the case where the sparse signal analysis indicates that the event of interest may be present. | 01-27-2011 |
20110103580 | COMPRESSING ENCRYPTED DATA WITHOUT THE ENCRYPTION KEY - A method, system and computer program product are disclosed for compressing encrypted data, wherein the data is encrypted by using a block encryption algorithm in a chained mode of operation, and the encrypted data is comprised of a set of N encrypted blocks, C | 05-05-2011 |
20110138104 | MULTI-WRITE CODING OF NON-VOLATILE MEMORIES - Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code such that the first codeword encodes the write data and is consistent with a target set of distributions of electrical charge levels in the memory page; and writing the first codeword to the memory page. If the memory page is in the previously written state: selecting a coset from a linear code such that the coset encodes the write data and includes one or more words that are consistent with previously written content of the memory page; selecting a subsequent codeword from the one or more words in the coset; and writing the subsequent codeword to the memory page. | 06-09-2011 |
20110138105 | NON-VOLATILE MEMORIES WITH ENHANCED WRITE PERFORMANCE AND ENDURANCE - Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate. | 06-09-2011 |
20110187565 | EFFICIENT RATELESS DISTRIBUTED COMPRESSION OF NON-BINARY SOURCES - A method, system and computer program product are disclosed for rateless compression of non-binary sources. In one embodiment, the method comprises representing a sequence of non-binary source symbols as a sequence of sets of binary values; selecting a code for compressing the sets of binary values; determining a puncturing pattern, based on the selected code; and puncturing the sets of binary values, in patterns based on the puncturing pattern, to form a sequence of unpunctured values. A sequence of computed syndromes is determined based on the sequence of non-binary source symbols; and the sequence of unpunctured values and the sequence of computed syndromes are combined to form an output stream of data representing said sequence of non-binary source symbols. In one embodiment, none of the sets of binary values is punctured completely, and, for example, each of the sets of binary values may be punctured only partially. | 08-04-2011 |
20120287714 | INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS - Providing increased capacity in heterogeneous storage elements including a method for reading from memory. The method includes receiving a read word from a block of memory cells, where physical characteristics of the memory cells support different sets of data levels. The read word is separated into two or more virtual read vectors. For each of the virtual read vectors, the codebook that was utilized to generate the virtual read vector is identified and a partial read data vector is generated. The generating includes multiplying the virtual read vector by a matrix that represents the codebook. The partial read data vectors are combined into a read message and the read message is output. | 11-15-2012 |
20120290898 | ADAPTIVE ENDURANCE CODING OF NON-VOLATILE MEMORIES - Adaptive endurance coding including a method for accessing memory that includes retrieving a codeword from a memory address. The codeword is multiplied by a metadata matrix to recover metadata for the codeword. The metadata includes a data location specification. The data in the codeword is identified in response to the metadata and the data is output as read data. | 11-15-2012 |
Patent application number | Description | Published |
20080288929 | METHOD AND APPARATUS FOR RUN-TIME STATISTICS DEPENDENT PROGRAM EXECUTION USING SOURCE-CODING - Disclosed are a method and system for optimized, dynamic data-dependent program execution. The disclosed system comprises a statistics computer which computes statistics of the incoming data at the current time instant, where the said statistics include the probability distribution of the incoming data, the probability distribution over program modules induced by the incoming data, the probability distribution induced over program outputs by the incoming data, and the time-complexity of each program module for the incoming data, wherein the said statistics are computed on as a function of current and past data, and previously computed statistics; a plurality of alternative execution path orders designed prior to run-time by the use of an appropriate source code; a source code selector which selects one of the execution path orders as a function of the statistics computed by the statistics computer; a complexity measurement which measures the time-complexity of the currently selected execution path-order. | 11-20-2008 |
20080320363 | METHOD AND APPARATUS FOR RATELESS SOURCE CODING WITH/WITHOUT DECODER SIDE INFORMATION - A method of and system for rateless source coding are disclosed. The method comprises the steps of providing a set of low-density parity check (LDPC) codes, each of which accepts a range of data input lengths and a range of target compression rates; identifying a data input having a data input length; and identifying a desired compression rate. The method comprises the further steps of selecting one of said LDPC codes based on said data input length and desired compression rate; encoding the data input, using the selected LDPC code, to generate a sequence of data values; and puncturing some of said encoded data values to achieve the desired compression rate. Preferably, the encoding step includes the steps of generating a syndrome and a parity sequence from the data input, puncturing the generated parity sequence, and mixing a remaining portion of the data input with the punctuated parity sequence. | 12-25-2008 |
20090030922 | Method and Apparatus for Constructing Efficient Slepian-Wolf Codes With Mismatched Decoding - Disclosed is a method for constructing Slepian-Wolf codes, wherein the designed Slepian-Wolf codes are robust to mismatched decoding. The disclosed method for constructing Slepian-Wolf codes includes the steps of: choosing representative probability distributions from a set of possible probability distributions; choosing a probability distribution as a decoding metric; converting the chosen decoding metric to a cyclic-symmetric channel; computing the initial message value given the cyclic-symmetric channel; computing a set of probability distributions of the initial message given the initial message values and the representative probability distributions; optimizing the degree distribution given the set of probability distributions of the initial message; optimizing the decoding metric. | 01-29-2009 |
20090122868 | METHOD AND SYSTEM FOR EFFICIENT VIDEO COMPRESSION WITH LOW-COMPLEXITY ENCODER - Disclosed are a method and system for video compression, wherein the video encoder has low computational complexity and high compression efficiency. The disclosed system comprises a video encoder and a video decoder, wherein the method for encoding includes the steps of converting a source frame into a space-frequency representation; estimating conditional statistics of at least one vector of space-frequency coefficients; estimating encoding rates based on the said conditional statistics; and applying Slepian-Wolf codes with the said computed encoding rates. The preferred method for decoding includes the steps of; generating a side-information vector of frequency coefficients based on previously decoded source data, encoder statistics, and previous reconstructions of the source frequency vector; and performing Slepian-Wolf decoding of at least one source frequency vector based on the generated side-information, the Slepian-Wolf code bits and the encoder statistics. | 05-14-2009 |
20090323798 | METHOD AND SYSTEM FOR LOW-COMPLEXITY SLEPIAN-WOLF RATE ESTIMATION IN WYNER-ZIV VIDEO ENCODING - A method and system for low-complexity Slepian-Wolf rate estimator in a hybrid Wyner-Ziv video encoder determines the minimum Slepian-Wolf code rate required to allow correct decoding. The Slepian-Wolf estimator does not assume ideality of source and side-information statistics and does not require the presence of a feedback channel from the decoder to the encoder in order to determine the correct Slepian-Wolf coding rate. Instead, it adapts to the statistical properties of the video steam. The Slepian-Wolf estimator provides very efficient compression performance while avoiding Slepian-Wolf decoding failures. | 12-31-2009 |
20100095116 | Method and System for Secure Collaboration Using Slepian-Wolf Codes - A method and system provide for secure sharing of arbitrary data between users with limited mutual trust. A user can encode its information by using a Slepian-Wolf code at a rate which enables a second user to correctly decode only if the side-information it has satisfies a conditional entropy constraint. The key advantages are as follows. Firstly, it is very flexible, in that it enables secure sharing for general data including multimedia data. Secondly, by appropriate Slepian-Wolf code selection, it enables compression in conjunction with security. Thirdly, it can be used for the case where the data model is imperfectly known and trust is to be built up incrementally. | 04-15-2010 |
20110246703 | CONSTRAINED CODING TO REDUCE FLOATING GATE COUPLING IN NON-VOLATILE MEMORIES - Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword. | 10-06-2011 |
20110320881 | ISOLATION OF FAULTY LINKS IN A TRANSMISSION MEDIUM - Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link. | 12-29-2011 |
20120281750 | METHOD AND SYSTEM FOR CODING MODE SELECTION IN VIDEO COMPRESSION SYSTEMS - A method and system are disclosed for selecting a mode to encode video data. The method comprises the steps of (a) transforming a source video frame into a set of coefficients, (b) partitioning said set of coefficients into a plurality of subsets of the coefficients on the basis of probability statistics corresponding to a plurality of encoding modes, wherein each of said subsets is identified for encoding by one of the plurality of encoding modes. The method comprises the further steps of (c) for each of the plurality of subsets of coefficients, computing defined parameters of an associated probability distribution for said subset, and (d) repeating steps (b) and (c) until a predetermined termination condition is satisfied. When this predetermined termination condition is satisfied, the subsets of coefficients, as they exist at that time, are output to a video encoder, which preferably is a Wyner-Ziv encoder. | 11-08-2012 |
20120290778 | INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS - Providing increased capacity in heterogeneous storage elements including a method for storing data in a heterogeneous memory that includes receiving a write message and a write address corresponding to a block of memory cells where at least two of the memory cells support different data levels, determining physical characteristics of the memory cells, and identifying virtual memories associated with the block of memory cells in response to the physical characteristics. The following is performed for each of the virtual memories: generating a constraint vector that describes the virtual cells in the virtual memory; and calculating a virtual write vector in response to the constraint vector and the write data, the calculating including writing the write data, bit by bit, in order, into the virtual memory, skipping locations known to be stuck to a particular value as indicated by the constraint vector. The virtual write vectors are combined into a write word and the write word is output to the block of memory cells. | 11-15-2012 |
20120311262 | MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE - Memory cell presetting for improved performance including a system that includes a memory, a cache, and a memory controller. The memory includes memory lines made up of memory cells. The cache includes cache lines that correspond to a subset of the memory lines. The memory controller is in communication with the memory and the cache. The memory controller is configured to perform a method that includes scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state. | 12-06-2012 |
20130013860 | MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE - Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting. | 01-10-2013 |
20130018889 | Lossless compression of high nominal-range dataAANM Jagmohan; AshishAACI IrvingtonAAST NYAACO USAAGP Jagmohan; Ashish Irvington NY USAANM Knight; Joshua W.AACI Mohegan LakeAAST NYAACO USAAGP Knight; Joshua W. Mohegan Lake NY USAANM Lastras-Montano; Luis A.AACI Cortlandt ManorAAST NYAACO USAAGP Lastras-Montano; Luis A. Cortlandt Manor NY US - A method for receiving a data stream that includes data samples, each data sample having one of a plurality of actual values. For each data sample in the data stream, a first index in a dictionary is selected. The dictionary includes indices corresponding to each of the plurality of actual values. The first index corresponds to an actual value of the data sample. A predicted value of the data sample is generated in response to previously received data samples in the data stream and to a prediction algorithm. A second index in the dictionary that corresponds to an actual value in the dictionary that is closest to the value of the predicted value is selected. The difference between the first index and the second index is calculated and compressed. The compressed difference between the first index and the second index is then output. This process is performed for each data sample in the data stream. | 01-17-2013 |
20130019029 | LOSSLESS COMPRESSION OF A PREDICTIVE DATA STREAM HAVING MIXED DATA TYPESAANM Jagmohan; AshishAACI IrvingtonAAST NYAACO USAAGP Jagmohan; Ashish Irvington NY USAANM Lastras-Montano; Luis A.AACI Cortlandt ManorAAST NYAACO USAAGP Lastras-Montano; Luis A. Cortlandt Manor NY US - Lossless compression of a data stream having mixed data types, including a method for receiving a data stream that includes a plurality of different types of bit groups. Bit groups of at least two different types are extracted from the data stream to form a sub-stream. Circular shifts of the sub-stream are generated and then sorted into a sorted list of circular shifts. A transformed string that includes a bit group from each of the circular shifts is extracted from the sorted list of circular shifts. A location in the transformed string of a bit group from a pre-determined location in the sub-stream is identified. The transformed string is partitioned between the at least two different types of bit groups into transformed string partitions, and the transformed string partitions are compressed to form compressed transformed string partitions. The compressed transformed string partitions and the location are output. | 01-17-2013 |
20130166821 | LOW LATENCY AND PERSISTENT DATA STORAGE - Persistent data storage with low latency is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed. | 06-27-2013 |
20130166822 | SOLID-STATE STORAGE MANAGEMENT - Solid-state storage management for a system that includes a main board and a solid-state storage board separate from the main board is provided. The sold-state storage board includes a solid-state memory device and solid-state storage devices. The system is configured to perform a method that includes a correspondence being established, by a software module located on the main board, between a first logical address and a first physical address on the solid-state storage devices. The correspondence between the first logical address and the first physical address is stored in a location on the solid-state memory device. The method also includes translating the first logical address into the first physical address. The translating is performed by an address translator module located on the solid-state storage board and is based on the previously established correspondence between the first logical address and the first physical address. | 06-27-2013 |
20130166826 | SOLID-STATE DEVICE MANAGEMENT - An embodiment is a method for establishing a correspondence between a first logical address and a first physical address on solid-state storage devices located on a solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses, and the establishing is by a software module located on a main board that is separate from the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in in a location on a solid-state memory device that is accessible by an address translator module located on the solid-state storage board. The solid-state memory device is located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address. | 06-27-2013 |
20130339570 | VARIABILITY AWARE WEAR LEVELING - Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products. | 12-19-2013 |
20130339574 | VARIABILITY AWARE WEAR LEVELING - Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products. | 12-19-2013 |
20140043927 | METHOD FOR OPTIMIZING REFRESH RATE FOR DRAM - A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set. | 02-13-2014 |
20140063997 | DRAM REFRESH - A refresh of a DRAM having at least a fast and a slow refresh rate includes encoding a pointer on a row or rows with refresh information, reading the refresh information, and incrementing a fast refresh address counter with the refresh information. The refresh may be performed by encoding one or more cells on a row that may require a fast refresh, one or more cells on a group of rows that may require a fast refresh, or one or more cells on a row that may not require a fast refresh. | 03-06-2014 |
20140136769 | SOLID-STATE STORAGE MANAGEMENT - Solid-state storage management for a system, the management including establishing, externally to a solid-state storage board, a correspondence between a first logical address and a first physical address on solid-state storage devices located on the solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses. The correspondence between the first logical address and the first physical address is accepted by the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in a location on a solid-state memory device that is accessible by an address translator module, the address translator module and the solid-state memory device located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address. | 05-15-2014 |
20140136770 | LOW LATENCY AND PERSISTENT DATA STORAGE - Persistent data storage with low latency is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed. | 05-15-2014 |
20140164692 | MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING - This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data. | 06-12-2014 |
20140164820 | MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING - This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data. | 06-12-2014 |
20140164871 | DRAM ERROR DETECTION, EVALUATION, AND CORRECTION - This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data. | 06-12-2014 |
20140164874 | DRAM ERROR DETECTION, EVALUATION, AND CORRECTION - This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data. | 06-12-2014 |
20140201044 | DETERMINING A PAYMENT POLICY - A method of generating a recommendation reducing a cost of subject attrition includes generating a plurality of policies, wherein each of the plurality of policies models a dependence of an attrition risk of each of a plurality of subject categories on a plurality of payment components of the plurality of subject categories, and each of the plurality of policies is associated with a respective set of weights on the plurality of subject categories, determining a benefit of each of the plurality of policies, selecting a selected policy from among the plurality of policies according to the benefit, and generating a recommendation for adjusting a specific payment component of a specific subject for each policy according to the selected policy. | 07-17-2014 |
20140201047 | DETERMINING A PAYMENT POLICY - A method of generating a recommendation reducing a cost of subject attrition includes generating a plurality of policies, wherein each of the plurality of policies models a dependence of an attrition risk of each of a plurality of subject categories on a plurality of payment components of the plurality of subject categories, and each of the plurality of policies is associated with a respective set of weights on the plurality of subject categories, determining a benefit of each of the plurality of policies, selecting a selected policy from among the plurality of policies according to the benefit, and generating a recommendation for adjusting a specific payment component of a specific subject for each policy according to the selected policy. | 07-17-2014 |
20140223117 | SECURING THE CONTENTS OF A MEMORY DRIVE - A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device. | 08-07-2014 |
20140223120 | SECURING THE CONTENTS OF A MEMORY DEVICE - A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device. | 08-07-2014 |
20140359197 | IMPLEMENTING REINFORCEMENT LEARNING BASED FLASH CONTROL - A method and system are provided for implementing enhanced flash storage control using reinforcement learning to provide enhanced performance metrics. A flash controller, such as a Reinforcement Learning (RL) flash controller, is coupled to a flash storage. The flash controller defines a feature set of flash parameters determined by a predefined one of a plurality of optimization metrics. The optimization metric is adapted dynamically based upon system workload and system state. The flash controller employing the feature set including at least one feature responsive to erase operations; computes a current system state responsive to the employed feature set; selects actions at each time step by sensing the computed current system state for performing an action to maximize a long term reward, and moves to another state in the system while obtaining a short-term reward for the performed action. | 12-04-2014 |
20140365480 | PERSONALIZED LOW LATENCY COMMUNICATION - Embodiments relate to personalized low latency communications. A method may include receiving a description of content of a message, receiving recipient data corresponding to at least two possible recipients within a population of possible recipients, and selecting a relevant subpopulation of the population. The selecting may include, for each of the at least two possible recipients, ranking a strength of an indirect relationship between the description and the recipient data. The indirect relationship may be based on the description, the recipient data and at least one additional data source. The selecting may also include, for each of the at least two possible recipients, adding a possible recipient to the relevant subpopulation based on the ranking of the indirect relationship associated with the possible recipient. The method may further include initiating a two-way communication channel between a sender of the message and the relevant subpopulation. | 12-11-2014 |
20140365503 | ESTIMATION OF CLOSENESS OF TOPICS BASED ON GRAPH ANALYTICS - Embodiments relate to estimating closeness of topics based on graph analytics. A graph that includes a plurality of nodes and edges is accessed. Each node in the graph represents a topic and each edge represents a known association between two topics. A statistical traversal experiment is performed on the graph. A strength of relations between any two topics represented by nodes in the graph is inferred based on statistics extracted from the statistical traversal experiment. | 12-11-2014 |
20140365504 | ESTIMATION OF CLOSENESS OF TOPICS BASED ON GRAPH ANALYTICS - Embodiments relate to estimating closeness of topics based on graph analytics. A graph that includes a plurality of nodes and edges is accessed. Each node in the graph represents a topic and each edge represents a known association between two topics. A statistical traversal experiment is performed on the graph. A strength of relations between any two topics represented by nodes in the graph is inferred based on statistics extracted from the statistical traversal experiment. | 12-11-2014 |
20140365584 | PERSONALIZED LOW LATENCY COMMUNICATION - Embodiments relate to personalized low latency communications. A method may include receiving a description of content of a message, receiving recipient data corresponding to at least two possible recipients within a population of possible recipients, and selecting a relevant subpopulation of the population. The selecting may include, for each of the at least two possible recipients, ranking a strength of an indirect relationship between the description and the recipient data. The indirect relationship may be based on the description, the recipient data and at least one additional data source. The selecting may also include, for each of the at least two possible recipients, adding a possible recipient to the relevant subpopulation based on the ranking of the indirect relationship associated with the possible recipient. The method may further include initiating a two-way communication channel between a sender of the message and the relevant subpopulation. | 12-11-2014 |
Patent application number | Description | Published |
20110206145 | Methods and Apparatus for Secure Distribution and Storage of Data Using N Channels - Methods and apparatus are provided for secure distribution and storage of data using N channels. An input data sequence, X, is distributed using a plurality, N, of channels. In one embodiment, the input data sequence, X, is split into N subsequences; and the N subsequences are encoded into N bit streams using a set of Slepian-Wolf codes with N separate encoders and a joint decoder. The Slepian-Wolf codes can be selected to ensure a computational complexity to obtain a portion of the input data sequence grows exponentially with respect to a length of the input data sequence unless all of the N bit streams are compromised. In another embodiment, the input data sequence, X, is compressed using a lossless data compressing techniques; and the compressed input data sequence is split into N subsequences that are distributed. | 08-25-2011 |
20110307670 | ENCODING DATA INTO CONSTRAINED MEMORY - Encoding data into constrained memory using a method for writing data that includes receiving write data to be encoded into a write word, receiving constraints on symbol values associated with the write word, encoding the write data into the write word, and writing the write word to a memory. The encoding includes: representing the write data and the constraints as a first linear system in a first field of a first size; embedding the first linear system into a second linear system in a second field of a second size, the second size larger than the first size; solving the second linear system in the second field resulting in a solution; and collapsing the solution into the first field resulting in the write word, the write word satisfying the constraints on symbol values associated with the write word. | 12-15-2011 |
20120096328 | MULTI-WRITE ENDURANCE AND ERROR CONTROL CODING OF NON-VOLATILE MEMORIES - Multi-write endurance and error control coding of non-volatile memories including a method for receiving write data and a write address of a memory page in a memory. The write data is partitioned into a plurality of sub-blocks, each sub-block including q bits of the write data. Error correction bits are generated at the computer in response to the sub-blocks and to an error correction code (ECC). At least one additional sub-block containing the error correction bits are appended to the partitioned write data and a write word is generated. The write word is generated by performing for each of the sub-blocks: selecting a codeword such that the codeword encodes the sub-block and is consistent with current electrical charge levels of the plurality of memory cells associated with the memory page; concatenating the selected codewords to form the write word; and writing the write word to the memory page. | 04-19-2012 |
20120144249 | Program Disturb Error Logging and Correction for Flash Memory - Program disturb error logging and correction for a flash memory including a computer implemented method for storing data. The method includes receiving a write request that includes data and a write address of a target page in a memory. A previously programmed page at a specified offset from the target page is read from the memory. Contents of the previously programmed page are compared to an expected value of the previously programmed page. Error data is stored in an error log in response to contents of the previously programmed page being different than the expected value of the previously programmed page, the error data describing an error in the previously programmed page and the error data used by a next read operation to the previously programmed page to correct the error in the previously programmed page. The received data is written to the target page in the memory. | 06-07-2012 |
20120144272 | PROBABILISTIC MULTI-TIER ERROR CORRECTION IN NOT-AND (NAND) FLASH MEMORY - Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output. | 06-07-2012 |
20120226962 | WEAR-FOCUSING OF NON-VOLATILE MEMORIES FOR IMPROVED ENDURANCE - Storing data in memory using wear-focusing techniques for improved endurance. A method for storing the data includes receiving write data to be written into a memory that is logically divided into a plurality of regions. The plurality of regions includes a first region and a second region that are implemented by the same memory technology. The memory is subject to degradation as a result of write operations. The write data is classified as dynamic data or static data. The write data is encoded using a first type of encoding in response to the write data being classified as dynamic. The write data encoded using the first type of encoding is stored in the first region of the memory. The write data is encoded using a second type of encoding and stored in the second region of the memory in response to classifying the write data as static data. | 09-06-2012 |
20120226963 | BAD BLOCK MANAGEMENT FOR FLASH MEMORY - Bad block management for flash memory including a method for storing data. The method includes receiving a write request that includes write data. A block of memory is identified for storing the write data. The block of memory includes a plurality of pages. A bit error rate (BER) of the block of memory is determined and expanded write data is created from the write data in response to the BER exceeding a BER threshold. The expanded write data is characterized by an expected BER that is lower than the BER threshold. The expanded write data is encoded using an error correction code (ECC). The encoded expanded write data is written to the block of memory. | 09-06-2012 |
20130117544 | METHOD AND APPARATUS FOR RUN-TIME STATISTICS DEPENDENT PROGRAM EXECUTION USING SOURCE-CODING PRINCIPLES - Disclosed are a method and system for optimized, dynamic data-dependent program execution. The disclosed system comprises a statistics computer which computes statistics of the incoming data at the current time instant, where the said statistics include the probability distribution of the incoming data, the probability distribution over program modules induced by the incoming data, the probability distribution induced over program outputs by the incoming data, and the time-complexity of each program module for the incoming data, wherein the said statistics are computed on as a function of current and past data, and previously computed statistics; a plurality of alternative execution path orders designed prior to run-time by the use of an appropriate source code; a source code selector which selects one of the execution path orders as a function of the statistics computed by the statistics computer; a complexity measurement which measures the time-complexity of the currently selected execution path-order. | 05-09-2013 |
20130212427 | RECLAIMING DISCARDED SOLID STATE DEVICES - Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced. | 08-15-2013 |