Patent application number | Description | Published |
20080288848 | Latency by offsetting cyclic redundancy code lanes from data lanes - Embodiments of the invention are generally directed to systems, methods, and apparatuses for improving latency by offsetting cyclic redundancy check lanes from data. In some embodiments, a memory device includes a memory array to provide read data bits and a cyclic redundancy code (CRC) generator to generate CRC bits corresponding to the read data bits. In addition, the memory device may include a transmit framing unit to transmit the read data bits and the CRC bits to a host, wherein the transmit framing unit includes logic to offset the transmission of the CRC bits from the transmission of the read data bits based, at least in part, on an offset value. Other embodiments are described and claimed. | 11-20-2008 |
20080304330 | SYSTEMS, METHODS, AND APPARATUSES FOR TRANSMITTING DATA MASK BITS TO A MEMORY DEVICE - Embodiments of the invention are generally directed to systems, methods, and apparatuses for transferring data mask bits to a memory device. In some embodiments, an integrated circuit includes logic to issue a partial write command to a memory device. In addition, the integrated circuit may include logic to transfer a write frame to the volatile memory device over an N bit wide data bus, wherein the write frame includes one or more data mask bits to be transferred over the N bit wide data bus. | 12-11-2008 |
20090055714 | OPTIMIZING THE SIZE OF MEMORY DEVICES USED FOR ERROR CORRECTION CODE STORAGE - Embodiments of the invention are generally directed to systems, methods, and apparatuses for optimizing the size of memory devices used for error correction code storage. An apparatus (such as a memory module) may include a number of memory devices to store data and a memory device to store error correction (ECC) bits. In some embodiments, the memory devices to store data may have a density of N and the memory device to store ECC bits has a density of ½ N. | 02-26-2009 |
20090132888 | RELIABILITY, AVAILABILITY, AND SERVICEABILITY SOLUTIONS FOR MEMORY TECHNOLOGY - Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed. | 05-21-2009 |
20090172271 | SYSTEM AND METHOD FOR EXECUTING FULL AND PARTIAL WRITES TO DRAM IN A DIMM CONFIGURATION - In an embodiment of the invention, a host or other controller writing to multiple DRAMs in a DIMM configuration determines whether there is full write request to at least one of the multiple DRAM's and a partial write request to at least another one of the multiple DRAM's. If so, then the host parses data associated with the full write request into a first portion and a second portion. The host then outputs a first partial write command associated with the first portion and a second partial write command associated with the second portion to the DIMM. Other embodiments are described. | 07-02-2009 |
20090249169 | SYSTEMS, METHODS, AND APPARATUSES TO SAVE MEMORY SELF-REFRESH POWER - Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency of a DRAM is reduced and errors are allowed to occur. In error check mode, the DRAM stores data and corresponding error check bits. The error check bits may be used to scrub the memory and fix the errors. | 10-01-2009 |
20090313533 | EFFICIENT IN-BAND RELIABILITY WITH SEPARATE CYCLIC REDUNDANCY CODE FRAMES - Embodiments of the invention are generally directed to systems, methods, and apparatuses for efficient in-band reliability with separate cyclic redundancy code (CRC) frames. In some embodiments, a memory system uses data frames to transfer data between a host and a memory device. The system also uses a separate frame (e.g., a CRC frame) to transfer a CRC checksum that covers the data frames. | 12-17-2009 |
20090319877 | SYSTEMS, METHODS, AND APPARATUSES TO TRANSFER DATA AND DATA MASK BITS IN A COMMON FRAME WITH A SHARED ERROR BIT CODE - Embodiments of the invention are generally directed to systems, methods, and apparatuses to transfer data and data mask bits in a common frame with a shared error bit code. A memory system uses data frames to transfer data between a host and a memory device. In some cases, the system may also transfer one or more data mask bits in a data frame (rather than via a separate bit lane). The system may generate an error bit checksum (such as a cyclic redundancy code or CRC) to cover the data bits and the data mask bits. In some embodiments, the data bits, data mask bits, and checksum bits are transferred in a common frame. | 12-24-2009 |
20090327660 | MEMORY THROUGHPUT INCREASE VIA FINE GRANULARITY OF PRECHARGE MANAGEMENT - Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three separate precharge timings may be used, e.g., optimized per memory bank, per memory bank group, and/or per a memory device. Other embodiments are also disclosed and claimed. | 12-31-2009 |
20100064100 | SYSTEMS, METHODS, AND APPARATUSES FOR IN-BAND DATA MASK BIT TRANSMISSION - Embodiments of the invention are generally directed to systems, methods, and apparatuses for in-band data mask bit transmission. In some embodiments, one or more data mask bits are integrated into a partial write frame and are transferred to a memory device via the data bus. Since the data mask bits are transferred via the data bus, the system does not need (costly) data mask pin(s). In some embodiments, a mechanism is provided to enable a memory device (e.g., a DRAM) to check for valid data mask bits before completing the partial write to the DRAM array. | 03-11-2010 |
20100080076 | COMMON MEMORY DEVICE FOR VARIABLE DEVICE WIDTH AND SCALABLE PRE-FETCH AND PAGE SIZE - Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a x4 mode, a x8 mode, and a x16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM. | 04-01-2010 |
20100165780 | DYNAMIC RANDOM ACCESS MEMORY WITH SHADOW WRITES - Methods and apparatus are disclosed for reducing write-to-read turnaround times using shadow writes in memory controllers and in DRAM. Embodiments of controllers including shadow write control logic may, in response to receiving a write request, issue an external write column address strobe (CAS) to DRAM to latch a valid write CAS address, and assert a set of write data values to be stored in a set of DRAM locations corresponding to the write CAS address. After asserting the write CAS and prior to asserting the complete set of write data values, such memory controllers may, in response to receiving a read request, issue an external read CAS to DRAM to indicate a valid read CAS address. A set of read data values from a second set of DRAM locations corresponding to the read CAS address, are received with reduced turnaround time after asserting the complete set of write data values. | 07-01-2010 |
20100262889 | RELIABILITY, AVAILABILITY, AND SERVICEABILITY IN A MEMORY DEVICE - Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits. | 10-14-2010 |
20110128765 | IDENTIFYING AND ACCESSING INDIVIDUAL MEMORY DEVICES IN A MEMORY CHANNEL - In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register. | 06-02-2011 |
20110138261 | METHOD AND SYSTEM FOR ERROR MANAGEMENT IN A MEMORY DEVICE - A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command. | 06-09-2011 |
20110153925 | MEMORY CONTROLLER FUNCTIONALITIES TO SUPPORT DATA SWIZZLING - A memory controller that can determine a swizzling pattern between the memory controller and memory devices. The memory controller generates a swizzling map based on the determined swizzling pattern. The memory controller may internally swizzle data using the swizzling map before writing the data to memory so that the data appears in the correct order at the pins of the memory chip(s). On reads, the controller can internally de-swizzle the data before performing the error correction operations using the swizzling map. | 06-23-2011 |
20110246712 | METHOD AND APPARATUS FOR INTERFACING WITH HETEROGENEOUS DUAL IN-LINE MEMORY MODULES - Described herein is a method and apparatus to interface a processor with a heterogeneous dual in-line memory module (DIMM). The method comprises determining an identity of a DIMM having data lanes; mapping the data lanes based on the determining of the identity of the DIMM; training input-output (I/O) transceivers in response to the mapping of the data lanes; and transferring data to and from the DIMM after training the I/O transceivers. | 10-06-2011 |
20110246713 | FAST EXIT FROM SELF-REFRESH STATE OF A MEMORY DEVICE - A system provides for a signal to indicate when a memory device exits from self-refresh. Thus, substantially at the same time (before or after) the memory device exits self-refresh, an indicator signal can be triggered to indicate normal operation or standard refresh operation and normal memory access of the memory device. A memory controller can access the indicator signal to determine whether the memory device is in self-refresh. Thus, the memory controller can more carefully manage the timing of sending a command to the memory device while reducing the delay time typically associated with detecting a self-refresh condition. | 10-06-2011 |
20110252193 | METHOD TO STAGGER SELF REFRESHES - A system, device, and method for designating a first rank among a plurality of memory ranks of a Memory Module as a primary rank and a second one or more ranks as secondary ranks, triggering, via hardware logic internal to the Memory Module coupled with the plurality of memory ranks, a refresh of the primary rank at a first time (e.g., Time | 10-13-2011 |
20110261636 | COMMON MEMORY DEVICE FOR VARIABLE DEVICE WIDTH AND SCALABLE PRE-FETCH AND PAGE SIZE - Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a ×4 mode, a ×8 mode, and a ×16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM. | 10-27-2011 |
20110316580 | METHOD AND APPARATUS FOR DYNAMIC MEMORY TERMINATION - Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level. | 12-29-2011 |
20110320867 | METHOD AND APPARATUS FOR TRAINING A MEMORY SIGNAL VIA AN ERROR SIGNAL OF A MEMORY - Described herein is a method and an apparatus for training a memory signal via an error signal of a memory. The method comprises transmitting from a memory controller a command-address (C/A) signal to a memory module; determining by the memory controller an error in the memory module via an error signal from an error pin of the memory module, the error associated with the C/A signal transmitted to the memory module; and modifying by the memory controller the C/A signal in response to determining an error in the memory module, wherein the error pin is a parity error pin of the memory module, and wherein the memory module comprises a Double Data Rate 4 (DDR4) interface. | 12-29-2011 |
20120075902 | IDENTIFYING AND ACCESSING INDIVIDUAL MEMORY DEVICES IN A MEMORY CHANNEL - In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register. | 03-29-2012 |
20120079182 | FAST EXIT FROM DRAM SELF-REFRESH - Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller. | 03-29-2012 |
20120079183 | REDUCED CURRENT REQUIREMENTS FOR DRAM SELF-REFRESH MODES - Embodiments of the invention describe systems, methods, and apparatuses to reduce the instantaneous power necessary to execute a DRAM device initiated self-refresh. Embodiments of the invention describe a DRAM device enabled to stagger self-refreshes between a plurality of banks. Staggering self-refreshes between banks reduces the current required for a DRAM self-refresh, thus reducing the amount of current required by the DRAM device. | 03-29-2012 |
20120124451 | OPTIMIZING THE SIZE OF MEMORY DEVICES USED FOR ERROR CORRECTION CODE STORAGE - Embodiments of the invention are generally directed to systems, methods, and apparatuses for optimizing the size of memory devices used for error correction code storage. An apparatus (such as a memory module) may include a number of memory devices to store data and a memory device to store error correction (ECC) bits. In some embodiments, the memory devices to store data may have a density of N and the memory device to store ECC bits has a density of ½ N. | 05-17-2012 |
20120131414 | RELIABILITY, AVAILABILITY, AND SERVICEABILITY SOLUTION FOR MEMORY TECHNOLOGY - Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed. | 05-24-2012 |
20120144106 | Memory Device Refresh Commands On the Fly - On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch from a currently-applied refresh rate to a different refresh rate. In response to the condition, the refresh rate is dynamically switched. The switching does not require a change of a mode register. Thus, a refresh rate for the memory device can be dynamically changed on the fly. | 06-07-2012 |
20120144264 | Memory Device On the Fly CRC Mode - On the fly enabling and disabling of error detection for memory access transactions on a transaction basis is provided. Dynamic enabling and disabling of error detection for memory access transactions can also be applied for multiple transactions. Control logic associated with the memory device determines whether to apply error detection, and selectively enables error detection in the memory access transaction. The selective enabling of error detection in a memory access transaction can apply to either reads or writes. | 06-07-2012 |
20120191907 | SYSTEMS, METHODS, AND APPARATUSES FOR IN-BAND DATA MASK BIT TRANSMISSION - Embodiments of the invention are generally directed to systems, methods, and apparatuses for in-band data mask bit transmission. In some embodiments, one or more data mask bits are integrated into a partial write frame and are transferred to a memory device via the data bus. Since the data mask bits are transferred via the data bus, the system does not need (costly) data mask pin(s). In some embodiments, a mechanism is provided to enable a memory device (e.g., a DRAM) to check for valid data mask bits before completing the partial write to the DRAM array. | 07-26-2012 |
20120314521 | MEMORY THROUGHPUT INCREASE VIA FINE GRANULARITY OF PRECHARGE MANAGEMENT - Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three separate precharge timings may be used, e.g., optimized per memory bank, per memory bank group, and/or per a memory device. Other embodiments are also disclosed and claimed. | 12-13-2012 |
20120331220 | FAST EXIT FROM DRAM SELF-REFRESH - Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller. | 12-27-2012 |
20130117641 | METHOD AND SYSTEM FOR ERROR MANAGEMENT IN A MEMORY DEVICE - A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command. | 05-09-2013 |
20130145197 | METHOD AND SYSTEM TO IMPROVE THE OPERATIONS OF A REGISTERED MEMORY MODULE - A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module. | 06-06-2013 |
20130185499 | FAST EXIT FROM SELF-REFRESH STATE OF A MEMORY DEVICE - A system provides for a signal to indicate when a memory device exits from self-refresh. Thus, substantially at the same time (before or after) the memory device exits self-refresh, an indicator signal can be triggered to indicate normal operation or standard refresh operation and normal memory access of the memory device. A memory controller can access the indicator signal to determine whether the memory device is in self-refresh. Thus, the memory controller can more carefully manage the timing of sending a command to the memory device while reducing the delay time typically associated with detecting a self-refresh condition. | 07-18-2013 |
20140006699 | FLEXIBLE COMMAND ADDRESSING FOR MEMORY | 01-02-2014 |
20140085995 | METHOD, APPARATUS AND SYSTEM FOR DETERMINING A COUNT OF ACCESSES TO A ROW OF MEMORY - Techniques and mechanisms for determining a count of accesses to a row of a memory device. In an embodiment, the memory device includes a counter comprising circuitry to increment a value of the count in response to detecting a command to activate the row. Circuitry of counter may further set a value of the count to a baseline value in response to detecting a command to refresh the row. In another embodiment, the memory device includes evaluation logic to compare a value of the count to a threshold value. A signal is generated based on the comparison to indicate whether a row hammer event for the row is indicated. | 03-27-2014 |
20140089573 | METHOD FOR ACCESSING MEMORY DEVICES PRIOR TO BUS TRAINING - Embodiments of the invention describe apparatuses, systems and methods for enabling memory device access prior to bus training, thereby enabling firmware image storage in non-flash nonvolatile memory, such as DDR DRAM. The increasing size of firmware images, such as BIOS, MRC, and ME firmware, makes current non-volatile storage solutions, such as SPI flash memory, impractical; executing BIOS code in flash is slow, and having a separate non-volatile memory device increases device costs. Furthermore, solutions such as Cache-as-RAM, which are utilized for running the pre-memory BIOS code, are limited by the cache size that is not scalable to the increasing complexity of BIOS code. | 03-27-2014 |
20140089576 | METHOD, APPARATUS AND SYSTEM FOR PROVIDING A MEMORY REFRESH - A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows. | 03-27-2014 |
20140095780 | DISTRIBUTED ROW HAMMER TRACKING - A memory controller issues a targeted refresh command in response to detection by a distributed detector. A memory device includes detection logic that monitors for a row hammer event, which is a threshold number of accesses to a row within a time threshold that can cause data corruption to a physically adjacent row (a “victim” row). The memory device sends an indication of the row hammer event to the memory controller. In response to the row hammer event indication, the memory controller sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row. | 04-03-2014 |
20140156923 | ROW HAMMER MONITORING BASED ON STORED ROW HAMMER THRESHOLD VALUE - Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row. | 06-05-2014 |
20140177370 | METHOD, APPARATUS AND SYSTEM FOR RESPONDING TO A ROW HAMMER EVENT - Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh. | 06-26-2014 |
20140181333 | VARIABLE-WIDTH COMMAND/ADDRESS BUS - Embodiments of the invention relate to a variable-width command/address bus (CA bus). In one embodiment, a memory controller includes first logic to determine whether a memory device is in a first mode or a second mode. The memory controller includes second logic to transmit a command to the memory device with a command/address bus having a first width over a first number of clock edges when the memory device is in the first mode, and with the command/address bus having a second width over a second number of clock edges when the memory device is in the second mode. | 06-26-2014 |
20140181390 | METHOD, APPARATUS AND SYSTEM FOR EXCHANGING COMMUNICATIONS VIA A COMMAND/ADDRESS BUS - Techniques and mechanisms for exchanging information from a memory controller to a memory device via a command/address bus. In an embodiment, the memory device samples a first portion of a command during a first sample period and samples a second portion of the command during a second sample period, the first portion and second portion exchanged via the command/address bus. The first sample period and the second sample period are concurrent with, respectively, a first transition of a clock signal and a second transition of the clock signal. In another embodiment, a mode of the memory device determines a relationship between the first transition and the second transition. | 06-26-2014 |
20140184523 | LOW SWING VOLTAGE MODE DRIVER - An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low. | 07-03-2014 |
20140241094 | MEMORY DEVICE REFRESH COMMANDS ON THE FLY - On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch from a currently-applied refresh rate to a different refresh rate. In response to the condition, the refresh rate is dynamically switched. The switching does not require a change of a mode register. Thus, a refresh rate for the memory device can be dynamically changed on the fly. | 08-28-2014 |
20140244922 | MULTI-PURPOSE REGISTER PROGRAMMING VIA PER DRAM ADDRESSABILITY MODE - Embodiments of an apparatus, system and method for using Per DRAM Addressability (PDA) to program Multi-Purpose Registers (MPRs) of a dynamic random access memory (DRAM) device are described herein. Embodiments of the invention allow unique 32 bit patterns to be stored for each DRAM device on a rank, thereby enabling data bus training to be done in parallel. Furthermore, embodiments of the invention provide 32 bits of storage per DRAM device on a rank for the system BIOS for storing codes such as MR values, or for any other purpose (e.g., temporary scratch storage to be used by BIOS processes). | 08-28-2014 |
20140372815 | APPARATUS AND METHOD TO REDUCE POWER DELIVERY NOISE FOR PARTIAL WRITES - Apparatus, systems, and methods to reduce power delivery noise for partial writes are described. In one embodiment, an apparatus comprises a processor and a memory control logic to insert one or more dummy unit intervals into data in a write operation when a number of state transitions between adjacent unit intervals exceeds a threshold. Other embodiments are also disclosed and claimed. | 12-18-2014 |
20140372816 | ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE - A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device. | 12-18-2014 |
20150067437 | APPARATUS, METHOD AND SYSTEM FOR REPORTING DYNAMIC RANDOM ACCESS MEMORY ERROR INFORMATION - Techniques and mechanisms for providing state information describing one or more data errors detected locally at a memory device. In an embodiment, the memory device includes a memory core and error detection circuit logic configured to detect for errors of data stored by the memory core. A die of the memory device includes both the memory core and the error detection circuitry. In another embodiment, state information is stored in a mode register of the memory device in response to the error detection logic detecting an occurrence of a data error. The state information is available for access by a memory controller or other agent which is external to the memory device. | 03-05-2015 |
20150089111 | ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE - A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device. | 03-26-2015 |
20150089127 | MEMORY BROADCAST COMMAND - Apparatus, systems, and methods to broadcast a memory command are described. In one embodiment, a memory controller comprising logic to insert a first predetermined value into an all ranks parameter in a memory command, and transmit the memory command to a memory device. Other embodiments are also disclosed and claimed. | 03-26-2015 |
20150089183 | MAPPING A PHYSICAL ADDRESS DIFFERENTLY TO DIFFERENT MEMORY DEVICES IN A GROUP - A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a memory access command to each memory device of the group. Thus, each physical address sent by an associated memory controller uniquely accesses a different row of each memory device, instead of being mapped to the same or corresponding row of each memory device. | 03-26-2015 |