Patent application number | Description | Published |
20080288238 | Computing System with Guest Code Support of Transactional Memory - A data structure of readily accessible units of memory is provided as computer useable media having computer readable program code logic providing information tables and a software emulation program to enable hardware to run new software that uses transactional memory and a bit associated with a transaction for executing transactional memory constructs. The data structure with Guest PTRAN bit is used in emulation of software written for a given computer on a different computer which executes a different set of instructions. The emulating instructions are used to provide transactional memory instructions on a computer which does not support those instructions natively | 11-20-2008 |
20080288726 | Transactional Memory System with Fast Processing of Common Conflicts - A computing system processes memory transactions for parallel processing of multiple threads of execution by support of which an application need not be aware. The computing system transactional memory support provides a Transaction Table in memory and performs fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. A transaction program employs a plurality of Set Associative Transaction Tables, one for each microprocessor, and Load and Store Summary Tables in memory for fast processing of common conflict. | 11-20-2008 |
20080288727 | Computing System with Optimized Support for Transactional Memory - A computing system processes memory transactions for parallel processing of multiple threads of execution by support of which an application need not be aware. The computing system transactional memory support provides a Transaction Table in memory and a method of fast detection, of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. | 11-20-2008 |
20080288730 | Transactional Memory System Which Employs Thread Assists Using Address History Tables - A computing system uses specialized “Set Associative Transaction Tables” and additional “Summary Transaction Tables” to speed the processing of common transactional memory conflict cases and those which employ assist threads using an Address History Table and processes memory transactions with a Transaction Table in memory for parallel processing of multiple threads of execution by support of which an application need not be aware. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. | 11-20-2008 |
20080288819 | Computing System with Transactional Memory Using Millicode Assists - A computing system processes memory transactions for parallel processing of multiple threads of execution with millicode assists. The computing system transactional memory support provides a Transaction Table in memory and a method of fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. Program millicode provides transactional memory functions including creating and updating transaction tables, committing transactions and controlling the rollback of transactions which fail. | 11-20-2008 |
20090113443 | Transactional Memory Computing System with Support for Chained Transactions - A computing system processes memory transactions for parallel processing of multiple threads of execution provides execution of multiple atomic instruction groups (AIGs) on multiple systems to support a single large transaction that requires operations on multiple threads of execution and/or on multiple systems connected by a network. The support provides a Transaction Table in memory and fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. | 04-30-2009 |
20090217018 | METHODS, APPARATUS AND ARTICLES OF MANUFACTURE FOR REGAINING MEMORY CONSISTENCY AFTER A TRAP VIA TRANSACTIONAL MEMORY - Embodiments of the invention provide a method for regaining memory consistency after a trap via transactional memory. Transactional memory and a transactional memory log are used to undo changes made to memory from a transaction start point up to the point of a trap event. After the trap event is processed, and the changes are rolled back, the program can resume execution at the beginning of the transaction. | 08-27-2009 |
20090217104 | METHOD AND APPARATUS FOR DIAGNOSTIC RECORDING USING TRANSACTIONAL MEMORY | 08-27-2009 |
20100174840 | PRIORITIZATION FOR CONFLICT ARBITRATION IN TRANSACTIONAL MEMORY MANAGEMENT - Embodiments of the present invention provide a method, system and computer program product for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management. In an embodiment of the invention, a method for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management can include setting different hardware registers with different priority values for correspondingly different transactions in a transactional memory system configured for transactional memory management according to respective priority values specified by priority assignment logic in external software support for the system. The method also can include detecting a conflict amongst the transactions in the system. Finally, the method can include applying conflict arbitration within the system based upon the priority values specified by the priority assignment logic in the external software support for the system. | 07-08-2010 |
20100217868 | MICROPROCESSOR WITH SOFTWARE CONTROL OVER ALLOCATION OF SHARED RESOURCES AMONG MULTIPLE VIRTUAL SERVERS - A system, method and computer program product for controlling the allocation of shared resources. The system includes a next request priority module connected to a shared resource and to a plurality of requesters identified by requester identifiers. The next request priority module includes a pending request mechanism that prioritizes pending requests for the shared resource, a logging mechanism logging requester identifiers associated with previous grants to the shared resource, and next request priority logic. The next request priority logic accesses the next pending request to determine if it should be granted priority to the shared resource. The determining is responsive to logged requester identifiers and to the next requester identifier. Priority is granted to the shared resource to the next pending request in response to determining that the next pending request should be granted priority to the shared resource. The next requester identifier is logged in response to the granting. | 08-26-2010 |
20110119452 | Hybrid Transactional Memory System (HybridTM) and Method - A computer processing system having memory and processing facilities for processing data with a computer program is a Hybrid Transactional Memory multiprocessor system with modules | 05-19-2011 |
20110119508 | Power Efficient Stack of Multicore Microprocessors - A computing system has a stack of microprocessor chips that are designed to work together in a multiprocessor system. The chips are interconnected with 3D through vias, or alternatively by compatible package carriers having the interconnections, while logically the chips in the stack are interconnected via specialized cache coherent interconnections. All of the chips in the stack use the same logical chip design, even though they can be easily personalized by setting specialized latches on the chips. One or more of the individual microprocessor chips utilized in the stack are implemented in a silicon process that is optimized for high performance while others are implemented in a silicon process that is optimized for power consumption i.e. for the best performance per Watt of electrical power consumed. The hypervisor or operating system controls the utilization of individual chips of a stack. | 05-19-2011 |
20110239015 | Allocating Computing System Power Levels Responsive to Service Level Agreements - A computer program product for initiating a task in a computer system including executing a method that includes receiving a task and a status of the task relative to a target service level. A current power state of the processor is determined. Execution of the task is initiated on the processor in response to the status indicating that the task is meeting the target service level and to the current power state being a low power state. It is determined if the processor can be moved into a high power state, the determining performed if the task is not meeting the target service level and the current power state is the low power state. If the processor can be moved into the high power state then the processor is moved into the high power state and execution of the task is initiated on the processor. | 09-29-2011 |
20110239016 | Power Management in a Multi-Processor Computer System - Power management in a multi-processor computer system, including a computer program product for facilitating receiving a task for execution in a high power state, and determining a current power state of a processor in a multi-processor system, the system having a specified power limit. The task is dispatched to the processor if the current power state of the processor is the high power state. If the processor is not in the high power state, then it is determined if moving the processor into the high power state will cause the multi-processor system to exceed the specified power limit. The processor is moved into the high power state in response to determining that moving the processor into the high power state will not cause the multi-processor system to exceed the specified power limit. The task is dispatched to the processor in response to moving the processor into the high power state. | 09-29-2011 |
20110271079 | MULTIPLE-CORE PROCESSOR SUPPORTING MULTIPLE INSTRUCTION SET ARCHITECTURES - A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. | 11-03-2011 |
20120271952 | MICROPROCESSOR WITH SOFTWARE CONTROL OVER ALLOCATION OF SHARED RESOURCES AMONG MULTIPLE VIRTUAL SERVERS - A method for controlling the allocation of shared resources that includes receiving, from a requestor executing on a processor, a request to access a shared resource. The receiving is at a next request priority module connected to the processor and the shared resource. It is determined if any of a specified number of most recent priority grants to the shared resource were to the requestor. The request is granted if none of the specified number of most recent priority grants to the shared resource were to the requestor. If any of the specified number of most recent priority grants to the shared resource were to the requestor, then it is determined if one or more other requests for the shared resource are pending. It is determined if one of the other requests should be granted priority to the shared resource if other requests for the shared resource are pending. | 10-25-2012 |
20130042094 | COMPUTING SYSTEM WITH TRANSACTIONAL MEMORY USING MILLICODE ASSISTS - A computing system processes memory transactions for parallel processing of multiple threads of execution with millicode assists. The computing system transactional memory support provides a Transaction Table in memory and a method of fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. Program millicode provides transactional memory functions including creating and updating transaction tables, committing transactions and controlling the rollback of transactions which fail. | 02-14-2013 |
20130297967 | HYBRID TRANSACTIONAL MEMORY (HYBRID TM) - Embodiments related to a hardware transactional memory (HTM). An aspect includes setting a mode register of a processor core of a computer to indicate a HTM mode. Another aspect includes executing a plurality of transactions by the processor core in the HTM mode based on the mode register. Another aspect includes determining whether a first transaction of the plurality of transactions exceeds a failure limit of the processor core in the HTM mode. Yet another aspect includes, based on determining that the first transaction exceeds the failure limit of the processor core in the HTM mode, transitioning the processor to an assisted transaction mode by setting the mode register of the processor core to indicate the assisted transaction mode. | 11-07-2013 |
20140325098 | HIGH THROUGHPUT HARDWARE ACCELERATION USING PRE-STAGING BUFFERS - Embodiments relate to providing high throughput hardware acceleration. Aspects include initializing an accelerator control queue (ACQ) configured to provide location information on a plurality of pages of data identified as accelerator data. An originating location of each page of requested target data is determined. The originating location includes one of system memory and disk storage. Based on determining that the originating location is system memory, an entry is created in the ACQ mapping to a system memory source address for the target data. Based on determining that the originating location is disk storage, an entry is created in the ACQ mapping to a special pre-stage buffer source address of a special pre-stage buffer for the target data. Each page of the plurality of pages of target data is accessed by the accelerator from respective locations in said memory or said special pre-stage buffer, based on respective entries of the ACQ. | 10-30-2014 |