Patent application number | Description | Published |
20100127352 | SELF-ALIGNED BIPOLAR TRANSISTOR STRUCTURE - A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region. | 05-27-2010 |
20110042778 | SEMICONDUCTOR DEVICE HAVING LOCALIZED INSULATED BLOCK IN BULK SUBSTRATE AND RELATED METHOD - One or more trenches can be formed around a first portion of a semiconductor substrate, and an insulating layer can be formed under the first portion of the semiconductor substrate. The one or more trenches and the insulating layer electrically isolate the first portion of the substrate from a second portion of the substrate. The insulating layer can be formed by forming a buried layer in the substrate, such as a silicon germanium layer in a silicon substrate. One or more first trenches through the substrate to the buried layer can be formed, and open spaces can be formed in the buried layer (such as by using an etch selective to silicon germanium over silicon). The one or more first trenches and the open spaces can optionally be filled with insulative material(s). One or more second trenches can be formed and filled to isolate the first portion of the substrate. | 02-24-2011 |
20110140118 | Backside stress compensation for gallium nitride or other nitride-based semiconductor devices - A method includes forming a stress compensation layer over a first side of a semiconductor substrate and forming a Group III-nitride layer over a second side of the substrate. Stress created on the substrate by the Group III-nitride layer is at least partially reduced by stress created on the substrate by the stress compensation layer. Forming the stress compensation layer could include forming a stress compensation layer from amorphous or microcrystalline material. Also, the method could include crystallizing the amorphous or microcrystalline material during subsequent formation of one or more layers over the second side of the substrate. Crystallizing the amorphous or microcrystalline material could occur during subsequent formation of the Group III-nitride layer and/or during an annealing process. The amorphous or microcrystalline material could create no or a smaller amount of stress on the substrate, and the crystallized material could create a larger amount of stress on the substrate. | 06-16-2011 |
20110140173 | Low OHMIC contacts containing germanium for gallium nitride or other nitride-based power devices - An apparatus includes a substrate, a Group III-nitride layer over the substrate, and an electrical contact over the Group III-nitride layer. The electrical contact includes a stack having multiple layers of conductive material, and at least one of the layers in the stack includes germanium. The layers in the stack may include a contact layer, where the contact layer includes aluminum copper. The stack could include a titanium or titanium alloy layer, an aluminum or aluminum alloy layer, and a germanium or germanium alloy layer. At least one of the layers in the stack could include an aluminum or titanium alloy having a germanium content between about 1% and about 5%. | 06-16-2011 |
20110140242 | Stress compensation for large area gallium nitride or other nitride-based structures on semiconductor substrates - A method includes forming a stress compensating stack over a substrate, where the stress compensating stack has compressive stress on the substrate. The method also includes forming one or more Group III-nitride islands over the substrate, where the one or more Group III-nitride islands have tensile stress on the substrate. The method further includes at least partially counteracting the tensile stress from the one or more Group III-nitride islands using the compressive stress from the stress compensating stack. Forming the stress compensating stack could include forming one or more oxide layers and one or more nitride layers over the substrate. The one or more oxide layers can have compressive stress, the one or more nitride layers can have tensile stress, and the oxide and nitride layers could collectively have compressive stress. Thicknesses of the oxide and nitride layers can be selected to provide the desired amount of stress compensation. | 06-16-2011 |
20110148403 | Magneto-electric sensor with injected up-conversion or down-conversion - A method includes generating an electrical signal representing a magnetic field using a magnetic field sensor having alternating layers of magneto-strictive material and piezo-electric material. The method also includes performing up-conversion or down-conversion so that the electrical signal representing the magnetic field has a higher or lower frequency than a frequency of the magnetic field. The up-conversion or down-conversion is performed before the magnetic field is converted into the electrical signal. The up-conversion or down-conversion could be performed by repeatedly sensitizing and desensitizing the magnetic field sensor. This could be done using a permanent magnet and an electromagnet, an electromagnet without a permanent magnet, or a movable permanent magnet. The up-conversion or down-conversion could also be performed by chopping the magnetic field. The chopping could involve intermittently shielding the magnetic field sensor from the magnetic field or moving the magnetic field sensor with respect to the magnetic field. | 06-23-2011 |
20110152703 | Heart monitoring system or other system for measuring magnetic fields - A system includes at least one first magnetic field sensor configured to measure first and second magnetic fields. The system also includes at least one second magnetic field sensor configured to measure the second magnetic field substantially without measuring the first magnetic field. The system further includes processing circuitry configured to perform signal cancellation to generate measurements of the first magnetic field and to generate an output based on the measurements of the first magnetic field. The sensors could represent magneto-electric sensors. The magneto-electric sensors could be configured to up-convert electrical signals associated with the first and/or second magnetic fields to a higher frequency. The processing circuitry could be configured to identify one or more problems associated with a patient's heart. | 06-23-2011 |
20110180848 | HIGH PERFORMANCE SiGe:C HBT WITH PHOSPHOROUS ATOMIC LAYER DOPING - A base structure for high performance Silicon Germanium:Carbon (SiGe:C) based heterojunction bipolar transistors (HBTs) with phosphorus atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas (in ambient temperature approximately equal to 500 degrees Celsius) and provides an additional SiGe:C spacer layer. During the ALD process, the percent concentrations of Germanium (Ge) and carbon (C) are substantially matched and phosphorus is a preferred dopant. The improved SiGe:C HBT is less sensitive to process temperature and exposure times, and exhibits lower dopant segregation and sharper base profiles. | 07-28-2011 |
20110180854 | Normally-off gallium nitride-based semiconductor devices - A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride. | 07-28-2011 |
20110186855 | Enhancement-Mode GaN MOSFET with Low Leakage Current and Improved Reliability - An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO | 08-04-2011 |
20120056244 | Growth of multi-layer group III-nitride buffers on large-area silicon Substrates and other substrates - A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer. | 03-08-2012 |
20120067396 | Hydrophobic Solar Concentrator and Method of Using and Forming the Hydrophobic Solar Concentrator - A solar concentrator is implemented with a plate structure that has a surface and one or more hydrophobic regions on the surface of the plate structure. The plate structure is transparent to visible light. A fluid is sprayed onto the surface of the plate structure where the fluid forms droplets on the hydrophobic regions. The droplets capture substantially all angles of incident solar radiation and deliver concentrated solar radiation to a corresponding number of solar cells. | 03-22-2012 |
20120119262 | SiGe Heterojunction Bipolar Transistor and Method of Forming a SiGe Heterojunction Bipolar Transistor - A SiGe heterojunction bipolar transistor is fabricated by etching an epitaxially-formed structure to form a mesa that has a collector region, a cap region, and a notched SiGe base region that lies in between. A protective plug is formed in the notch of the SiGe base region so that thick non-conductive regions can be formed on the sides of the collector region and the cap region. Once the non-conductive regions have been formed, the protective plug is removed. An extrinsic base is then formed to lie in the notch and touch the base region, followed by the formation of isolation regions and an emitter region. | 05-17-2012 |
20140042458 | GROWTH OF MULTI-LAYER GROUP III-NITRIDE BUFFERS ON LARGE-AREA SILICON SUBSTRATES AND OTHER SUBSTRATES - A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer. | 02-13-2014 |
20140051226 | GROWTH OF MULTI-LAYER GROUP III-NITRIDE BUFFERS ON LARGE-AREA SILICON SUBSTRATES AND OTHER SUBSTRATES - A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer. | 02-20-2014 |
20140094005 | Enhancement-Mode GaN MOSFET with Low Leakage Current and Improved Reliability - An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO | 04-03-2014 |
20140295651 | BACKSIDE STRESS COMPENSATION FOR GALLIUM NITRIDE OR OTHER NITRIDE-BASED SEMICONDUCTOR DEVICES - A method includes forming a stress compensation layer over a first side of a semiconductor substrate and forming a Group III-nitride layer over a second side of the substrate. Stress created on the substrate by the Group III-nitride layer is at least partially reduced by stress created on the substrate by the stress compensation layer. Forming the stress compensation layer could include forming a stress compensation layer from amorphous or microcrystalline material. Also, the method could include crystallizing the amorphous or microcrystalline material during subsequent formation of one or more layers over the second side of the substrate. Crystallizing the amorphous or microcrystalline material could occur during subsequent formation of the Group III-nitride layer and/or during an annealing process. The amorphous or microcrystalline material could create no or a smaller amount of stress on the substrate, and the crystallized material could create a larger amount of stress on the substrate. | 10-02-2014 |
20140312358 | NORMALLY-OFF GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICES - A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride. | 10-23-2014 |
Patent application number | Description | Published |
20130140605 | GaN high voltage HFET with passivation plus gate dielectric multilayer structure - A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device. | 06-06-2013 |
20130146863 | HIGH QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON - Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline Al | 06-13-2013 |
20130157440 | Composite wafer for fabrication of semiconductor devices - A composite wafer includes a first substrate having a first vertical thickness and a top surface, the top surface being prepared in a state for subsequent semiconductor material epitaxial deposition. A carrier substrate is disposed beneath the first substrate. The carrier substrate has a second vertical thickness greater than the first vertical thickness. An interlayer bonds the first substrate to the carrier substrate. | 06-20-2013 |
20130302972 | HIGH QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON - Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline Al | 11-14-2013 |
20140077266 | Heterostructure Transistor with Multiple Gate Dielectric Layers - A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A first gate dielectric layer is disposed on the second active layer. A second gate dielectric layer is disposed on the first gate dielectric layer. A passivation layer is disposed over the second gate dielectric layer. A gate extends through the passivation layer to the second gate dielectric layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts. | 03-20-2014 |
20140124789 | GaN High Voltage HFET with Passivation Plus Gate Dielectric Multilayer Structure - A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device. | 05-08-2014 |
20140239309 | Heterostructure Power Transistor With AlSiN Passivation Layer - A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts. | 08-28-2014 |
20140374768 | HIGH QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON - Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline Al | 12-25-2014 |
20150076510 | Heterostructure Power Transistor with AlSiN Passivation Layer - A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts. | 03-19-2015 |
20150364552 | HIGH-QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON - A GaN HFET includes a silicon substrate with an Al | 12-17-2015 |
Patent application number | Description | Published |
20080287700 | Method for Preparing an Omega-Haloalkyl Dialkylhalosilane - The present invention relates to a method for preparing an omega-haloalkyl dialkylhalosilane by means of a hydrosilylation reaction in the presence of a catalytically effective amount of a hydrosilylation catalyst containing a platinum group metal. The catalytic metal is recovered by (i) subjecting the distillation residue to controlled hydrolysis to release the gaseous H-Hal haloacid, and providing an aqueous medium containing the catalytic metal with a low hydrolysable halide content Si-Hal=2%, expressed by weight of Hal, then (2i) recovering the platinum group catalytic metal from said aqueous medium by means of one of the conventional techniques specific to catalyst manufacturers that do not use a solid adsorbent and operate in ordinary facilities that do not have to be acid-resistant. | 11-20-2008 |
20090093605 | PROCESS FOR PREPARING A SILICONE RESIN - The invention relates to, and the general field of the invention is that of, the synthesis of silicone resins, more particularly the synthesis of silicone resins of type MQ. The process relates to the preparation of MQ silicone resins and permits better control of the operating conditions in the step of the polymerization of a sodium silicate (B) in aqueous medium in the presence of an acid (C) to form a silica hydrosol (polysilicic acid). In the course of the polycondensation step the reactants, a sodium silicate and an acid, are mixed, preferably in continuous fashion, dynamically to form a mixture (3), by means of at least one intensive mixing tool (M) producing a power ε per unit volume of more than 10 kW/m | 04-09-2009 |
20100056745 | METHOD FOR PRODUCING ORGANOALKOXYDIALKYLSILANE - The invention relates to producing an organo alcoxydialkylsilane by a method which consists in introducing by pouring an alcanol in a dialkylhalogenosilane omega-halogenalkyl+an organic solvent (s) phase mixture and in removing a halogen acid formed by entrainment with the aid of said organic solvent(s) phase and is characterised, in particular (i) by selecting a particular phase of solvent(s), for example based on cyclohexane, (2i) by carrying out an alcanol introduction mode which makes it possible to control the drawing off the halogen acid formed during reaction and by (3i) controlling the halogen acid quantity in a reaction medium. The thus obtained dialkylhalogenosilane omega-halogenalkyl is usable, in particular as an initial product for preparing organosilisic sulphur-containing compounds of general formula (IV) by a sulfidising reaction carried out on a alkali metal polysulfur. | 03-04-2010 |
20110020249 | POLYORGANOSILOXANE WITH A PIPERIDINE FUNCTION, DEVOID OF TOXICITY UPON CONTACT WITH THE SKIN, AND USE THEREOF IN COSMETIC COMPOSITIONS - The invention relates to polyorganosiloxanes containing, per molecule, at least one siloxyl unit substituted with at least one group having one or more sterically hindered piperidinyl functional groups, devoid of toxicity upon contact with the skin. The invention also relates to an improved cosmetic composition comprising the polyorganosiloxanes according to the invention and the use of these compositions for the treatment of keratin materials, in particular the skin and the hair. | 01-27-2011 |