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Huilong Zhu
POUGHKEEPSIE, NY US
1. 20090283836 CMOS STRUCTURE INCLUDING PROTECTIVE SPACERS AND METHOD OF FORMING THEREOF 11-19-20092. 20090280626 FINFET STRUCTURE WITH MULTIPLY STRESSED GATE ELECTRODE 11-12-2009
3. 20090273040 HIGH PERFORMANCE SCHOTTKY-BARRIER-SOURCE ASYMMETRIC MOSFETS 11-05-2009
4. 20090256594 NANOELECTROMECHANICAL DIGITAL INVERTER - digital inverter formed by three carbon nanotubes extending vertically from a substrate one CNT functioning as 10-15-2009
5. 20090256213 STRUCTURE AND METHOD FOR MANUFACTURING DEVICE WITH A V-SHAPE CHANNEL NMOSFET 10-15-2009
6. 20090256205 2-T SRAM CELL STRUCTURE AND METHOD - The present invention in one embodiment provides a memory device including a substrate including at least one 10-15-2009
7. 20090242942 ASYMMETRIC SOURCE AND DRAIN FIELD EFFECT STRUCTURE AND METHOD 10-01-2009
8. 20090242941 STRUCTURE AND METHOD FOR MANUFACTURING DEVICE WITH A V-SHAPE CHANNEL NMOSFET 10-01-2009
9. 20090236676 STRUCTURE AND METHOD TO MAKE HIGH PERFORMANCE MOSFET WITH FULLY SILICIDED GATE 09-24-2009
10. 20090230455 STRUCTURE AND METHOD FOR MANUFACTURING MEMORY 09-17-2009
11. 20090230438 SELECTIVE NITRIDATION OF TRENCH ISOLATION SIDEWALL 09-17-2009
12. 20090218631 SRAM CELL HAVING ASYMMETRIC PASS GATES - Conductive stripes laterally abutting the dielectric lines are formed over a thin semiconductor layer on a gate 09-03-2009
13. 20090218627 FIELD EFFECT DEVICE STRUCTURE INCLUDING SELF-ALIGNED SPACER SHAPED CONTACT 09-03-2009
14. 20090206441 METHOD OF FORMING COPLANAR ACTIVE AND ISOLATION REGIONS AND STRUCTURES THEREOF 08-20-2009
15. 20090194819 CMOS STRUCTURES AND METHODS USING SELF-ALIGNED DUAL STRESSED LAYERS 08-06-2009
16. 20090184378 STRUCTURE AND METHOD TO FABRICATE MOSFET WITH SHORT GATE 07-23-2009
17. 20090184369 FINFET DEVICES AND METHODS FOR MANUFACTURING THE SAME 07-23-2009
18. 20090174006 STRUCTURE AND METHOD OF CREATING ENTIRELY SELF-ALIGNED METALLIC CONTACTS 07-09-2009
19. 20090149010 STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C 06-11-2009
20. 20090142894 METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE 06-04-2009
21. 20090140350 LITHOGRAPHY FOR PRINTING CONSTANT LINE WIDTH FEATURES 06-04-2009
22. 20090140345 SEMICONDUCTOR STRUCTURE INCLUDING SELF-ALIGNED DEPOSITED GATE DIELECTRIC 06-04-2009
23. 20090127626 STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION 05-21-2009
24. 20090108378 STRUCTURE AND METHOD FOR FABRICATING SELF-ALIGNED METAL CONTACTS 04-30-2009
25. 20090108351 FINFET MEMORY DEVICE WITH DUAL SEPARATE GATES AND METHOD OF OPERATION 04-30-2009
26. 20090108324 SEMICONDUCTOR FIN BASED NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATION THEREOF 04-30-2009
27. 20090096003 SEMICONDUCTOR CELL STRUCTURE INCLUDING BURIED CAPACITOR AND METHOD FOR FABRICATION THEREOF 04-16-2009
28. 20090090979 HIGH PERFORMANCE MOSFET - semiconductor structure which exhibits high device performance and improved short channel effects is provided 04-09-2009
29. 20090090938 CHANNEL STRESS ENGINEERING USING LOCALIZED ION IMPLANTATION INDUCED GATE ELECTRODE VOLUMETRIC CHANGE 04-09-2009
30. 20090079026 STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES 03-26-2009
31. 20090073758 SRAM CELLS WITH ASYMMETRIC FLOATING-BODY PASS-GATE TRANSISTORS 03-19-2009
32. 20090072400 CONTACT FORMING IN TWO PORTIONS AND CONTACT SO FORMED 03-19-2009
33. 20090065872 FULL SILICIDE GATE FOR CMOS - method is provided for fabricating an n-type field effect transistor and a p-type field effect transistor in which the 03-12-2009
34. 20090057765 FINFET STRUCTURE USING DIFFERING GATE DIELECTRIC MATERIALS AND GATE ELECTRODE MATERIALS 03-05-2009
35. 20090050942 SELF-ALIGNED SUPER STRESSED PFET - The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor 02-26-2009
36. 20090032889 FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE 02-05-2009
37. 20090032859 FINFET FLASH MEMORY DEVICE WITH AN EXTENDED FLOATING BACK GATE 02-05-2009
38. 20090032845 SOI FIELD EFFECT TRANSISTOR HAVING ASYMMETRIC JUNCTION LEAKAGE 02-05-2009
39. 20090017572 NANOELECTROMECHANICAL TRANSISTORS AND METHODS OF FORMING SAME 01-15-2009
40. 20090014803 NANOELECTROMECHANICAL TRANSISTORS AND METHODS OF FORMING SAME 01-15-2009
41. 20090014798 FINFET SRAM WITH ASYMMETRIC GATE AND METHOD OF MANUFACTURE THEREOF 01-15-2009
42. 20090014794 MOSFET WITH LATERALLY GRADED CHANNEL REGION AND METHOD FOR MANUFACTURING SAME 01-15-2009
43. 20090008705 BODY-CONTACTED FINFET - silicon containing fin is formed on a semiconductor substrate 01-08-2009
44. 20090001429 HYBRID STRAINED ORIENTATED SUBSTRATES AND DEVICES 01-01-2009
45. 20080311708 HYBRID STRAINED ORIENTATED SUBSTRATES AND DEVICES 12-18-2008
46. 20080310220 3-D SRAM ARRAY TO IMPROVE STABILITY AND PERFORMANCE 12-18-2008
47. 20080310207 3-D SRAM ARRAY TO IMPROVE STABILITY AND PERFORMANCE 12-18-2008
48. 20080299732 METHOD FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS 12-04-2008
49. 20080296648 FIN MEMORY STRUCTURE AND METHOD FOR FABRICATION THEREOF 12-04-2008
50. 20080296634 STRUCTURE AND METHOD FOR MANUFACTURING STRAINED SILICON DIRECTLY-ON-INSULATOR SUBSTRATE WITH HYBRID CRYSTALLINE ORIENTATION AND DIFFERENT STRESS LEVELS 12-04-2008
51. 20080286916 METHODS OF STRESSING TRANSISTOR CHANNEL WITH REPLACED GATE 11-20-2008
52. 20080286909 SIDEWALL SEMICONDUCTOR TRANSISTORS - novel transistor structure and method for fabricating the same 11-20-2008
53. 20080283934 SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT AND RELATED METHOD 11-20-2008
54. 20080251856 FORMING SILICIDED GATE AND CONTACTS FROM POLYSILICON GERMANIUM AND STRUCTURE FORMED 10-16-2008
55. 20080246112 SEMICONDUCTOR STRUCTURE INCLUDING LAMINATED ISOLATION REGION 10-09-2008
56. 20080246041 METHOD OF FABRICATING SOI nMOSFET AND THE STRUCTURE THEREOF 10-09-2008
57. 20080246032 TEST STRUCTURE FOR DETECTING VIA CONTACT SHORTING IN SHALLOW TRENCH ISOLATION REGIONS 10-09-2008
58. 20080242069 HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS 10-02-2008
59. 20080237749 CMOS GATE CONDUCTOR HAVING CROSS-DIFFUSION BARRIER 10-02-2008
60. 20080237733 STRUCTURE AND METHOD TO ENHANCE CHANNEL STRESS BY USING OPTIMIZED STI STRESS AND NITRIDE CAPPING LAYER STRESS 10-02-2008
61. 20080237720 HIGH MOBILITY CMOS CIRCUITS - Semiconductor structure formed on a substrate and process of forming the semiconductor 10-02-2008
62. 20080224258 SEMICONDUCTOR STRUCTUE WITH MULTIPLE FINS HAVING DIFFERENT CHANNEL REGION HEIGHTS AND METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE 09-18-2008
63. 20080224231 TRANSISTORS HAVING V-SHAPE SOURCE/DRAIN METAL CONTACTS 09-18-2008
64. 20080224216 STRAINED HOT (HYBRID OREINTATION TECHNOLOGY) MOSFETs 09-18-2008
65. 20080220581 OPTO-THERMAL ANNEALING METHODS FOR FORMING METAL GATE AND FULLY SILICIDED GATE-FIELD EFFECT TRANSISTORS 09-11-2008
66. 20080217696 METHOD AND STRUCTURE FOR CONTROLLING STRESS IN A TRANSISTOR CHANNEL 09-11-2008
67. 20080204200 Systems and methods of locating raido frequency identification tags by radio frequencey technology 08-28-2008