Patent application number | Description | Published |
20100128376 | MAGNETIC DISK DRIVE HAVING ASSISTED RECORDING AND METHODS OF RECORDING DATA THERETO - In one embodiment, a magnetic disk drive includes a magnetic disk, a head slider for flying above the spinning magnetic disk, a pattern analyzer for analyzing a data pattern of data to be recorded on the magnetic disk to determine a recording current reversal timing and a recording assistance area in accordance with the analysis so that the rear end of the determined recording assistance area is shifted forward if the determined recording current reversal timing is earlier than a criterion, or the rear end of the determined recording assistance area is shifted backward if the determined recording current reversal timing is later than the criterion, a recording assistance element on the slider for forming the determined recording assistance area on the magnetic disk, and a recording element for recording the data on the magnetic disk using the recording current in accordance with the determined recording current reversal timing. | 05-27-2010 |
20100128382 | MAGNETIC RECORDING DEVICE AND MAGNETIC RECORDING METHOD THEREOF - A magnetic recording device according to one embodiment includes a magnetic recording medium having a magnetic recording layer; a recording element positioned on a head slider; an assistance element for supplying assistance energy to an area on the recording layer to which a recording magnetic field generated by the recording element is applied, the assistance element being positioned on the head slider; and a controller for controlling a size of an assistance area from the assistance element in accordance with a position of the head slider in a radial direction of the magnetic recording medium. Additional systems and methods are also presented. | 05-27-2010 |
20100142077 | MAGNETIC RECORDING/REPRODUCING USING A PATTERNED MEDIUM - To synchronize a write/read frequency with media with high precision even when a write head is positioned in a different zone in a magnetic recording/reproducing device equipped with patterned media formed with writing hit patterns and having a zoned format function, a write head is positioned on a recording track in the vicinity of a boundary between zones, and the write head is positioned in a different zone from the zone in which the read head is positioned, the preamble pattern in the zone in which the read head is positioned is reproduced, a difference between frequencies of the preamble patterns of the zones is compensated to determine a write frequency used for writing data into a desired track, and then start timing for writing is determined based on a synchronization pattern obtained at the position of the read head. Other systems and methods are presented as well. | 06-10-2010 |
20110096638 | HEAD-SLIDER INCLUDING A MAGNETIC-RECORDING ASSISTANCE ELEMENT, HEAD-ARM ASSEMBLY INCLUDING THE HEAD-SLIDER, AND HARD-DISK DRIVE INCLUDING THE HEAD-ARM ASSEMBLY - A head-slider configured to fly in proximity to a recording surface of a magnetic-recording disk. The head-slider includes a write element including a main pole configured to generate a magnetic-recording field from a pole tip of the main pole in a first localized portion of the magnetic-recording disk. The head-slider also includes a magnetic-recording assistance element configured to provide energy to a second localized portion of the magnetic-recording disk in order to increase reversibility of a magnetization in a first localized portion of the magnetic-recording disk. A width of the pole tip of the main pole on a leading-edge side is wider than a width of the pole tip of the main pole on a trailing-edge side. | 04-28-2011 |
20150138937 | SELF-CONTROLLED LASER PULSING FOR THERMALLY ASSISTED RECORDING - A method of storing data includes providing a write signal for a write head of a hard disk drive, generating a transition pulse signal derived from the write signal using a transition pulse generator, and generating a logic signal to drive a thermal source associated with the write head of the hard disk drive. The logic signal includes the logical summation of a cyclical base pulse signal and the transition pulse signal. | 05-21-2015 |
Patent application number | Description | Published |
20080286997 | CONNECTOR - A connector includes a first and a second terminal portions each having: a substrate pressing portion; a spacer pressing portion; and a fulcrum portion arranged between the substrate pressing portion and the spacer pressing portion, a spacer arranged between the spacer pressing portions of the first and the second terminal portions, and a clipping section formed of the substrate pressing portions of the first and the second terminal portions. The clipping section opens and closes while operating the fulcrum portions as a fulcrum. The spacer pressing portions of the first and the second terminal portions close via the fulcrum when the clipping section opens. | 11-20-2008 |
20090042442 | RUBBER STOPPER FOR WATERPROOF CONNECTOR AND WATERPROOF CONNECTOR - A rubber stopper for a waterproof connector includes: a first elastic member including a first contact face, and first wire fitting grooves each having an arc cross-section; and a second elastic member including a second contact face and second wire fitting grooves each having an arc cross-section. When the first contact face contacts the second contact face, circular cross-section is formed by the arc cross-sections of the first and second wire fitting grooves to fit wires into the first and second wire fitting grooves. Arc length of the arc cross-section of the first wire fitting groove is different from arc length of the arc cross-section of the second wire fitting groove so that a center of the circular cross-section is disposed away from the first and second contact faces in a direction perpendicular to an extending direction of the first and the second contact faces. | 02-12-2009 |
20090149079 | SURFACE-MOUNTED CONNECTOR | 06-11-2009 |
20100015864 | MANUFACTURING METHOD OF PIN-LIKE MALE TERMINAL FOR BOARD-MOUNTING CONNECTOR - A method of manufacturing a terminal for a board-mounting connector, wherein the terminal includes two L-shaped bent portions formed at its intermediate portion between its front and rear ends, a straight electrical contact portion formed at its front end, and a straight rear leg portion, the method includes a stamping operation applied to a stock to form a stamped-out terminal including the two bent portions, the electrical contact portion and the rear leg portion. | 01-21-2010 |
20120100753 | L-SHAPED CONNECTOR - An L-shaped connector, which can waterproof simply and connect an L-shape terminal to an electric shield wire in miniaturized size so as to insulate and electromagnetic shield the L-shaped terminal, includes an L-shaped dividable insulation inner housing receiving an L-shaped terminal joined to the electric shield wire; an electric conductive shield shell covering a terminal receiving portion of the inner housing; an outer housing covering the shield shell; an electric conductive housing receiving a wire lead-out portion of the inner housing, and joining a flange of the shield shell and a flange of the outer housing to a flange of the electric conductive housing by screwing, and connecting a shield portion of the electric shield wire through a shield terminal to the shield shell; and a shield packing waterproofing between the flange of the shield shell and the flange of the electric conductive shell. | 04-26-2012 |
20120252272 | INSULATING STRUCTURE FOR L-SHAPED TERMINAL - To electromagnetically-shield an L-shaped terminal in a compact and reliable manner while easily and securely fixing the L-shaped terminal, there is employed an insulating split inner housing having an L-shaped terminal receiving portion including an electric-contact-portion-side receiving portion covering an electric contact portion of the L-shaped terminal connected to a shielded wire and a wire-connection-portion-side receiving portion covering a wire connection portion of the L-shaped terminal, the electric-contact-portion-side receiving portion is covered by a conductive shield shell, the wire-connection-portion-side receiving portion is covered by a conductive housing connected to the shield shell and to a shield portion of the shielded wire, and the L-shaped terminal is insulated by the inner housing from the shield shell and the conductive housing. | 10-04-2012 |
20130019471 | METHOD FOR MANUFACTURING CONNECTOR - In order to avoid cost for accommodating a shield wire in a housing while bending, and smoothly and readily accommodate within the housing while the shield electric wire is insulated, a conductive housing | 01-24-2013 |
20130029524 | CONNECTING STRUCTURE OF SHIELD TERMINALS - There is provided a connecting structure of shield terminals configured to tighten and connect a pair of shield terminals with a single bolt simultaneously in a smaller space with an object of reducing the number of components and the component cost by sharing the same type shield terminals. The connecting structure of shield terminals includes: two shield terminals | 01-31-2013 |
20130084728 | SHIELD CONNECTOR - A shield connector includes a housing and a shield terminal. The housing, has a tubular shape so that a shield electric wire is inserted thereinto, and is attached to an objective body so as to communicate with an insert hole of the objective body. The shield terminal, has a tubular shape, is electrically conductive, is attached to an inner peripheral side of the housing, and is electrically conducted to the objective body and the shield layer. A seal member having a tubular shape is provided between an inner periphery of the insert hole and the shield electric wire and between the shield terminal and the shield electric wire, so as to seal a part between the inner periphery of the insert hole and an outer periphery of the shield electric wire and a part between an inner periphery of the shield terminal and the outer periphery of the shield electric wire. | 04-04-2013 |
20130095683 | LOW INSERTION FORCE CONNECTOR UNIT WITH SAFETY CIRCUIT UNIT - An object is to surely connect and disconnect the safety circuit for connectors with good workability. A low insertion force connector unit with a safety circuit unit | 04-18-2013 |
20130237074 | CONNECTOR UNIT - A connector unit which prevents a user from contacting a first terminal fitting when fitting a first connector and a second connector together is provided. A connector unit | 09-12-2013 |
Patent application number | Description | Published |
20090004889 | Board-connecting connector - A board-connecting connector including a pair of inner housings opposed to each other for receiving elastic contact terminals with respect to a circuit board, a guiding plate having a sloped guiding part for engaging inner housing-driven projections and guiding the inner housings close to each other, and an outer housing for receiving the inner housings and the guide plate, and holding the guide plate. When the circuit board is fully inserted into the pair of inner housings, the circuit board abuts on the inner housings, and pushes to move the inner housings along the guiding plate. | 01-01-2009 |
20100136814 | PACKING AND CONNECTOR HAVING THE SAME - [Problems] To provide a packing which makes it easy to connect the connector housing to which the packing is attached to the mating connector housing, and keeps a connecting area between the connector housing watertight, and to provide a connector having the packing. | 06-03-2010 |
20100136842 | CONNECTOR - A connector which can be made small is provided. The connector | 06-03-2010 |
20120295479 | WATERTIGHT SHIELD CONNECTOR - An object of the present invention is to provide a watertight shield connector able to waterproof successfully without an effect of a parting line, and surely preventing an annular packing or a shield shell from falling out with a plain structure. For attaining the object, there is provided a watertight shield connector | 11-22-2012 |
Patent application number | Description | Published |
20100194930 | ZOOM LENS SYSTEM, INTERCHANGEABLE LENS APPARATUS AND CAMERA SYSTEM - Provided is a zoom lens system including a compact focusing lens unit and having a suppressed change in image magnification at the time of movement of the focusing lens unit. The zoom lens system of the present invention includes, in order from an object side to an image side, a first lens unit G | 08-05-2010 |
20100195216 | ZOOM LENS SYSTEM, INTERCHANGEABLE LENS APPARATUS AND CAMERA SYSTEM - Provided is a zoom lens system including a compact focusing lens unit and having a suppressed change in image magnification at the time of movement of the focusing lens unit. A zoom lens system of the present invention, in order from an object side to an image side, includes, a first lens unit G | 08-05-2010 |
20100196003 | ZOOM LENS SYSTEM, INTERCHANGEABLE LENS APPARATUS AND CAMERA SYSTEM - Provided is a zoom lens system including a compact focusing lens unit and having a suppressed change in image magnification at the time of movement of the focusing lens unit. The zoom lens system of the present invention includes an aperture diaphragm A, a first lens unit G | 08-05-2010 |
20130141629 | SINGLE FOCAL LENGTH LENS SYSTEM, INTERCHANGEABLE LENS APPARATUS AND CAMERA SYSTEM - A single focal length lens system comprising a front lens unit, an aperture diaphragm, and a rear lens unit, wherein the front lens unit is composed of three or less lenses including a negative lens located closest to the object side and a positive lens located on the image side relative to the negative lens, and does not move along an axis in focusing, the rear lens unit includes a focusing lens unit moving along the axis and a fixed lens unit not moving along the axis in focusing, and the conditions: 0.406-06-2013 | |
20130148006 | SINGLE FOCAL LENGTH LENS SYSTEM, INTERCHANGEABLE LENS APPARATUS AND CAMERA SYSTEM - A single focal length lens system comprising: at least a front lens unit having positive or negative power, and being fixed in focusing; a focusing lens unit having positive power, and moving along an optical axis in focusing; and a rear lens unit having negative power, and being fixed in focusing, wherein the focusing lens unit includes: a cemented lens of a negative lens and a positive lens; and a positive single lens located on the image side relative to the cemented lens and having an aspheric surface, the rear lens unit is composed of one single lens, and the condition: −0.506-13-2013 | |
20150185399 | SURFACE LIGHT SOURCE APPARATUS - A surface light source apparatus includes an end face for taking in light emitted from a light source and a main surface for emitting the light. The surface light source apparatus further includes a plurality of structure bodies formed on an opposed surface disposed opposite to the main surface in the surface light source apparatus, each of which has a reflecting surface facing the point light source. Each structure body has a cut-off portion which removes a portion on the reflecting surface in a longitudinal direction of the structure body and in a height direction. | 07-02-2015 |
Patent application number | Description | Published |
20150214950 | PROGRAMMABLE LOGIC CIRCUIT AND NONVOLATILE FPGA - A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain. | 07-30-2015 |
20150244373 | Nonvolatile Programmable Logic Switch - A nonvolatile programmable logic switch of an embodiment includes: a cell including: a first memory including a first terminal connected to a first wiring line, and a second terminal; a second memory including a third terminal connected to a second wiring line, and a fourth terminal connected to the second terminal of the first memory; a first transistor, of which one of a source and a drain is connected to the second and fourth terminals, the other of the source and the drain is connected to a third wiring line, and a gate is connected to a fourth wiring line; and a second transistor, of which one of a source and a drain is connected to the second and fourth terminals, the other of the source and the drain is connected to a gate of a pass transistor, and a gate is connected to a fifth wiring line. | 08-27-2015 |
20150262624 | SEMICONDUCTOR NONVOLATILE MEMORY DEVICE - A semiconductor nonvolatile memory device of an embodiment includes: a plurality of transistors arranged in a matrix, the transistors in the same row being connected in series to form a transistor string having a first terminal and a second terminal; a plurality of first wiring lines each corresponding to one of the columns, and being connected to the gates of the transistors of the corresponding column; a common first electrode connected to each semiconductor region in which each transistor is disposed; and a write unit that selects one of the first wiring lines and one of the transistor strings, and applies a first voltage to the first electrode, a first write voltage to the selected first wiring line, a second voltage to the other first wiring lines, and a second write voltage to the first terminal and the second terminal of the selected transistor string in a write operation. | 09-17-2015 |
20150263072 | PROGRAMMABLE LOGIC DEVICE - A programmable logic device includes: a first memory element including a first electrode connected to a first wiring line, a second electrode, and a first resistive change layer, a resistance between the first and second electrodes being changed from a low-resistance state to a high-resistance state by applying, to the second electrode, a voltage higher than a voltage applied to the first electrode; a second memory element. including a third electrode connected to the second electrode, a fourth electrode connected to a second wiring line, and a second resistive change layer, a resistance between the third and fourth electrodes being changed from a low-resistance state to a high-resistance state by applying, to the fourth electrode, a voltage higher than a voltage applied to the third electrode; and a first transistor, of which a gate is connected to the second electrode and the third electrode. | 09-17-2015 |
20150348631 | NONVOLATILE MEMORY, NONVOLATILE PROGRAMMABLE LOGIC SWITCH INCLUDING NONVOLATILE MEMORY, AND NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile memory according to an embodiment includes a memory cell, the memory cell including: a memory transistor including a source, a drain, a gate electrode disposed above a channel between the source and the drain, and a gate insulating film disposed between the channel and the gate electrode; and a fuse element disposed between the gate electrode and a wiring line to which the gate electrode of the memory transistor is connected. | 12-03-2015 |
20150357032 | MULTI-CONTEXT CONFIGURATION MEMORY - According to one embodiment, an integrated circuit includes first and second data lines, a first memory cell includes first and second resistance changing elements connected in series between the first and second data lines and a first selection transistor including a drain connected to a connection node of the first and second resistance changing elements, and a second memory cell includes third and fourth resistance changing elements connected in series between the first and second data lines and a second selection transistor including a drain connected to a connection node of the third and fourth resistance changing elements. | 12-10-2015 |
20160035419 | RECONFIGURABLE CIRCUIT AND METHOD OF PROGRAMMING THE SAME - A reconfigurable circuit according to an embodiment includes: first wiring lines; second wiring lines crossing the first wiring lines; resistive change elements disposed in intersection regions of the first and second wiring lines, each of the resistive change elements including a first terminal connected to the one of the first wiring lines and a second terminal connected to the one of the second wiring lines, and being switchable between a low-resistance state and a high-resistance state; a first control circuit controlling a voltage to be applied to the first wiring lines; a second control circuit controlling a voltage to be applied to the second wiring lines; and current limiting elements corresponding to the second wiring lines, and controlling current flowing through the resistive change elements connected to the corresponding second wiring line. | 02-04-2016 |
20160078933 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes a memory cell including first and second electrodes and a resistance change film therebetween, and a control circuit controlling a potential difference between the first and second electrodes. The control circuit reversibly changes the memory cell to a first resistive state by applying a first potential to the first electrode and by applying a second potential smaller than the first potential to the second electrode. The control circuit reversibly changes the memory cell to a second resistive state by applying a third potential to the first electrode and by applying a fourth potential smaller than the third potential to the second electrode. | 03-17-2016 |
20160078935 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: first and second wiring lines; resistive change memories disposed intersection regions of the first and second wiring lines; and a control circuit controlling the first and second drivers to select one of the first wiring lines and one of the second wiring lines, the control circuit changing a resistance of the selected one of the resistive change memories from the first resistive state to the third resistive state, and then changing the resistive state of the selected one of the resistive change memories from the third resistive state to the second resistive state. | 03-17-2016 |
20160079983 | RECONFIGURABLE CIRCUIT - According to one embodiment, a reconfigurable circuit includes first, second, third and fourth circuit blocks arranged with a matrix, a first conductive line shared by the first and second circuit blocks, a second conductive line shared by the third and fourth circuit blocks, a third conductive line shared by the first and third circuit blocks, the third conductive line crossing the first and second conductive lines, a fourth conductive line shared by the second and fourth circuit blocks, the fourth conductive line crossing the first and second conductive lines, a first controller controlling voltages to be applied to the first and second conductive lines, and a second controller controlling voltages to be applied to the third and fourth conductive lines. | 03-17-2016 |
20160088243 | IMAGING ELEMENT, IMAGING APPARATUS, AND SEMICONDUCTOR APPARATUS - According to an embodiment, an imaging element includes a plurality of light receiving elements, a plurality of scanning circuits, a first line comprising a plurality of nodes, and a plurality of first variable resistance elements. The plurality of scanning circuits are respectively connected to the plurality of light receiving elements. Each of the plurality of first variable resistance elements is connected between the corresponding one of the nodes and a corresponding one of the scanning circuits. At least one of the first variable resistance elements includes a plurality of resistance elements connected to each other in parallel. | 03-24-2016 |
20160112049 | PROGRAMMABLE LOGIC CIRCUIT AND NONVOLATILE FPGA - A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain. | 04-21-2016 |
Patent application number | Description | Published |
20140022840 | NON-VOLATILE PROGRAMMABLE SWITCH - According to one embodiment, a non-volatile programmable switch according to this embodiment includes first and second non-volatile memory transistors, and a common node that is connected to the output side terminals of the first and second non-volatile memory transistors, and a logic transistor unit that is connected to the common node. A length of a gate electrode of the first and second non-volatile memory transistors in a channel longitudinal direction is shorter than a length of the charge storage film in the channel longitudinal direction. | 01-23-2014 |
20140035616 | RECONFIGURABLE INTEGRATED CIRCUIT DEVICE AND WRITING METHOD THEREOF - A reconfigurable integrated circuit device includes a memory unit for storing configuration information. The memory unit has a nonvolatile memory transistor having a gate connected to a first wire, a first terminal connected to a second wire, and a second terminal connected to a third wire. The memory unit also includes a switch circuit connected to the third wire. The switch circuit alters the configuration of the integrated circuit device by, for example, opening and closing to make wiring connections or disconnections. The integrated circuit device additionally includes a data supply circuit for supplying bit data and a first power supply circuit for supplying voltages to the first wire for storing bit data in the first nonvolatile memory transistor and for storing bit data as a charge level on the third wire. | 02-06-2014 |
20140035618 | CIRCUIT HAVING PROGRAMMABLE MATCH DETERMINATION FUNCTION, AND LUT CIRCUIT, MUX CIRCUIT AND FPGA DEVICE WITH SUCH FUNCTION AND METHOD OF DATA WRITING - A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line. | 02-06-2014 |
20140061765 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a transistor with a source region, a drain region, and a control gate electrode. The integrated circuit additionally includes a controller that selectively applies voltages to the control gate of the transistor. The controller may apply a first voltage that that forms a permanent conductive path between the source and drain of the transistor. | 03-06-2014 |
Patent application number | Description | Published |
20130076392 | NONVOLATILE PROGRAMMABLE LOGIC SWITCH - A nonvolatile programmable logic switch according to an embodiment includes first and second cells, each of the first and second cells including: a first memory having a first to third terminals, the third terminal being receiving a control signal; a first transistor connected at one of source/drain to the second terminal; and a second transistor connected at a gate to the other of the source/drain of the first transistor, the third terminal of the first memory in the first cell and the third terminal of the first memory in the second cell being connected in common. When conducting writing into the first memory in the first cell, the third terminal is connected to a write power supply generating a write voltage, the first terminals in the first and second cells are connected to a ground power supply and a write inhibit power supply generating a write inhibit voltage respectively. | 03-28-2013 |
20130134499 | NONVOLATILE PROGRAMMABLE SWITCHES - A nonvolatile programmable switch according to an embodiment includes: a first nonvolatile memory transistor including a first to third terminals connected to a first to third interconnects respectively; a second nonvolatile memory transistor including a fourth terminal connected to a fourth interconnect, a fifth terminal connected to the second interconnect, and a sixth terminal connected to the third interconnect, the first and second nonvolatile memory transistors having the same conductivity type; and a pass transistor having a gate electrode connected to the second interconnect. When the first and fourth interconnects are connected to a first power supply while the third interconnect is connected to a second power supply having a higher voltage than that of the first power supply, a threshold voltage of the first nonvolatile memory transistor increases, and a threshold voltage of the second nonvolatile memory transistor decreases. | 05-30-2013 |
20130215670 | MEMORY CIRCUIT AND FIELD PROGRAMMABLE GATE ARRAY - A memory circuit according to an embodiment includes: a plurality of memory cells each having one pair of first and second nonvolatile memory circuits, each of the first and second nonvolatile memory circuits in each memory cell being capable of making a transition between a high resistance state and a low resistance state, and in a state in which one memory cell in the plurality of memory cells has information stored therein, one of the first and second nonvolatile memory circuits in the one memory cell being in a high resistance state whereas the other being in a low resistance state. | 08-22-2013 |
20130222011 | PROGRAMMABLE LOGIC SWITCH - One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory. | 08-29-2013 |
20130241596 | PROGRAMMABLE LOGIC DEVICE - One embodiment provides a programmable logic device in which a logic switch includes: a first memory having a first terminal connected to a first wire, a second terminal connected to a second wire, and a third terminal connected to a third wire; a second memory having a fourth terminal connected to the first wire, a fifth terminal connected to a fourth wire, and a sixth terminal connected to a fifth wire; and a pass transistor having a gate connected to the first terminal, and a source and a drain respectively connected to a sixth wire and a seventh wire. A source or drain of a first select gate transistor is connected the sixth wire, and a source or drain of a second select gate transistor is connected to the seventh wire. | 09-19-2013 |
20130248959 | PROGRAMMABLE LOGIC SWITCH - According to one embodiment, a programmable logic switch includes first and second word lines above a first path transistor, a first pillar passing through the first and second word lines and connected to the first path transistor, a second pillar passing through the first and second word lines and connected to the first path transistor, a first memory device between the first pillar and the first word line, a second memory device between the first pillar and the second word line, a third memory device between the second pillar and the first word line, and a fourth memory device between the second pillar and the second word line. | 09-26-2013 |
20130258782 | CONFIGURATION MEMORY - According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node. | 10-03-2013 |
20130307054 | SEMICONDUCTOR INTEGRATED CIRCUIT - One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories. | 11-21-2013 |
20140035619 | SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAMMABLE LOGIC DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CITCUIT - According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode. | 02-06-2014 |
20140131811 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: a first transistor having a first source region and a first drain region arranged in a first protruded semiconductor region, a first channel region having a first corner portion in its upper portion in a section perpendicular to a first direction, the first corner portion having a first radius of curvature; a second transistor having a second source region and a second drain region arranged in a second protruded semiconductor region, and a second channel region having a second corner portion in its upper portion in a section that is perpendicular to a second direction, the second corner portion having a second radius of curvature greater than the first radius of curvature. | 05-15-2014 |
20150014748 | SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAMMABLE LOGIC DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode. | 01-15-2015 |
Patent application number | Description | Published |
20110246052 | CONGESTION LEVEL DISPLAY APPARATUS, CONGESTION LEVEL DISPLAY METHOD, AND CONGESTION LEVEL DISPLAY SYSTEM - In a congestion level display apparatus for a vehicle, a correlation between a traveling speed and a congestion level sent from a traffic center is learnt when the vehicle is travelling within a home area. When the vehicle is traveling outside the home area, the learned correlation is used, by the congestion level display apparatus and in relation to the traveling speed, to display a learned congestion level, instead of the congestion level sent from the traffic center. | 10-06-2011 |
20110276257 | NAVIGATION DEVICE, PROBE INFORMATION TRANSMISSION METHOD, COMPUTER-READABLE STORAGE MEDIUM THAT STORING PROBE INFORMATION TRANSMISSION PROGRAM, AND TRAFFIC INFORMATION GENERATION DEVICE - When a vehicle passes through an intersection that is stored in a collection target intersection database and for which direction-specific probe information is collected, a CPU of a navigation device generates a plurality of direction-specific probe information (entry link, exit link, section travel time, and the like) from a plurality of unit distance section information that is collected within a direction-specific traffic information acquisition section until the vehicle passes through the intersection, an entry link traveled before entering the intersection; and an exit link traveled after passing through the intersection, and transmits these to an information distribution center. | 11-10-2011 |
20120041669 | TRAFFIC INFORMATION MANAGEMENT DEVICE, TRAFFIC INFORMATION MANAGEMENT METHOD, AND TRAFFIC INFORMATION MANAGEMENT PROGRAM - Conventionally, different traffic information cannot be sent in accordance with an output reason of a request to send. According to the present invention, a request to send traffic information, which is output in response to an instruction given by a user operation or an automatically given instruction, is acquired, an output reason of the request to send is determined, and a communication unit is controlled so that the traffic information on different areas is sent depending on the cases where the output reason is the instruction given by the user operation or the automatically given instruction. | 02-16-2012 |
20120245833 | VEHICLE GUIDANCE DEVICE, VEHICLE GUIDANCE METHOD, AND VEHICLE GUIDANCE PROGRAM - A vehicle guidance device includes: an inter- vehicle distance specification unit that specifies an inter-vehicle distance, which is an inter-vehicle distance in a prescribed lane, between vehicles up to a reference point of a lane change; a recommended section specification unit based on the specified inter-vehicle distance, specifies a recommended section in which a lane change to the prescribed lane should be made before reaching the reference point; and a communication unit that, based on the specified recommended section, outputs guidance information pertaining to the lane change to the prescribed lane. | 09-27-2012 |
20120265428 | VEHICLE MOTION ESTIMATING DEVICE, VEHICLE MOTION ESTIMATING METHOD, AND VEHICLE MOTION ESTIMATING PROGRAM - According to the present invention, information which is associated with a motion of a vehicle can be acquired even in the case where no vehicle travels on a road. Motion information, which is associated with the motion of the vehicle on the road where the vehicle traveled, is acquired along with time information. Reference traffic information, which is traffic information on the road at a reference time which is specified by the time information, is acquired from a traffic information providing device which constantly provides the traffic information. A correlation between the motion information and the reference traffic information is specified. Furthermore, estimated motion information, which indicates an estimated motion of the vechicle on the road at an estimate time when the motion is estimated, is acquired based on estimating source traffic information at the estimate time and the correlation, the estimating source traffic information being provided as the traffic information of the estimating source from the traffic information providing device in the case where no motion information is acquired at the estimate time. | 10-18-2012 |
Patent application number | Description | Published |
20110203726 | METHOD FOR MANUFACTURING RESIN MOLDING - A method for manufacturing a resin molding that uses a laser beam can provide a high level of adhesion, an excellent appearance, and can include very strong welded portions. The method can include preparing a light-transmitting resin member having a protruding portion formed on a rear surface of the light-transmitting resin member and having an end surface, the protruding portion having both side surfaces having asymmetric inclination angles with respect to the normal of the end surface of the protruding portion. The method can also include arranging and pressing together the end surface of the protruding portion that is a welded region of the light-transmitting resin member, and a welded region of a corresponding light-absorbing resin member so that they are opposed to each other. A laser beam can be emitted from a laser light source to be incident on a surface of the light-transmitting resin member while the laser beam is refracted. The method can also include repeatedly irradiating the laser beam onto the welded regions to heat and fuse the entire welded regions to weld the light-transmitting resin member and the light-absorbing resin member while opposed to each other and pressed together, wherein the inclination angle of the side surface of the protruding member near the laser light source is equal to or more than a travel angle of the refracted laser beam. | 08-25-2011 |
20110298160 | METHOD FOR MANUFACTURING RESIN MOLDING AND LASER BEAM IRRADIATION APPARATUS - A method for manufacturing a resin molding can be provided that uses a laser beam. The method can include providing the resin molding including welded portions that can impart high level of adhesion, have excellent appearance and provide very strong bonding strength. The method can also include arranging and pressing a weld region of a light-absorbing resin member and corresponding weld region of a light-transmitting resin member that are opposed to each other, and setting a plurality of irradiation areas in the extending direction of the welded regions. The method can also include arranging a plurality of laser irradiation scanning heads corresponding to the irradiation areas. Here, the irradiation areas can include a single irradiation area which the corresponding scanning head can irradiate with the laser beam and a composite irradiation area which the adjacent scanning heads can irradiate with respective laser beams. The method can further include causing the plurality of laser beams emitted from the scanning heads to repeatedly scan the single irradiation area along a first trajectory in the extending direction of the single irradiation area and part of both the single irradiation area and the composite irradiation area along a second trajectory in the extending direction, so that the entire welded regions are heated and fused to weld the light-transmitting resin member and the light-absorbing resin member. | 12-08-2011 |
20110317443 | VEHICLE LIGHTING FITTING AND METHOD FOR MANUFACTURING VEHICLE LIGHTING FITTING - A vehicle lighting fitting can include a housing including an opening end portion, a lens, an outer peripheral portion of which is laser-welded to the opening end portion to define a lighting chamber, and a decorative member disposed in the lighting chamber. The resin decorative member can include an outer peripheral portion on which a joint portion and a non-joint portion are alternately formed along a perimeter thereof, wherein the joint portion of the decorative member and the opening end portion of the housing are laser-welded in a state in which clearances are maintained between the non-joint portion of the decorative member and the housing, and between the lens and the housing. | 12-29-2011 |