Patent application number | Description | Published |
20080286664 | Full Phase Shifting Mask In Damascene Process - A full phase shifting mask (FPSM) can be advantageously used in a damascene process for hard-to-etch metal layers. Because the FPSM can be used with a positive photoresist, features on an original layout can be replaced with shifters on a FPSM layout. Adjacent shifters should be of opposite phase, e.g. 0 and 180 degrees. In one embodiment, a dark field trim mask can be used with the FPSM. The trim mask can include cuts that correspond to cuts on the FPSM. Cuts on the FPSM can be made to resolve phase conflicts between proximate shifters. In one case, exposing two proximate shifters on the FPSM and a corresponding cut on the trim mask can form a feature in the metal layer. The FPSM and/or the trim mask can include proximity corrections to further improve printing resolution. | 11-20-2008 |
20090125867 | Handling Of Flat Data For Phase Processing Including Growing Shapes Within Bins To Identify Clusters - Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the overlapping shapes can be grouped together to identify shapes that should be processed together. For large layouts, growing and grouping the shapes can be time consuming. Therefore, an approach that uses bins can speed up the clustering process, thereby allowing the phase shifting to be performed in parallel on multiple computers. Additional efficiencies result if identical clusters are identified and processing time saved so that repeated clusters of shapes only undergo the computationally expensive phase shifter placement and assignment process a single time. | 05-14-2009 |
20090249266 | Displacing Edge Segments On A Fabrication Layout Based On Proximity Effects Model Amplitudes For Correcting Proximity Effects - Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias. | 10-01-2009 |
20100040965 | Exposure control for phase shifting photolithographic masks - Mask and integrated circuit fabrication approaches are described to facilitate use of so called “full phase” masks. This facilitates use of masks where substantially all of a layout is defined using phase shifting. In one embodiment, the phase shifting mask and the trim mask are exposed using substantially the same exposure conditions. These approaches facilitate better exposure profiles for the resulting ICs and can thus improve chip yield and increase throughput by reducing the need to alter settings and/or switch reticles between exposures. | 02-18-2010 |
20100050149 | Design and Layout of Phase Shifting Photolithographic Masks - A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts. | 02-25-2010 |
20100218156 | SYSTEM AND METHOD FOR COMPRESSED POST-OPC DATA - According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process. | 08-26-2010 |
20100251202 | Lithography Modelling And Applications - The manufacturing of integrated circuits relies on the use of lithography simulation to predict the image of the mask created on the wafer. Such predictions can be used for example to assess the quality of the images, verify the manufacturability of such images, perform using OPC necessary correction of the mask data to achieve images close to the targets, optimize the printing parameters such as the illumination source, or globally optimize the source and the mask to achieve better printability. This disclosure provides a technique based on the association of at least one kernel function per source region or source point. Each kernel function can be directly convoluted with a mask image to create a prediction of the wafer image. As the kernel functions are associated with the source, the source can be easily changed to create new models. The optical system can be fully described by computing the possible kernels for all possible source points and all possible numerical apertures. Therefore this technique is ideally suited for source-mask optimization as well as source-mask-numerical aperture optimization, and their associated applications. | 09-30-2010 |
20100299646 | UNIFORMITY FOR SEMICONDUCTOR PATTERNING OPERATIONS - Systems and methods of semiconductor device optimization include a system and method to determine a dataset for a layer of the semiconductor device, where the operation includes receiving a dataset defining a plurality of original patterns of sacrificial material in a layer of a semiconductor device, wherein the original patterns of sacrificial material are used to define placement of spacer material to define patterning of circuit elements for the semiconductor device; determining densities of the plurality of original patterns of sacrificial material in areas across a portion of the layer of the semiconductor device; and augmenting the dataset to include an additional pattern of sacrificial material in an area of the layer having a density lower than a threshold density. | 11-25-2010 |
20110012237 | SPACER DOUBLE PATTERNING FOR LITHOGRAPHY OPERATIONS - Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the tilled pattern to remove portions of the final material beyond dimensions of the layout elements. | 01-20-2011 |
20110018146 | SPACER DOUBLE PATTERNING FOR LITHOGRAPHY OPERATIONS - Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the filled pattern to remove portions of the final material beyond dimensions of the layout elements. | 01-27-2011 |
20110207056 | Contact or proximity printing using a magnified mask image - Improvements in the fabrication of integrated circuits are driven by the decrease of the size of the features printed on the wafers. Current lithography techniques limits have been extended through the use of phase-shifting masks, off-axis illumination, and proximity effect correction. More recently, liquid immersion lithography has been proposed as a way to extend even further the limits of optical lithography. This invention described a methodology based on contact or proximity printing using a projection lens to define the image of the mask onto the wafer. As the imaging is performed in a solid material, larger refractive indices can be obtained and the resolution of the imaging system can be increased. | 08-25-2011 |
20130346037 | Lithography Modeling And Applications - The manufacturing of integrated circuits relies on the use of lithography simulation to predict the image of the mask created on the wafer. Such predictions can be used for example to assess the quality of the images, verify the manufacturability of such images, perform using OPC necessary correction of the mask data to achieve images close to the targets, optimize the printing parameters such as the illumination source, or globally optimize the source and the mask to achieve better printability. This disclosure provides a technique based on the association of at least one kernel function per source region or source point. Each kernel function can be directly convoluted with a mask image to create a prediction of the wafer image. As the kernel functions are associated with the source, the source can be easily changed to create new models. The optical system can be fully described by computing the possible kernels for all possible source points and all possible numerical apertures. Therefore this technique is ideally suited for source-mask optimization as well as source-mask-numerical aperture optimization, and their associated applications. | 12-26-2013 |