Patent application number | Description | Published |
20080209109 | INTERRUPTIBLE CACHE FLUSHING IN FLASH MEMORY SYSTEMS - Cache flushing is effected for a flash memory by copying, to a block of the memory, first and second portions of cached data, and servicing a host access in-between copying the first portion and the second portion. Either both portions are selected before the copying, or erasing the block is forbidden until after the copying, or a portion of the block left unwritten by the first copying remains unwritten until after the host access is serviced. | 08-28-2008 |
20080270682 | METHOD FOR USING A MULTI-BIT CELL FLASH DEVICE IN A SYSTEM NOT DESIGNED FOR THE DEVICE - A computerized system is booted from a flash memory device configured to always operate one or more of its blocks only in a M-bit-per-cell mode and the rest of its blocks in a N>M-bit-per-cell mode. When the system is powered up, an initialization program is retrieved from the M-bit-per-cell block(s), corrected for errors using a first error correction method, and executed. Data accessed subsequently from the N-bit-per-cell blocks are corrected using an error correction method that corrects more errors per block than the first error correction method. | 10-30-2008 |
20080270730 | METHOD FOR EFFICIENT STORAGE OF METADATA IN FLASH MEMORY - User data are stored in a memory that includes one or more blocks of pages by, for one of the blocks, and optionally for all of the blocks, whenever writing any of the user data to that block, writing the block according to a predefined plan for specifying, with respect to each page of that block, a portion of the user data that is to be written to that page. Alternatively or additionally, each page that stores user data has associated therewith a metadatum related to the age of the user data stored therein; and, for one of the blocks, at any time that two or more of the pages of that block store user data, a common value of the metadatum is associated with all such pages. | 10-30-2008 |
20080285351 | MEASURING THRESHOLD VOLTAGE DISTRIBUTION IN MEMORY USING AN AGGREGATE CHARACTERISTIC - A threshold voltage distribution of a set of storage elements in a memory device is measured by sweeping a control gate voltage while measuring a characteristic of the set of storage elements as a whole. The characteristic indicates how many of the storage elements meet a given condition, such as being in a conductive state. For example, the characteristic may be a combined current, voltage or capacitance of the set which is measured at a common source of the set. The control gate voltage can be generated internally within a memory die. Similarly, the threshold voltage distribution can be determined internally within the memory die. Optionally, storage elements which become conductive can be locked out, such as by changing a bit line voltage, so they no longer contribute to the characteristic. New read reference voltages are determined based on the threshold voltage distribution to reduce errors in future read operations. | 11-20-2008 |
20080286082 | METHODS AND SYSTEMS FOR INTERRUPTED COUNTING OF ITEMS IN COUNTAINERS - Methods and systems for counting items in storage containers in an array of at least two storage containers, the method including the steps of: providing a storage array of at least two storage containers, each of the storage containers containing an unknown amount of items; providing a receiving array of at least two receiving containers, wherein the receiving containers initially contain no items; extracting a layer of the items from the storage array; inserting the layer into corresponding locations in the receiving array; repeating the steps of extracting and inserting while at least one of the storage containers is not empty; counting, for each storage container in the storage array, a productive-extraction amount; and reporting, for at least some of the storage containers, the productive-extraction amount from each storage container. Preferably, the method further includes recovering a storage identity upon recovery from a system failure that erases the productive-extraction amount. | 11-20-2008 |
20090070657 | METHOD OF ERROR CORRECTION IN MBC FLASH MEMORY - A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods. | 03-12-2009 |
20090080247 | USING MLC FLASH AS SLC BY WRITING DUMMY DATA - A method for storing data includes designating, in a memory array including cells configured for writing a first number of bits per cell, a group of the cells to which input data are to be written at a second number of bits per cell, smaller than the first number. Dummy data that are independent of the input data are stored in a first set of one or more bits of the cells in the group. The input data are written to a second set of at least one other bit of the cells in the group. | 03-26-2009 |
20090135646 | OPERATION SEQUENCE AND COMMANDS FOR MEASURING THRESHOLD VOLTAGE DISTRIBUTION IN MEMORY - A memory device generates one or more read reference voltages rather than being explicitly supplied with each read reference voltage from an external host controller. The technique involves providing a command to the memory device that causes a reading of a set of storage elements by the memory device using a reference voltage which is different than a reference voltage used in a previous reading, where the new read reference value is not explicitly set outside the memory device. In one implementation, the memory device is provided with an initial reference voltage and a step size for generating additional reference voltages. The technique can be used, e.g., in determining a threshold voltage distribution of a set of storage elements. In this case, a voltage sweep can be applied to a word line associated with the set of storage elements, and data obtained based on the number of conductive storage elements. | 05-28-2009 |
20090157974 | System And Method For Clearing Data From A Cache - A system and method for clearing data from a cache is disclosed. The method may include the steps of receiving data at a cache of a self-caching storage device, determining a cost-effectiveness of flushing a logical block from the cache and, if the current available capacity of the cache is greater than a minimum capacity parameter, only flushing the logical block if a predetermined criteria is met, regardless of whether the storage device is idle. The system may include a cache storage, a main storage and a controller configured to only flush a logical block from the cache if a determined cost effectiveness meets a predetermined criteria when the current available capacity of the cache is greater than a minimum capacity parameter. | 06-18-2009 |
20090172286 | Method And System For Balancing Host Write Operations And Cache Flushing - A method and system for balancing host write operations and cache flushing is disclosed. The method may include steps of determining an available capacity in a cache storage portion of a self-caching storage device, determining a ratio of cache flushing steps to host write commands if the available capacity is below a desired threshold and interleaving cache flushing steps with host write commands to achieve the ratio. The cache flushing steps may be executed by maintaining a storage device busy status after executing a host write command and utilizing this additional time to copy a portion of the data from the cache storage into the main storage. The system may include a cache storage, a main storage and a controller configured to determine and execute a ratio of cache flushing steps to host write commands by executing cache flushing steps while maintaining a busy status after a host write command. | 07-02-2009 |
20090183049 | PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY - Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal. | 07-16-2009 |
20090217124 | METHOD AND DEVICE FOR MULTI PHASE ERROR-CORRECTION - Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. A subset whose decoding is terminated is decoded again, at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits. | 08-27-2009 |
20090217131 | PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY - Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal. | 08-27-2009 |
20090268516 | METHOD FOR ADAPTIVE SETTING OF STATE VOLTAGE LEVELS IN NON-VOLATILE MEMORY - A method in which non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user. | 10-29-2009 |
20090268517 | NON-VOLATILE MEMORY WITH ADAPTIVE SETTING OF STATE VOLTAGE LEVELS - A non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user. | 10-29-2009 |
20090279362 | PARTIAL SCRAMBLING TO REDUCE CORRELATION - Decorrelation is provided between data stored in respective pairs of adjacent memory cells in a plurality of bit lines of a flash memory. Each of the pairs of adjacent memory cells is located along a respective one of the bitlines and common to two adjacent wordlines. The decorrelation is achieved by storing scrambled data in at least one memory cell of each of the pairs of adjacent memory cells and storing unscrambled data in at least one memory cell of at least one of the pairs of adjacent memory cells. | 11-12-2009 |
20090282267 | PARTIAL SCRAMBLING TO REDUCE CORRELATION - Decorrelation is provided between data stored in respective pairs of adjacent memory cells in a plurality of bit lines of a flash memory. Each of the pairs of adjacent memory cells is located along a respective one of the bitlines and common to two adjacent wordlines. The decorrelation is achieved by storing scrambled data in at least one memory cell of each of the pairs of adjacent memory cells and storing unscrambled data in at least one memory cell of at least one of the pairs of adjacent memory cells. | 11-12-2009 |
20090310413 | REVERSE ORDER PAGE WRITING IN FLASH MEMORIES - To store, in a memory block whose word lines are written successively in a word line writing order, a plurality of data pages that are ordered by logical page address, the pages are written to the word lines so that every page that is written to any one of the word lines has a higher logical page address than any page that is written to a subsequently written word line, regardless of the sequence in which the pages are received for writing. Alternatively, the pages are written to the word lines so that for every pair of written word lines, the word line of the pair that is earlier in the writing order has written thereto a page having a higher logical page address than at least one page written to the other word line of the pair. | 12-17-2009 |
20090319843 | METHOD AND APPARATUS FOR ERROR CORRECTION - Methods, apparatus and computer readable medium for handling error correction in a memory are disclosed. In some embodiments, after an attempt is made to write original data to a ‘target’ memory, data is read back from the target memory in a ‘first read operation’, thereby generating first read data. After the first read operation, the first read data is compared to the original data and/or an indication of a difference between the original data and the first data is determined. The information obtained by effecting the data-comparison and/or information related to the difference indication is used when correcting errors in data read back from the target memory in a ‘second read operation.’. The presently-disclosed teachings are applicable to any kind of memory including (i) non-volatile memories such as flash memory, magnetic memory and optical storage and (ii) volatile memory such as SRAM or DRAM. | 12-24-2009 |
20090327841 | PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY - Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal. | 12-31-2009 |
20100005367 | PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY - Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal. | 01-07-2010 |
20100005370 | PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY - Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal. | 01-07-2010 |
20100023800 | NAND Flash Memory Controller Exporting a NAND Interface - A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed. | 01-28-2010 |
20100049909 | NAND Flash Memory Controller Exporting a NAND Interface - A NAND controller for interfacing between a host device and a flash memory device (e.g. a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed. | 02-25-2010 |
20100057976 | MULTIPLE PERFORMANCE MODE MEMORY SYSTEM - A method and system for controlling a write performance level of a memory is disclosed. The method includes receiving an input at the memory, and configuring the memory to an operation mode providing a write performance level and a storage capacity. The input may specify a storage capacity, a working area capacity, a write performance level, and/or a ratio of the storage capacity to the working area capacity. A desired write performance level may be set by receiving a software command or hardware setting. The storage capacity may be varied depending on whether the memory device has been formatted. As the storage capacity decreases, working area capacity of the memory device increases and write performance increases. Conversely, as the storage capacity increases, working area capacity decreases and write performance decreases. | 03-04-2010 |
20100082537 | FILE SYSTEM FOR STORAGE DEVICE WHICH USES DIFFERENT CLUSTER SIZES - A file system for managing files in a storage device in a more optimal way by providing allocation units or clusters with non-uniform sizes. Clusters of at least two different sizes are allocated in a common partition of a storage device, such as a hard disk drive, other magnetic media, optical media and semiconductor storage such as flash memory and other non-volatile memory. At least two clusters are allocated in the storage device for storing the files. First and second allocated clusters are allocated to first and second portions of the storage device, respectively, and contain different numbers of sectors. One or more optimum cluster sizes can be selected for storing the files without knowing the size of the files in advance, based on factors such as whether compression is to be performed, file type, access patterns of a calling application, and an identification of the calling application. | 04-01-2010 |
20100082885 | METHOD AND SYSTEM FOR ADAPTIVE CODING IN FLASH MEMORIES - Bits are stored by attempting to set parameter value(s) of (a) cell(s) to represent some of the bits. In accordance with the attempt, an adaptive mapping of the bits to value ranges is provided and the value(s) is/are adjusted accordingly as needed. Or, to store (a) bit(s) in (a) cell(s), a default mapping of the bit(s) to a predetermined set of value ranges is provided and an attempt is made to set the cell value(s) accordingly. If, for one of the cells, the attempt sets the value such that the desired range is inaccessible, an adaptive mapping is provided such that the desired range is accessible. Or, to store (a) bit(s) in (a) cell(s), several mappings of the bit(s) to a predetermined set of ranges is provided. Responsive to an attempt to set the cell value(s) according to one of the mappings, the mapping to actually use is selected. | 04-01-2010 |
20100153660 | Ruggedized memory device - A non-volatile storage device with built-in ruggedized features is disclosed. The device processes a write command to a logical block address by writing the data from the command to a non-volatile memory within the non-volatile storage device and conditionally associating the data received from the command with its corresponding logical block address. Two or more received write commands define a set of commands associated with an atomic transaction. When an end of set command is received, the device unconditionally associates the received data with each write command with its corresponding logical block address. If a power loss interrupts the reception of a set of commands, the non-volatile storage device may recover the last consistent data state before the atomic transaction was started. A write command transaction identifier allows the device to associate the command with a thread of commands that define an atomic transaction in a multithreaded system. | 06-17-2010 |
20100169737 | METHOD AND DEVICE FOR MULTI PHASE ERROR-CORRECTION - Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits. | 07-01-2010 |
20100199135 | METHOD, SYSTEM AND COMPUTER-READABLE CODE TO TEST FLASH MEMORY - A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a flash controller die that is separate from the at least one flash memory die. The flash memory and the flash controller reside within, reside on, or are attached to a common housing. The flash controller is configured to execute at least one test program to test at least one flash memory die. | 08-05-2010 |
20100205362 | Cache Control in a Non-Volatile Memory Device - A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that manages data transfer between the cache memory portion and the main memory portion according to at least one caching command received from a host. The management of data transfer, by the controller, includes transferring new data from the host to the cache memory portion, copying the data from the cache memory portion to the main memory portion and controlling (enabling/disabling) the scheduling of cache cleaning operations. | 08-12-2010 |
20100262799 | METHOD AND APPARATUS FOR FACILITATING FAST WAKE-UP OF A NON-VOLATILE MEMORY SYSTEM - A method includes storing at a non-volatile memory in a data storage device a first copy of a memory management table. The method further includes storing, at the non-volatile memory, a list of data entries that identify unused blocks of the non-volatile memory, where the list defines an order of allocating the unused blocks. The method further includes, in response to detecting a power event, accessing an entry of the ordered list to identify a block, and selectively updating the first copy of the memory management table based on a status of the identified block. | 10-14-2010 |
20100274955 | Flash Memory Storage System and Method - A flash memory storage system includes a memory array containing a plurality of memory cells and a controller for controlling the flash memory array. The controller dedicates a first group of memory cells to operate with a first number of bits per cell and a second, separate group of memory cells to operate with a second number of bits per cell. A mechanism is provided to apply wear leveling techniques separately to the two groups of cells to evenly wear out the memory cells. | 10-28-2010 |
20110013450 | METHOD FOR ADAPTIVE SETTING OF STATE VOLTAGE LEVELS IN NON-VOLATILE MEMORY - A method in which non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user. | 01-20-2011 |
20110096603 | REVERSE ORDER PAGE WRITING IN FLASH MEMORIES - To store, in a memory block whose word lines are written successively in a word line writing order, a plurality of data pages that are ordered by logical page address, the pages are written to the word lines so that every page that is written to any one of the word lines has a higher logical page address than any page that is written to a subsequently written word line, regardless of the sequence in which the pages are received for writing. Alternatively, the pages are written to the word lines so that for every pair of written word lines, the word line of the pair that is earlier in the writing order has written thereto a page having a higher logical page address than at least one page written to the other word line of the pair. | 04-28-2011 |
20110231740 | Method for Recovering From Errors in Flash Memory - Methods, devices and computer readable code for reading data from one or more flash memory cells, and for recovering from read errors are disclosed. In some embodiments, in the event of an error correction failure by an error detection and correction module, the flash memory cells are re-read at least once using one or more modified reference voltages, for example, until a successful error correction may be carried out. In some embodiments, after successful error correction a subsequent read request is handled without re-writing data (for example, reliable values of the read data) to the flash memory cells in the interim. In some embodiments, reference voltages associated with a reading where errors are corrected may be stored in memory, and retrieved when responding to a subsequent read request. In some embodiments, the modified reference voltages are predetermined reference voltages. Alternatively or additionally, these modified reference voltages may be determined as needed, for example, using randomly generated values or in accordance with information provided by the error detection and correction module. Methods, devices and computer readable code for reading data for situations where there is no error correction failure are also provided. | 09-22-2011 |
20110258514 | OVERLAPPING ERROR CORRECTION OPERATIONS - Systems and methods of overlapping error correction operations are disclosed. A method at an encoder device includes receiving data bits to be encoded including a first bit, a second bit, and a third bit. A first encode operation to encode a first group of the data bits is initiated to generate a first codeword. The first group of the data bits includes the first bit and the second bit, but not the third bit. A second encode operation to encode a second group of the data bits is initiated to generate a second codeword. The second group of the data bits includes the second bit and the third bit, but not the first bit. | 10-20-2011 |
20110276856 | METHOD AND DEVICE FOR MULTI PHASE ERROR-CORRECTION - Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits. | 11-10-2011 |
20110283051 | MOVING EXECUTABLE CODE FROM A FIRST REGION OF A NON-VOLATILE MEMORY TO A SECOND REGION OF THE NON-VOLATILE MEMORY - A data storage device includes a controller and a non-volatile memory coupled to the controller. The non-volatile memory includes executable boot code that is executable by a processor associated with the data storage device. The controller is configured to read a first portion of the executable boot code from a first region of the non-volatile memory, and in response to detecting a condition, move a second portion of the executable boot code in a second region of the non-volatile memory to a third region of the non-volatile memory. | 11-17-2011 |
20120042219 | States Encoding in Multi-Bit Flash Cells for Optimizing Error Rate - Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2 | 02-16-2012 |
20120173807 | Cache Control in a Non-Volatile Memory Device - A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that manages data transfer between the cache memory portion and the main memory portion according to at least one caching command received from a host. The management of data transfer, by the controller, includes transferring new data from the host to the cache memory portion, copying the data from the cache memory portion to the main memory portion and controlling (enabling/disabling) the scheduling of cache cleaning operations. | 07-05-2012 |
20120243654 | Methods for Interrupted Counting of Particles in Cells - A method executed by a circuit for counting electrons in storage cells in an array of at least two storage cells is provided. The method includes providing a storage array of at least two storage cells, and each of said at least two storage cells containing an unknown amount of electrons. A receiving array of at least two receiving cells is provided, where said at least two receiving cells initially contain no electrons. Then, extracting a layer of said electrons from said storage array of cells and inserting said layer into corresponding locations in said receiving array. The method then repeats said steps of extracting and inserting while at least one of said at least two storage cells is not empty. The method counts, for each said storage cell in said storage array, a productive-extraction amount. | 09-27-2012 |
20130024605 | SYSTEMS AND METHODS OF STORING DATA - A method of writing data is performed in a data storage device with a controller and a memory. The memory includes latches and multiple storage elements and is operative to store a first number of bits in each storage element according to a first mapping of sequences of bits to states of the storage elements. The method includes loading data bits into the latches within the memory and generating manipulated data bits in the latches by manipulating designated data bits in the latches using one or more logical operations. The method also includes storing sets of the manipulated data bits to respective storage elements of the group of storage elements according to the first mapping. The designated data bits correspond to states of the respective storage elements according to a second mapping of sequences of bits to states. The second mapping is different than the first mapping. | 01-24-2013 |
20130067151 | METHOD FOR EFFICIENT STORAGE OF METADATA IN FLASH MEMORY - A method includes writing a first portion of received user data to a first page of a block of a memory according to a writing schedule and writing a subsequent portion of the received user data to another page of the block according to the writing schedule. The method includes storing first metadata corresponding to writing the first portion in the memory. The method further includes associating the first metadata with the subsequent portion. | 03-14-2013 |
20130111113 | NAND Flash Memory Controller Exporting a NAND Interface | 05-02-2013 |
20130191580 | Controller, System, and Method for Mapping Logical Sector Addresses to Physical Addresses - A controller of a flash memory device exchanges data pages with the memory device via a host-type NAND interface and exchanges data sectors with a host via a flash-type NAND interface. The data sectors are different in size than the data pages. A data storage system includes the controller and the memory device. Another data storage system includes a memory whose physical pages have a common size and circuitry for exporting a flash-type NAND interface for exchanging data sectors, that differ in size from the physical pages, with a host. A data processing system includes the data storage system and the host. | 07-25-2013 |
20140160248 | HEAD MOUNTABLE CAMERA SYSTEM - Head mountable camera devices, systems, and methods are disclosed. | 06-12-2014 |
20140160250 | HEAD MOUNTABLE CAMERA SYSTEM - Head mountable camera devices, systems, and methods are disclosed. | 06-12-2014 |
20140269050 | DETERMINING READ VOLTAGES FOR READING MEMORY - A method of reading data at a data storage device that includes a non-volatile memory having a three-dimensional (3D) configuration includes identifying a first set of storage elements of a first word line of the non-volatile memory that satisfy a condition. The condition is based on one or more states of one or more storage elements. The method includes determining a first read voltage corresponding to the first set of storage elements of the first word line and determining a second read voltage corresponding to a second set of storage elements of the first word line that do not satisfy the condition. The method includes reading data from the first word line by applying the first read voltage to the first set of storage elements of the first word line and applying the second read voltage to the second set of storage elements of the first word line. | 09-18-2014 |
20140269085 | DETERMINING READ VOLTAGES FOR READING MEMORY - A method of reading data at a data storage device that includes a non-volatile memory includes identifying a first set of storage elements of a first word line of the non-volatile memory that satisfy a condition. The condition is based on one or more states of one or more storage elements. The method includes determining a first read voltage corresponding to the first set of storage elements of the first word line and determining a second read voltage corresponding to a second set of storage elements of the first word line that do not satisfy the condition. The method includes reading data from the first word line by applying the first read voltage to the first set of storage elements of the first word line and applying the second read voltage to the second set of storage elements of the first word line. | 09-18-2014 |
20140269086 | SYSTEM AND METHOD OF ACCESSING MEMORY OF A DATA STORAGE DEVICE - Flash memory devices and methods of reading data from flash memory devices reduce an overall number of sensing operations when data is to be read from one word line in accordance with one or more flags set according to data read from another word line. | 09-18-2014 |
20140376297 | DATA ENCODING FOR NON-VOLATILE MEMORY - A data storage device includes a memory and a controller. Mapping circuitry is configured to apply a mapping to received data to generate mapped data to be stored in storage elements. The mapping is configured to reduce average write time by mapping at least one incoming data value into a mapped value such that no transitions of storage elements from a second state to a first state are used for storing the mapped value into the storage elements. | 12-25-2014 |
20140376298 | DATA ENCODING FOR NON-VOLATILE MEMORY - A data storage device includes a memory and a controller. Mapping circuitry is configured to apply a mapping to received data to generate mapped data to be stored in storage elements. The mapping is configured to reduce average write time by mapping at least one incoming data value into a mapped value such that no transitions of storage elements from a second state to a first state are used for storing the mapped value into the storage elements. The mapping of the received data to the mapped data does not depend on the states of the storage elements prior to the writing of the mapped data. | 12-25-2014 |
20140379961 | DATA ENCODING FOR NON-VOLATILE MEMORY - A data storage device includes a memory and a controller. Mapping circuitry is configured to apply a mapping to received data to generate mapped data to be stored into the memory. The mapping is configured to reduce an average number of state changes of storage elements per write operation and is independent of the states of the storage elements prior to the writing of the mapped data. | 12-25-2014 |
20140379962 | DATA ENCODING FOR NON-VOLATILE MEMORY - A data storage device includes a memory and a controller. Mapping circuitry is configured to apply a mapping to received data to generate mapped data to be stored into the memory. The mapping is configured to increase average reliability by reducing an average number of state changes of storage elements per write operation and to reduce average write time by reducing a number of operations for storing the mapped value into the storage elements. | 12-25-2014 |
20140380015 | DATA ENCODING FOR NON-VOLATILE MEMORY - A data storage device includes a memory and a controller. Mapping circuitry is configured to apply a mapping to received data to generate mapped data to be stored into the memory. The mapping is configured to reduce an average number of state changes of storage elements per write operation. | 12-25-2014 |
20150058528 | RELOCATING DATA BASED ON MATCHING ADDRESS SEQUENCES - A data storage device includes a non-volatile memory and a controller. The controller is configured to store a first sequence of addresses based on a first sequence of read instructions received from a host device. Subsequent to storing the first sequence of addresses, the controller is configured to receive a second sequence of read instructions from the host device and to determine whether a second sequence of addresses that is based on the second sequence of read instructions matches the first sequence of addresses. The controller is configured to relocate at least one page of the non-volatile memory at least partially based on the second sequence of addresses matching the first sequence of addresses. | 02-26-2015 |
20150058535 | RELOCATING DATA BASED ON MATCHING ADDRESS SEQUENCES - A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory. A controller of the data storage device is configured to store a first sequence of addresses based on a first sequence of read instructions received from a host device. Subsequent to storing the first sequence of addresses, the controller is configured to receive a second sequence of read instructions from the host device and to determine whether a second sequence of addresses that is based on the second sequence of read instructions matches the first sequence of addresses. The controller is configured to relocate at least one page of the non-volatile memory at least partially based on the second sequence of addresses matching the first sequence of addresses. | 02-26-2015 |