Cavanna
Antonella Cavanna, Villiers Sur Orge FR
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20130277715 | Semiconductor Heterostructure and Transistor of HEMT Type, in Particular for Low-Frequency Low-Noise Cryogenic Applications. - A semiconductor heterostructure having: a substrate (SS); a buffer layer (h); a spacer layer (d, e, f); a barrier layer (b, c); and which may also include a cover layer (a) is provided. The barrier layer is doped (DS); and the barrier and spacer layers are made of one or more semiconductors having wider bandgaps than the one or more materials forming the buffer layer, the heterostructure being characterized in that: the barrier layer comprises a first barrier sublayer (c) in contact with the spacer layer, and a second barrier sublayer (b), distant from the spacer layer; and in that the second barrier sublayer has a wider bandgap than the first barrier sublayer. The invention also relates to a HEMT transistor produced using such a heterostructure and to the use of such a transistor at cryogenic temperatures. | 10-24-2013 |
Carlos Cavanna, Toronto CA
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20110113223 | BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS - Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed. | 05-12-2011 |
20140059331 | BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS - Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed. | 02-27-2014 |
20140059332 | BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS - Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction. | 02-27-2014 |
Javier Cavanna, Munro AR
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20080284548 | Method for Sectioning With a Section Switch a Medium-Voltage Electric Power Distribution Line Exhibiting a Disturbance, Section Switch for Medium-Voltage Electric Power Distribution Line Applicable Thereon and Electronic Circuit for Detecting a Fault Current and Comprised by Said Section Switch - The present invention discloses a method for sectioning a medium-voltage distribution electric line evidencing a disturbance, wherein said method comprises the stages of: (a) evaluating a current in a medium-voltage line with a detection coil; (b) converting the intensity generated by said current by the detection coil in a potential difference, further transferring the information to a microprocessor; (c) analyzing the profile of the wave generated by the current by an algorithm to analyze harmonic levels by Fourier Series, and (d) determining the behavior or the section switch from the result obtained in (c). Step d) comprises making no count to trigger the disconnection mechanism (i) when the current value does not exceed a predetermined value for which said current is detected as a fault current; (ii) when el the wave profile corresponds to a transformer input current or in-rush current; or (iii) making a count to trigger the disconnection mechanism when the wave profile corresponds to a short-circuit exceeding the predetermined current value as fault current. Given the case of d) (ii) the method further comprises step e) comprising: (i) not triggering the disconnection mechanism when a transient fault is involved; or either, (ii) triggering the disconnection mechanism when the predetermined count number is reached. The method can simultaneously with e) ii) further comprise f) sending a RF signal to other or others parallel connected section switches at a point of the distribution line in order to be jointly disconnected. The invention also refers to section switches for electric power distribution lines for auxiliary branches where the main fine is protected by an automatic reset circuit breaker, which comprises an electronic circuit with a microcontroller capable of distinguishing a permanent fault current from a transient fault current, thereby immunizing the section switch against “in-rush” currents; and to said electronic circuit. | 11-20-2008 |
Jorge Cavanna, Munro AR
Patent application number | Description | Published |
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20080284548 | Method for Sectioning With a Section Switch a Medium-Voltage Electric Power Distribution Line Exhibiting a Disturbance, Section Switch for Medium-Voltage Electric Power Distribution Line Applicable Thereon and Electronic Circuit for Detecting a Fault Current and Comprised by Said Section Switch - The present invention discloses a method for sectioning a medium-voltage distribution electric line evidencing a disturbance, wherein said method comprises the stages of: (a) evaluating a current in a medium-voltage line with a detection coil; (b) converting the intensity generated by said current by the detection coil in a potential difference, further transferring the information to a microprocessor; (c) analyzing the profile of the wave generated by the current by an algorithm to analyze harmonic levels by Fourier Series, and (d) determining the behavior or the section switch from the result obtained in (c). Step d) comprises making no count to trigger the disconnection mechanism (i) when the current value does not exceed a predetermined value for which said current is detected as a fault current; (ii) when el the wave profile corresponds to a transformer input current or in-rush current; or (iii) making a count to trigger the disconnection mechanism when the wave profile corresponds to a short-circuit exceeding the predetermined current value as fault current. Given the case of d) (ii) the method further comprises step e) comprising: (i) not triggering the disconnection mechanism when a transient fault is involved; or either, (ii) triggering the disconnection mechanism when the predetermined count number is reached. The method can simultaneously with e) ii) further comprise f) sending a RF signal to other or others parallel connected section switches at a point of the distribution line in order to be jointly disconnected. The invention also refers to section switches for electric power distribution lines for auxiliary branches where the main fine is protected by an automatic reset circuit breaker, which comprises an electronic circuit with a microcontroller capable of distinguishing a permanent fault current from a transient fault current, thereby immunizing the section switch against “in-rush” currents; and to said electronic circuit. | 11-20-2008 |
Vicente V. Cavanna, Roseville, CA US
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20090003229 | Adaptive Bandwidth Management Systems And Methods - Adaptive bandwidth management systems and methods are disclosed. An exemplary system comprises a network switching device including a plurality of physical ports and at least one switching fabric for managing connections between the physical ports. The system also includes a management processor operatively associated with the plurality of physical ports and the at least one switching fabric. The system also includes program code stored in computer-readable storage and executable by the management processor, the program code configuring the network switching device to conserve electrical energy based on the current bandwidth requirements. | 01-01-2009 |
Vincent E Cavanna, Loomis, CA US
Patent application number | Description | Published |
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20140098810 | FABRIC CHIP HAVING A PORT RESOLUTION MODULE - A fabric chip includes a plurality of port interfaces, wherein each of the plurality of port interfaces includes a network chip interface (NCI) block having a port resolution module, and wherein the port resolution module is to determine which of the port interfaces is to receive a packet from the NCI block, and a crossbar block communicatively coupled with each of the NCI blocks in the plurality of port interfaces. | 04-10-2014 |
20140112125 | Fabric Chip Having Trunked Links - A fabric chip includes a plurality of port interfaces, in which each of the plurality of port interfaces includes a network chip interface (NCI) block having a port resolution module to determine which of the port interfaces is to receive a packet from the NCI block and a crossbar block communicatively coupled with each of the NCI blocks in the plurality of port interfaces. In addition, at least two of the plurality of port interfaces are to be connected to at least two port interfaces of another fabric chip as trunked links of a trunk. Moreover, the NCI blocks of the at least two of the plurality of port interfaces include a resource that keeps track of the port interfaces in the fabric chip that are connected to the trunk links of the trunk. | 04-24-2014 |
20140198631 | MANAGING A SWITCH FABRIC - In a method for managing a switch fabric comprising a plurality of fabric chips, each of said plurality of fabric chips comprising a plurality of port interfaces, a first configuration set and a second configuration set, each comprising a plurality of configuration registers for the port interfaces to use in calculating a port resolution for an incoming packet, are generated. In addition, a determination as to which of the first configuration set and the second configuration set the plurality of fabric chips are to use is made an instruction is communicated to each of the fabric chips to use the determined one of the first configuration set and the second configuration set. | 07-17-2014 |
20140211609 | IMPLEMENTING A SWITCH FABRIC RESPONSIVE TO AN UNAVAILABLE PATH - In a method for implementing a switch fabric, in a first fabric chip, a packet comprising an identification of a destination node chip is received from a source fabric chip, and a determination that a first path in the switch fabric along which the packet is to be communicated toward the destination node chip is unavailable is made. In addition, a determination as to whether another path along which the packet is to be communicated toward the destination node chip that does not include the source fabric chip is available is made. In response to a determination that the another path is available, the packet is communicated along the another path. In addition, in response to a determination that the another path is unavailable, the packet is communicated back to the source fabric chip. | 07-31-2014 |
20140211630 | MANAGING PACKET FLOW IN A SWITCH FARIC - In a method for managing packet flow in a switch fabric comprising a plurality of fabric chips, wherein a packet comprises a counter, a determination as to whether the packet has been detoured around an unavailable fabric link and a determination as to whether the packet is making forward progress are made. In addition, a value of the counter in the packet is modified in response to a determination that the packet has been detoured around an unavailable fabric link and a determination that forward progress is not being made. | 07-31-2014 |
Vincent E. Cavanna, Rocklin, CA US
Patent application number | Description | Published |
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20080301362 | Content addressable memory address resolver - Systems, devices, and methods, including executable instructions are provided for resolving content addressable memory (CAM) match address priority. One method includes retaining a first match address as the best match address. Subsequent match addresses are compared to the retained best match address, each match address being associated with a compare cycle during which a selected columnar portion of each CAM entry is compared to a corresponding portion of a search term. The best match address is updated as a result of the comparison. | 12-04-2008 |