Patent application number | Description | Published |
20080283959 | Tapered through-silicon via structure - An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV. | 11-20-2008 |
20080296763 | Multi-Die Wafer Level Packaging - A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration. | 12-04-2008 |
20090263214 | FIXTURE FOR P-THROUGH SILICON VIA ASSEMBLY - A silicon-based wafer such as a TSV interposer wafer having a first and second surfaces wherein a glass carrier is mounted on the second surface by a UV tape is held by a vacuum holder applied on the first surface and the glass carrier is removed from the silicon-based wafer by irradiating the UV tape with a UV light through the glass carrier. The silicon-based wafer is then flipped and placed onto a vacuum plate and secured to the vacuum plate by applying vacuum to the vacuum plate. The vacuum holder is then released from the silicon-based wafer leaving the silicon-based wafer secured to the vacuum plate for subsequent processing steps. | 10-22-2009 |
20090269905 | Tapered Through-Silicon Via Structure - An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV. | 10-29-2009 |
20090321948 | METHOD FOR STACKING DEVICES - A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process. | 12-31-2009 |
20100032843 | Through Silicon Via Layout - A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die. | 02-11-2010 |
20100047963 | Through Silicon Via Bonding Structure - System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate. | 02-25-2010 |
20100084747 | Zigzag Pattern for TSV Copper Adhesion - A system and method for forming a TSV contact is presented. A preferred embodiment includes a TSV in contact with a portion of the uppermost metal layer of a semiconductor die. The interface between the TSV conductor and the contact pad is preferably characterized by a non-planar zigzag pattern that forms a grid pattern of contacts. Alternatively, the contacts may form a plurality of metal lines that make contact with the contact pad. | 04-08-2010 |
20100090304 | BONDING PROCESS FOR CMOS IMAGE SENSOR - The present disclosure provides a method of making an integrated circuit (IC). The method includes forming an electric device on a front side of a substrate; forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device; forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer; forming an opening in the passivation layer, exposing the top metal pad; forming a deep trench in the substrate; filling a conductive material in the deep trench and the opening, resulting in a though-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature; and applying a polishing process to remove excessive conductive material, forming a substantially planar surface. | 04-15-2010 |
20100090318 | Backside Connection to TSVs Having Redistribution Lines - An integrated circuit structure includes a semiconductor substrate including a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, and has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is over the backside of the semiconductor substrate and connected to the back end of the TSV. The integrated circuit structure further includes a passivation layer over the RDL; an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening; and a nickel layer in the opening and contacting the RDL. | 04-15-2010 |
20100090319 | Bond Pad Connection to Redistribution Lines Having Tapered Profiles - An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL. | 04-15-2010 |
20100102453 | Three-Dimensional Integrated Circuit Stacking-Joint Interface Structure - A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV. | 04-29-2010 |
20100117201 | Cooling Channels in 3DIC Stacks - An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through. | 05-13-2010 |
20100140805 | Bump Structure for Stacked Dies - A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board. | 06-10-2010 |
20100144094 | Method of Forming Stacked Dies - The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to metallization processing. TSVs may be fabricated with increased aspect ratio, extending deeper in a wafer substrate. The method generally reduces the risk of overly-thinning a wafer substrate in a wafer back-side grinding process typically used to expose and make electrical contacts to the TSVs. By providing deeper TSVs and bonding pads, individual wafers and dies may be bonded directly between the TSVs and bonding pads on an additional wafer. | 06-10-2010 |
20100171197 | Isolation Structure for Stacked Dies - An isolation structure for stacked dies is provided. A through-silicon via is formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon via. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon via. The isolation film is thinned to re-expose the through-silicon via, and conductive elements are formed on the through-silicon via. The conductive element may be, for example, a solder ball or a conductive pad. The conductive pad may be formed by depositing a seed layer and an overlying mask layer. The conductive pad is formed on the exposed seed layer. Thereafter, the mask layer and the unused seed layer may be removed. | 07-08-2010 |
20100171223 | Through-Silicon Via With Scalloped Sidewalls - A semiconductor device having one or more through-silicon vias (TSVs) is provided. The TSVs are formed such that sidewalls of the TSVs have a scalloped surface. In an embodiment, the sidewalls of the TSVs are sloped wherein a top and bottom of the TSVs have different dimensions. The TSVs may have a V-shape wherein the TSVs have a wider dimension on a circuit side of the substrate, or an inverted V-shape wherein the TSVs have a wider dimension on a backside of the substrate. The scalloped surfaces of the sidewalls and/or sloped sidewalls allow the TSVs to be more easily filled with a conductive material such as copper. | 07-08-2010 |
20100174858 | EXTRA HIGH BANDWIDTH MEMORY DIE STACK - A system includes a central processing unit (CPU); a memory device in communication with the CPU, and a direct memory access (DMA) controller in communication with the CPU and the memory device. The memory device includes a plurality of vertically stacked chips and a plurality of input/output (I/O) ports. Each of the I/O ports connected to at least one of the plurality of chips through a through silicon via. The DMA controller is configured to manage to transfer of data to and from the memory device. | 07-08-2010 |
20100276787 | Wafer Backside Structures Having Copper Pillars - An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL. | 11-04-2010 |
20100279463 | METHOD OF FORMING STACKED-DIE PACKAGES - A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer. | 11-04-2010 |
20100330788 | THIN WAFER HANDLING STRUCTURE AND METHOD - A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer. | 12-30-2010 |
20100330798 | Formation of TSV Backside Interconnects by Modifying Carrier Wafers - An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×10 | 12-30-2010 |
20110006416 | STRUCTURE AND METHOD FOR FORMING PILLAR BUMP STRUCTURE HAVING SIDEWALL PROTECTION - A method for forming a metal pillar bump structure is provided. In one embodiment, a passivation layer is formed over a semiconductor substrate and a conductive layer is formed over the passivation layer. A patterned and etched photoresist layer is provided above the conductive layer, the photoresist layer defining at least one opening therein. A metal layer is deposited in the at least one opening. Portions of the photoresist layer are etched along one or more interfaces between the photoresist layer and the metal layer to form cavities. A solder material is deposited in the at least one opening, the solder material filling the cavities and a portion of the opening above the metal layer. The remaining photoresist layer and the conductive layer not formed under the copper layer are removed. The solder material is then reflown to encapsulate the metal layer. | 01-13-2011 |
20110049706 | Front Side Copper Post Joint Structure for Temporary Bond in TSV Application - An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via. | 03-03-2011 |
20110095436 | THROUGH SILICON VIA WITH DUMMY STRUCTURE AND METHOD FOR FORMING THE SAME - A through silicon via structure includes a top pad and a vertical conductive post that is connected to the top pad. The top pad covers a wider area than the cross section of the vertical conductive post. An interconnect pad is formed at least partially below the top pad. An under layer is also formed at least partially below the top pad. At least one dummy structure connects the top pad and the under layer to fasten the top pad and the interconnect pad. | 04-28-2011 |
20110101519 | Robust Joint Structure for Flip-Chip Bonding - An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a copper bump at a main surface of the first work piece and having a first dimension; and a nickel-containing barrier layer over and adjoining the copper bump. The second work piece is bonded to the first work piece and includes a bond pad at a main surface of the second work piece; and a solder mask at the main surface of the second work piece and having a solder resist opening with a second dimension exposing a portion of the bond pad. A ratio of the first dimension to the second dimension is greater than about 1. Further, a solder region electrically connects the copper bump to the bond pad, with a vertical distance between the bond pad and the copper bump being greater than about 30 μm. | 05-05-2011 |
20110101526 | Copper Bump Joint Structures with Improved Crack Resistance - An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium. | 05-05-2011 |
20110165776 | Bond Pad Connection to Redistribution Lines Having Tapered Profiles - An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL. | 07-07-2011 |
20110175220 | SEMICONDUCTOR DEVICE HAVING CONDUCTIVE PADS AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes at least two conductive pads, one of the conductive pads being formed above another of the at least two conductive pads, and a redistribution layer extending from at least one of the conductive pads. The semiconductor device also includes a bump structure formed over the conductive pads and electrically coupled to the conductive pads. | 07-21-2011 |
20110186986 | T-Shaped Post for Semiconductor Devices - A T-shaped post for semiconductor devices is provided. The T-shaped post has an under-bump metallization (UBM) section and a pillar section extending from the UBM section. The UBM section and the pillar section may be formed of a same material or different materials. In an embodiment, a substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like, having T-shaped posts is attached to a contact of another substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like. The T-shaped posts may have a solder material pre-formed on the pillar section such that the pillar section is exposed or such that the pillar section is covered by the solder material. In another embodiment, the T-shaped posts may be formed on one substrate and the solder material formed on the other substrate. | 08-04-2011 |
20110186988 | Multi-Direction Design for Bump Pad Structures - An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction. | 08-04-2011 |
20110193220 | Pillar Structure having a Non-Planar Surface for Semiconductor Devices - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 08-11-2011 |
20110193227 | Methods and Apparatus for Robust Flip Chip Interconnections - Apparatus and methods for providing a robust solder connection in a flip chip arrangement using lead free solder are disclosed. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of a material comprising one of nickel, nickel alloys, palladium, platinum, cobalt, silver, gold, and alloys of these is formed on the exterior surface of the copper column. A lead free solder connector is disposed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. A thermal reflow is performed. The metal finish may be of nickel, nickel alloy and nickel based materials. Following a thermal reflow, the solder connection formed between the copper terminal column and the metal finish solder pad is less than 0.5 wt. %. | 08-11-2011 |
20110193232 | CONDUCTIVE PILLAR STRUCTURE FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - A conductive pillar structure for a die includes a passivation layer having a metal contact opening over a substrate. A bond pad has a first portion inside the metal contact opening and a second portion overlying the passivation layer. The second portion of the bond pad has a first width. A buffer layer over the bond pad has a pillar contact opening with a second width to expose a portion of the bond pad. A conductive pillar has a first portion inside the pillar contact opening and a second portion over the buffer layer. The second portion of the conductive pillar has a third width. A ratio of the second width to the first width is between about 0.35 and about 0.65. A ratio of the second width to the third width is between about 0.35 and about 0.65. | 08-11-2011 |
20110217841 | METHOD OF FORMING THROUGH SILICON VIA WITH DUMMY STRUCTURE - A method of forming a through silicon via (TSV) structure includes forming an interconnect pad over a substrate. An under layer is formed over the interconnect pad. A vertical conductive post is formed at least partially through the substrate. At least one dummy structure is formed at least partially through the under layer. A top pad is formed over the dummy structure and the vertical conductive post. The top pad covers a wider area than a cross section of the vertical conductive post. The interconnect pad is electrically connected to the top pad. The dummy structure connects the top pad and the under layer thereby fastening the top pad and the interconnect pad. | 09-08-2011 |
20110227216 | Under-Bump Metallization Structure for Semiconductor Devices - An under-bump metallization (UBM) structure for a semiconductor device is provided. A passivation layer is formed over a contact pad such that at least a portion of the contact pad is exposed. A protective layer, such as a polyimide layer, may be formed over the passivation layer. The UBM structure, such as a conductive pillar, is formed over the underlying contact pad such that the underlying contact pad extends laterally past the UBM structure by a distance large enough to prevent or reduce cracking of the passivation layer and or protective layer. | 09-22-2011 |
20110241202 | Dummy Metal Design for Packaging Structures - An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad. | 10-06-2011 |
20110285013 | Controlling Solder Bump Profiles by Increasing Heights of Solder Resists - A device includes a first work piece bonded to a second work piece. The first work piece includes a solder resist at a surface of the first work piece, wherein the solder resist includes a solder resist opening, and a bond pad in the solder resist opening. The second work piece includes a non-reflowable metal bump at a surface of the second work piece. A solder bump bonds the non-reflowable metal bump to the bond pad, with at least a portion of the solder bump located in the solder resist opening and adjoining the non-reflowable metal bump and the bond pad. A thickness of the solder resist is greater than about 50 percent a height of the solder bump, wherein the height equals a distance between the non-reflowable metal bump and the bond pad. | 11-24-2011 |
20110285023 | Substrate Interconnections having Different Sizes - A bump structure that may be used to interconnect one substrate to another substrate is provided. A conductive pillar is formed on a first substrate such that the conductive pillar has a width different than a contact surface on a second substrate. In an embodiment the conductive pillar of the first substrate has a trapezoidal shape or a shape having tapered sidewalls, thereby providing a conductive pillar having base portion wider than a tip portion. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like. | 11-24-2011 |
20110291262 | Strength of Micro-Bump Joints - A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface. | 12-01-2011 |
20120012985 | Substrate Stand-Offs for Semiconductor Devices - Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars. | 01-19-2012 |
20120012997 | Recessed Pillar Structure - A bump structure that may be used to interconnect one substrate to another substrate is provided. A recessed conductive pillar is formed on a first substrate such that the recessed conductive pillar has a recess formed therein. The recess may be filled with a solder material. A conductive pillar on a second substrate may be formed having a contact surface with a width less than or equal to a width of the recess. The first substrate may be attached to the second substrate such that the conductive pillar on the second substrate is positioned over or in the recess of the first substrate. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like. | 01-19-2012 |
20120040524 | PROCESS FOR MAKING CONDUCTIVE POST WITH FOOTING PROFILE - A process for making a copper post with footing profile employs dual photoresist films of different photosensitivities and thicknesses on an under-bump-metallurgy (UBM) layer. After an exposure lithography process, a first opening with a substantially vertical sidewall is formed in a first photoresist film, and a second opening with a sloped sidewall is formed in a second photoresist film. The second opening has a top diameter and a bottom diameter greater than the top diameter, and the bottom diameter is greater than the diameter of the first opening. A conductive layer is then formed in the first opening and the second opening followed by removing the dual photoresist films. | 02-16-2012 |
20120119354 | Protecting Flip-Chip Package using Pre-Applied Fillet - A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials. | 05-17-2012 |
20120178252 | Dummy Metal Design for Packaging Structures - A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern. | 07-12-2012 |
20120199966 | Elongated Bump Structure for Semiconductor Devices - An elongated bump structure for semiconductor devices is provided. An uppermost protective layer has an opening formed therethrough. A pillar is formed within the opening and extending over at least a portion of the uppermost protective layer. The portion extending over the uppermost protective layer exhibits a generally elongated shape. In an embodiment, the position of the opening relative to the portion of the bump structure extending over the uppermost protective layer is such that a ratio of a distance from an edge of the opening to an edge of the bump is greater than or equal to about 0.2. In another embodiment, the position of the opening is offset relative to center of the bump. | 08-09-2012 |
20120270369 | Methods for Lead Free Solder Interconnections for Integrated Circuits - Methods for forming lead free solder interconnections for integrated circuits. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of material is formed on the input/output terminal of the integrated circuit. A lead free solder connector is formed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. An intermetallic compound is formed at the interface between the cap layer and the lead free solder connector. A solder connection is formed between input/output terminal of the integrated circuit and the metal finish pad that is less than 0.5 weight percent copper, and the intermetallic compound is substantially free of copper. | 10-25-2012 |
20120329264 | Reflow System and Method for Conductive Connections - A system and method for forming conductive connections is disclosed. An embodiment comprises forming conductive material on to contacts of a semiconductor substrate. The semiconductor substrate is then inverter such that the conductive material is beneath the semiconductor substrate, and the conductive material is reflowed to form a conductive bump. The reflow is performed using gravity in order to form a more uniform shape for the conductive bump. | 12-27-2012 |
20130009303 | Connecting Function Chips To A Package To Form Package-On-Package - A package-on-package (PoP) comprises a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of bond-on-trace connections, and a second function chip on top of the first function chip, directly connected to the substrate. Another package-on-package (PoP) comprises: a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of solder mask defined (SMD) connections formed on SMD bonding pads connected to solder bumps, and a second function chip on top of the first function chip, directly connected to the substrate by a plurality of bond-on-trace connections. | 01-10-2013 |
20130026614 | STRUCTURE AND METHOD FOR BUMP TO LANDING TRACE RATIO - The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T. | 01-31-2013 |
20130026619 | BUMP STRUCTURES - The embodiments of bump and bump-on-trace (BOT) structures provide bumps with recess regions for reflowed solder to fill. The recess regions are placed in areas of the bumps where reflow solder is most likely to protrude. The recess regions reduce the risk of bump to trace shorting. As a result, yield can be improved. | 01-31-2013 |
20130026622 | BUMP STRUCTURES IN SEMICONDUCTOR DEVICE AND PACKAGING ASSEMBLY - A bump structure in a semiconductor device or a packing assembly includes an under-bump metallization (UBM) layer formed on a conductive pad of a semiconductor substrate. The UBM layer has a width greater than a width of the conductive pad. | 01-31-2013 |
20130032923 | Integrated Inductor - A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization. | 02-07-2013 |
20130040453 | Through Silicon Via Layout - A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die. | 02-14-2013 |
20130043583 | Dummy Flip Chip Bumps for Reducing Stress - A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. | 02-21-2013 |
20130056869 | PILLAR STRUCTURE HAVING A NON-PLANAR SURFACE FOR SEMICONDUCTOR DEVICES - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 03-07-2013 |
20130056872 | Packaging and Function Tests for Package-on-Package and System-in-Package Structures - A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls. | 03-07-2013 |
20130062741 | Semiconductor Devices and Methods of Manufacturing and Packaging Thereof - Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation. | 03-14-2013 |
20130062755 | ELONGATED BUMP STRUCTURE IN SEMICONDUCTOR DEVICE - A device includes a chip attached to a substrate. The chip includes a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a conductive trace and a mask layer overlying the conductive trace, wherein the mask layer has an opening exposing a portion of the conductive trace. An interconnection is formed between the conductive pillar and the exposed portion of the conductive trace. The opening has a first dimension (d | 03-14-2013 |
20130075872 | Metal Pad Structures in Dies - A die includes a substrate, a metal pad over the substrate, and a passivation layer that has a portion over the metal pad. A dummy pattern is disposed adjacent to the metal pad. The dummy pattern is level with, and is formed of a same material as, the metal pad. The dummy pattern forms at least a partial ring surrounding at least a third of the metal pad. | 03-28-2013 |
20130093075 | Semiconductor Device Package and Method - An embodiment is a structure. The structure comprises a substrate, a chip, and a reinforcement component. The substrate has a first surface, and the first surface comprises depressions. The chip is over and attached to the first surface of the substrate. The reinforcement component is over a first area of the first surface of the substrate. The first area is not under the chip. The reinforcement component has a portion disposed in at least some of the depressions in the first area. | 04-18-2013 |
20130093079 | Connector Structures of Integrated Circuits - A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad. | 04-18-2013 |
20130119539 | Package Structures and Methods for Forming the Same - A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface. | 05-16-2013 |
20130134563 | Electrical Connection Structure - A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer. | 05-30-2013 |
20130147030 | Landing Areas of Bonding Structures - A device includes a first and a second package component. A metal trace is disposed on a surface of the first package component. The metal trace has a lengthwise direction. The metal trace includes a portion having an edge, wherein the edge is not parallel to the lengthwise direction of the metal trace. The second package component includes a metal pillar, wherein the second package component is disposed over the first package component. A solder region bonds the metal pillar to the metal trace, wherein the solder region contacts a top surface and the edge of the portion of the metal trace. | 06-13-2013 |
20130181325 | Through-Assembly Via Modules and Methods for Forming the Same - A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias. | 07-18-2013 |
20130182402 | PoP Structures Including Through-Assembly Via Modules - A device includes a Through-Assembly Via (TAV) Module, which includes a substrate, a plurality of through-vias penetrating through the substrate, and a second plurality of metal posts at a bottom surface of the TAV module and electrically coupled to the plurality of through-vias. A polymer includes a first portion between and contacting sidewalls of the first package component and the TAV module, a second portion disposed between the first plurality of metal posts, and a third portion disposed between the second plurality of metal posts. A first plurality of Redistribution Lines (RDLs) is underlying a bottom surface of the second and the third portions of the polymer. A second plurality of RDLs is over the first package component and the TAV module. The first plurality of RDLs is electrically coupled to the second plurality of RDLs through the plurality of through-vias in the TAV module. | 07-18-2013 |
20130241052 | Methods and Apparatus for Solder on Slot Connections in Package on Package Structures - Solder on slot connections in package on package structures. An apparatus includes a substrate having a front side surface and a back side surface; a first passivation layer disposed over at least one of the front side and back side surfaces; at least one via opening formed in the first passivation layer; a conductor layer disposed over the first passivation layer, coupled to the at least one via and forming a conductive trace on the surface of the first passivation layer; a second passivation layer formed over the conductor layer; and at least one slot opening formed in the second passivation layer and exposing a portion of the conductive trace for receiving a solder connector. In additional embodiments the substrate may be a semiconductor wafer. Methods for forming the structures are disclosed. | 09-19-2013 |
20130249091 | Multi-Direction Design for Bump Pad Structures - An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction. | 09-26-2013 |
20130256836 | Package-on-Package (PoP) Device with Integrated Passive Device - A package for a use in a package-on-package (PoP) device. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor. | 10-03-2013 |
20130256874 | Elongated Bumps in Integrated Circuit Devices - A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 μm. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer. | 10-03-2013 |
20130270682 | Methods and Apparatus for Package on Package Devices with Reversed Stud Bump Through Via Interconnections - Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed. | 10-17-2013 |
20130270693 | Trace Layout Method in Bump-on-Trace Structures - A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components. | 10-17-2013 |
20130270699 | Conical-Shaped or Tier-Shaped Pillar Connections - A pillar structure for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled. | 10-17-2013 |
20130277830 | Bump-on-Trace Interconnect - Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance. | 10-24-2013 |
20130288473 | Electrical Connection Structure - A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer. | 10-31-2013 |
20130292827 | Pillar Structure having a Non-Planar Surface for Semiconductor Devices - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 11-07-2013 |
20130299992 | Bump Structure for Stacked Dies - A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board. | 11-14-2013 |
20130307140 | PACKAGING WITH INTERPOSER FRAME - The mechanisms of using an interposer frame to package a semiconductor die enables fan-out structures and reduces form factor for the packaged semiconductor die. The mechanisms involve using a molding compound to attach the semiconductor die to the interposer frame and forming a redistribution layer on one or both sides of the semiconductor die. The redistribution layer(s) in the package enables fan-out connections and formation of external connection structures. Conductive columns in the interposer frame assist in thermal management. | 11-21-2013 |
20130320524 | Design Scheme for Connector Site Spacing and Resulting Structures - A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. | 12-05-2013 |
20140021583 | PACKAGE STRUCTURES INCLUDING A CAPACITOR AND METHODS OF FORMING THE SAME - A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side. | 01-23-2014 |
20140027901 | PACKAGE-ON-PACKAGE STRUCTURES HAVING BUFFER DAMS AND METHODS FOR FORMING THE SAME - A device includes a device die and a plurality of metal posts at a surface of the device die and electrically coupled to the device die. The device further includes a plurality of through-assembly vias (TAVs), a dam member between the device die and the plurality of TAVs, and a polymer layer encompassing the device die, the plurality of metal posts, the plurality of TAVs, and the dam member. | 01-30-2014 |
20140035148 | Bump on Pad (BOP) Bonding structure - The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. | 02-06-2014 |
20140048929 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 02-20-2014 |
20140051244 | METHOD OF FORMING AN INTEGRATED CIRCUIT DEVICE - A method of forming an integrated circuit device includes forming an under-bump metallurgy (UBM) layer overlying a semiconductor substrate. Next, a first photoresist film is formed on the UBM layer where the first photoresist film has a first photosensitivity and a first thickness. Additionally, the method includes forming a second photoresist film on the first photoresist film. Next, the method includes performing an exposure process on the second photoresist film and the first photoresist film. The method further includes removing an exposed portion of the second photoresist film to form a first opening. The method further also includes removing an exposed portion of the first photoresist film to expose a portion of the UBM layer. Furthermore, the method includes forming a copper layer in the first opening. The method also includes removing the second photoresist film and the first photoresist film where the copper layer forms a copper post. | 02-20-2014 |
20140061937 | Fan-Out Package Comprising Bulk Metal - A device includes a polymer, a device die in the polymer, and a plurality of Through Assembly Vias (TAVs) extending from a top surface to a bottom surface of the polymer. A bulk metal feature is located in the polymer and having a top-view size greater than a top-view size of each of the plurality of TAVs. The bulk metal feature is electrically floating. The polymer, the device die, the plurality of TAVs, and the bulk metal feature are portions of a package. | 03-06-2014 |
20140070402 | Stress Reduction Apparatus - A structure comprises a plurality of connectors formed on a top surface of a first semiconductor die, a second semiconductor die formed on the first semiconductor die and coupled to the first semiconductor die through the plurality of connectors and a first dummy conductive plane formed between an edge of the first semiconductor die and the plurality of connectors, wherein an edge of the first dummy conductive plane and a first distance to neutral point (DNP) direction form a first angle, and wherein the first angle is less than or equal to 45 degrees. | 03-13-2014 |
20140070403 | Packaging Methods and Packaged Devices - Packaging methods and packaged devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes forming a first redistribution layer (RDL) over a carrier, and forming a plurality of through assembly vias (TAVs) over the first RDL. An integrated circuit die is coupled over the first RDL, and a molding compound is formed over the first RDL, the TAVs, and the integrated circuit die. A second RDL is formed over the molding compound, the TAVs, and the integrated circuit die. | 03-13-2014 |
20140070422 | Semiconductor Device with Discrete Blocks - A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers. | 03-13-2014 |
20140076617 | Passive Devices in Package-on-Package Structures and Methods for Forming the Same - A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs. | 03-20-2014 |
20140077358 | Bump Structure and Method of Forming Same - An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent. | 03-20-2014 |
20140077359 | Ladder Bump Structures and Methods of Making Same - An embodiment ladder bump structure includes an under bump metallurgy (UBM) feature supported by a substrate, a copper pillar mounted on the UBM feature, the copper pillar having a tapering curved profile, which has a larger bottom critical dimension (CD) than a top critical dimension (CD) in an embodiment, a metal cap mounted on the copper pillar, and a solder feature mounted on the metal cap. | 03-20-2014 |
20140077360 | Interconnection Structure and Method of Forming Same - An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion. | 03-20-2014 |
20140077365 | Metal Bump and Method of Manufacturing Same - An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width. | 03-20-2014 |
20140091471 | Apparatus and Method for a Component Package - A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure. | 04-03-2014 |
20140097532 | Thermally Enhanced Package-on-Package (PoP) - A method and structure for providing improved thermal management in multichip and package on package (PoP) applications. A first substrate attached to a second smaller substrate wherein the second substrate is encircled by a heat ring attached to the first substrate, the heat ring comprising heat conducting materials and efficient heat dissipating geometries. The first substrate comprises a heat generating chip and the second substrate comprises a heat sensitive chip. A method is presented providing the assembled structure with increased heat dissipation away from the heat sensitive chip. | 04-10-2014 |
20140103488 | POP Structures and Methods of Forming the Same - A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a Through Assembly Via (TAV) penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line. | 04-17-2014 |
20140103540 | Cooling Channels in 3DIC Stacks - An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through. | 04-17-2014 |
20140110847 | BUMP-ON-TRACE INTERCONNECTION STRUCTURE FOR FLIP-CHIP PACKAGES - A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding surface having a width W | 04-24-2014 |
20140117532 | Bump Interconnection Ratio for Robust CPI Window - The disclosure is directed to a device and method for manufacture thereof. The device includes a first workpiece bonded to a second workpiece by a bump interconnection structure. The bump interconnection structure allows for optimized packaging assembly yield and bond integrity. | 05-01-2014 |
20140117534 | Interconnection Structure - A structure comprises a first passivation layer formed over a substrate, a second passivation layer formed over the first passivation layer, wherein the second passivation layer includes a first opening with a first dimension, a bond pad embedded in the first passivation layer and the second passivation layer, a protection layer formed on the second passivation layer comprising a second opening with a second dimension, wherein the second dimension is greater than the first dimension and a connector formed on the bond pad. | 05-01-2014 |
20140124947 | Methods and Apparatus for Flip Chip Substrate with Guard Rings Outside of a Die Attach Region - Methods and apparatus for flip chip substrates with guard rings. An embodiment comprises a substrate core with a die attach region for attaching an integrated circuit die; at least one dielectric layer overlying a die side surface of the substrate core; and at least one guard ring formed adjacent a corner of the substrate core, the at least one guard ring comprising: a first trace overlying the dielectric layer having rectangular portions extending in two directions from the corner of the substrate core and in parallel to the edges of the substrate core; a second trace underlying the dielectric layer; and at least one via extending through the dielectric layer and coupling the first and second traces; wherein the first trace, the at least one via, and the second trace form a vertical via stack. Methods for forming the flip chip substrates with the guard rings are disclosed. | 05-08-2014 |
20140127857 | Carrier Wafers, Methods of Manufacture Thereof, and Packaging Methods - Carrier wafers, methods of manufacture thereof, and packaging methods are disclosed. In one embodiment, a carrier wafer includes a first glass layer. The carrier wafer includes a second glass layer coupled to the first glass layer. The first glass layer has a first coefficient of thermal expansion (CTE), and the second glass layer has a second CTE. | 05-08-2014 |
20140127866 | Package Structures Including a Capacitor and Methods of Forming the Same - A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side. | 05-08-2014 |
20140130962 | THIN WAFER HANDLING METHOD - A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer. | 05-15-2014 |
20140131858 | Warpage Control of Semiconductor Die Package - Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved. | 05-15-2014 |
20140131862 | SEMICONDUCTOR DEVICE HAVING CONDUCTIVE PADS AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a plurality of conductive pads formed in consecutive conductive layers, and a bump structure. The plurality of conductive pads is aligned and arranged one above another over the substrate. The plurality of conductive pads comprises a first conductive pad and a second conductive pad. The first conductive pad is above the second conductive pad. A redistribution layer extends the second conductive pad. The first conductive pad is not extended by a redistribution layer. The bump structure is formed directly on the first conductive pad and electrically coupled to the plurality of conductive pads. | 05-15-2014 |
20140131865 | Structure and Method for Bump to Landing Trace Ratio - The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T. | 05-15-2014 |
20140131894 | POP Structures with Air Gaps and Methods for Forming the Same - A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die. | 05-15-2014 |
20140159203 | Substrate Pad Structure - A structure comprises a first pad protruding over a top surface of a package substrate, wherein the first pad is of a first elongated shape, a second pad embedded in the package substrate, wherein the second pad is of a second elongated shape and a via coupled between the first pad and the second pad. | 06-12-2014 |
20140159232 | Apparatus and Method for Three Dimensional Integrated Circuits - A structure comprises a substrate comprising a plurality of traces on top of the substrate, a plurality of connectors formed on a top surface of a semiconductor die, wherein the semiconductor die is formed on the substrate and coupled to the substrate through the plurality of connectors and a dummy metal structure formed at a corner of a top surface of the substrate, wherein the dummy metal structure has two discontinuous sections. | 06-12-2014 |
20140167253 | Semiconductor Devices, Methods of Manufacture Thereof, and Packaged Semiconductor Devices - Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a semiconductor device includes a substrate and conductive traces disposed over the substrate. Each of the conductive traces has a bottom region proximate the substrate and a top region opposite the bottom region. The top region has a first width and the bottom region has a second width. The second width is greater than the first width. | 06-19-2014 |
20140185264 | METHODS AND APPARATUS FOR FORMING PACKAGE-ON-PACKAGES - Methods and apparatus are disclosed for a package or a package-on-package (PoP) device. An IC package or a PoP device may comprise an electrical path connecting a die and a decoupling capacitor, wherein the electrical path may have a width in a range from about 8 um to about 44 um and a length in a range from about 10 um to about 650 um. The decoupling capacitor and the die may be contained in a same package, or at different packages within a PoP device, connected by contact pads, redistribution layers (RDLs), and connectors. | 07-03-2014 |
20140186591 | Solder Mask Shape for BOT Laminate Packages - A device is provided. The device may comprise an integrated circuit package. The integrated circuit package may comprise a first layer and a solder mask. The first layer may comprise a top surface wherein the solder mask is disposed on the top surface of the first layer. The solder mask may comprise a vertical edge. The vertical edge may form an angle between the top surface of the first layer and the vertical edge of not less than 90 degrees. The angle may be not less than 120 degrees or not less than 150 degrees. | 07-03-2014 |
20140191390 | Metal Routing Architecture for Integrated Circuits - A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar. | 07-10-2014 |
20140191391 | ELONGATED BUMP STRUCTURES IN PACKAGE STRUCTURE - A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2. | 07-10-2014 |
20140210099 | Packaged Semiconductor Devices and Packaging Methods - Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads. | 07-31-2014 |
20140220776 | Multi-Direction Design for Bump Pad Structures - An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction. | 08-07-2014 |
20140231987 | Connector Structures of Integrated Circuits - A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad. | 08-21-2014 |
20140231994 | APPARATUS FOR LEAD FREE SOLDER INTERCONNECTIONS FOR INTEGRATED CIRCUITS - An apparatus includes an integrated circuit having at least one input/output terminal comprising copper formed thereon. A metal cap layer overlies an upper surface of the at least one input/output terminal. A substrate includes at least one conductive trace formed on a first surface, and a metal finish layer overlies a portion of the at least one conductive trace. A lead free solder connection is disposed between the metal cap layer and the metal finish layer, and a first intermetallic compound is disposed at an interface between the metal cap layer and the lead free solder connection. The lead free solder connection has a copper content of less than 0.5 wt. %, and the first intermetallic compound is substantially free of copper. | 08-21-2014 |
20140248722 | Packaging and Function Tests for Package-on-Package and System-in-Package Structures - A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls. | 09-04-2014 |
20140252598 | Package Having Substrate with Embedded Metal Trace Overlapped by Landing Pad - A package and method of making the package are provided. An embodiment package includes an integrated circuit supporting a conductive pillar, a substrate having a landing pad on each embedded metal trace, a landing pad width greater than a corresponding embedded metal trace width, and a conductive material electrically coupling the conductive pillar to the landing pad. In an embodiment, the landing pad overlaps the metal trace in one direction. | 09-11-2014 |
20140252647 | Warpage Reduction and Adhesion Improvement of Semiconductor Die Package - Various embodiments of mechanisms for forming a die package and a package on package (PoP) structure using one or more compressive dielectric layers to reduce warpage are provided. The compressive dielectric layer(s) is part of a redistribution structure of the die package and its compressive stress reduces or eliminates bowing of the die package. In addition, the one or more compressive dielectric layers improve the adhesion between redistribution structure and the materials surrounding the semiconductor die. As a result, the yield and reliability of the die package and PoP structure using the die package are improved. | 09-11-2014 |
20140264337 | PACKAGING MECHANISMS FOR DIES WITH DIFFERENT SIZES OF CONNECTORS - Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost. | 09-18-2014 |
20140264769 | PACKAGING MECHANISMS FOR DIES WITH DIFFERENT SIZES OF CONNECTORS - Embodiments of mechanisms for forming a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate. The usage of the interconnect substrate enables cost reduction because it is cheaper to make than an interposer with through silicon vias (TSVs). The interconnect substrate also enables dies with different sizes of bump structures to be packaged in the same die package. | 09-18-2014 |
20140264930 | Fan-Out Interconnect Structure and Method for Forming Same - A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad. | 09-18-2014 |
20140291838 | Design Scheme for Connector Site Spacing and Resulting Structures - A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad. | 10-02-2014 |
20140302669 | Pillar Structure having a Non-Planar Surface for Semiconductor Devices - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 10-09-2014 |
20140335662 | METHODS FOR FORMING PACKAGE-ON-PACKAGE STRUCTURES HAVING BUFFER DAMS - Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: placing a device die having a plurality of metal posts over a release layer, wherein the release layer is over a first carrier; forming a plurality of through-assembly vias (TAVs) over the release layer; forming a dam member between the device die and the plurality of TAVs; molding the device die, the dam member, and the plurality of TAVs in a molding compound; and grinding the molding compound to expose ends of the plurality of metal posts and ends of the plurality of TAVs, wherein a top surface of the molding compound is substantially level with the exposed ends of the plurality of metal posts and exposed ends of the plurality of TAVs. | 11-13-2014 |
20140346673 | Methods and Apparatus for bump-on-trace Chip Packaging - Methods and apparatuses for a attaching a first substrate to a second substrate are provided. In some embodiments, a first substrate has a protective layer, such as a solder mask, around a die attach area, at which a second substrate is attached. A keep-out region (e.g., an area between the second substrate and the protective layer) is a region around the second substrate in which the protective layer is not formed or removed. The keep-out region is sized such that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids and while allowing traces in the keep-out region to be covered by the underfill. | 11-27-2014 |
20140377946 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 12-25-2014 |
20150037936 | Strength of Micro-Bump Joints - A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface. | 02-05-2015 |
20150040387 | Semiconductor Wafer Carrier and Method of Manufacturing - A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants. | 02-12-2015 |
20150069595 | Apparatus and Method for a Component Package - A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure. | 03-12-2015 |
20150072476 | Methods and Apparatus for Package on Package Devices with Reversed Stud Bump Through Via Interconnections - Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed. | 03-12-2015 |
20150084186 | BUMP STRUCTURE HAVING A SINGLE SIDE RECESS - A bump structure includes a first end, and a second end opposite the first end. The bump structure further includes a first side connected between the first end and the second end. The bump structure further includes a second side opposite the first side. The second side is connected between the first end and the second end, and the second side comprises a recess for a reflowed solder material to fill. | 03-26-2015 |