Patent application number | Description | Published |
20080283946 | MAGNETORESISTIVE RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic random access memory includes a transistor having a gate electrode formed above a surface of a substrate, and first and second impurity diffusion regions which sandwich a channel region below the gate electrode, a first plug formed on the first impurity diffusion region, a recording element formed on the first plug, including a plurality of stacked layers, and configured to hold information in accordance with an internal magnetization state, a first signal line formed on the recording element, a second plug formed on the second impurity diffusion region, an electrical conductor formed on the second plug, an area of a shape of the electrical conductor, which is projected onto the surface of the substrate, being larger than that of a shape of the recording element, which is projected onto the surface of the substrate, and a second signal line formed on the electrical conductor. | 11-20-2008 |
20080310215 | MAGNETIC RANDOM ACCESS MEMORY AND WRITE METHOD OF THE SAME - A magnetic random access memory includes a memory unit including a memory cell array having a first memory cell for writing first information and a second memory cell for writing second information, and a controller connected to the memory unit, and configured to start supplying a write current in a first direction for writing the first information to the first memory cell and the second memory cell before a write data signal is determined, and, after the write data signal is determined, keep supplying the write current in the first direction to the first memory cell and supply the write current changed in a second direction for writing the second information to the second memory cell alone. | 12-18-2008 |
20080315335 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A magnetoresistive random access memory includes first and second magnetoresistive effect element. A shape of the first magnetoresistive effect element has a first length in a first direction and a second length in a second direction. The second length is equal to or greater than the first length. A ratio of the second length to the first length is a first value. The second magnetoresistive effect element is used to determine a resistance state of the first magnetoresistive effect element. A shape of the second magnetoresistive effect element has a third length in a third direction and a fourth length in a fourth direction. The fourth length is equal to or greater than the third length. A ratio of the fourth length to the third length is a second value which is greater than the first value. | 12-25-2008 |
20090010045 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A MRAM includes a first magnetoresistive effect (MR) element that takes a low and high resistance states. A second MR element is fixed to a low or high resistance state. First and second MOSFETs are connected to the first and second MR elements, respectively. A sense amplifier amplifies a difference between values of current flowing through the first and second MOSFETs. A current circuit outputs reference current whose value lies between current flowing through the first MR element of the low and high resistance states. A third MOSFET has one end that receives the reference current and is connected to its own gate terminal. The gate terminal of the second MOSFET receives the same potential as the gate terminal of the third MOSFET. A first resistance element is connected to the others end of the third MOSFET and has the same resistance as the second magnetoresistive effect element. | 01-08-2009 |
20090034320 | RESISTANCE CHANGE MEMORY AND WRITE METHOD OF THE SAME - A resistance change memory includes a resistance change element having a high-resistance state and a low-resistance state in accordance with write information, and a write circuit configured to supply a write current that the write current flowing through the resistance change element is held constant before and after the resistance change element is changed from the high-resistance state to the low-resistance state, and apply a write voltage that the write voltage applied to the resistance change element is held constant before and after the resistance change element is changed from the low-resistance state to the high-resistance state. | 02-05-2009 |
20090091969 | RESISTANCE CHANGE MEMORY - A resistance change memory includes a memory cell which is connected to a first node, and programmed from a first resistance state to a second resistance state, a first replica cell which is connected to a second node, generates a write voltage for programming from the first resistance state to the second resistance state, and is fixed in the first resistance state, and a first constant-current source connected to the second node, wherein when writing the second resistance state in the memory cell, a voltage of the first node is held equal to that of the second node. | 04-09-2009 |
20090190391 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A word line voltage is applied to a plurality of word lines. A read/write voltage is applied to a plurality of bit lines. The read/write voltage is applied to a plurality of source lines. A word line selector selects the word line and applies the word line voltage. A driver applies a predetermined voltage to the bit line and the source line, thereby supplying a current to the memory cell. A read circuit reads a first current having flowed through the memory cell, and determines data stored in the memory cell. When performing the read, the driver supplies a second current to second bit lines among other bit lines, which are adjacent to the first bit line through which the first current has flowed. The second current generates a magnetic field in a direction to suppress a write error in the memory cell from which data is to be read. | 07-30-2009 |
20090201710 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of cell arrays, each cell array including a plurality of mutually parallel word lines, a plurality of mutually parallel bit lines disposed to cross these word lines, and a plurality of cells connected to the intersections of these word lines and bit lines, respectively, one portion of the cell arrays forming a memory cell array that has the cells as memory cells, and another portion of the cell arrays forming a reference cell array that has the cells as reference cells. A cell selection circuit is operative to select from the memory cell array a memory cell whose data is to be read, and to select from the reference cell array a reference cell at a position corresponding to a position of the memory cell selected in the memory cell array. A sense amplifier circuit is operative to detect and compare a current or a voltage of the selected memory cell with a current or a voltage of the selected reference cell, and thereby read data of the memory cell. | 08-13-2009 |
20090201717 | RESISTANCE-CHANGE MEMORY - A resistance-change memory includes first and second bit lines running in the same direction, a third bit line running parallel to the first and second bit lines, fourth and fifth bit lines running in the same direction, a sixth bit line running parallel to the fourth and fifth bit lines, a first memory element which has one and the other terminals connected to the first and third bit lines, and changes to one of first and second resistance states, a first reference element having one and the other terminals connected to the fourth and sixth bit lines, and set in the first resistance state, a second reference element having one and the other terminals connected to the fifth and sixth bit lines, and set in the second resistance state, and a sense amplifier having first and second input terminals connected to the first and fourth bit lines. | 08-13-2009 |
20090257274 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under different conditions, and a write circuit which is connected to one end of the n resistance change elements, and applies a pulse current m (1≦m≦n) times to the n resistance change elements during a write operation. Letting Im be a current value of an mth pulse current, condition I | 10-15-2009 |
20090323395 | SEMICONDUCTOR STORAGE DEVICE - A plurality of memory cells, each including a variable resistance element capable of having four or more values, are arranged at intersections of first wirings and second wirings. A control circuit selectively drives the first and second wirings. A sense amplifier circuit compares, with a reference voltage, a voltage generated by a current flowing through a selected memory cell. A reference voltage generation circuit includes: a resistance circuit including first and second resistive elements connected in parallel. Each of the first resistive elements has a resistance value substantially the same as a maximum resistance value in the variable resistance elements, and each of the second resistive elements has a resistance value substantially the same as a minimum resistance value in the variable resistance elements. A current regulator circuit averages currents flowing through the first and second resistive elements. | 12-31-2009 |
20100046274 | RESISTANCE CHANGE MEMORY - A resistance change memory includes two memory cell arrays each including a plurality of memory cells, the memory cells including variable resistive elements, two reference cell arrays provided to correspond to the two memory cell arrays, respectively, and each including a plurality of reference cells, the reference cells having a reference value, and a sense amplifier shared by the two memory cell arrays and detecting data in an accessed memory cell by use of a reference cell array corresponding to a second memory cell array different from a first memory cell array including the accessed memory cell. In reading the data, a particular reference cell in one reference cell array is always activated for an address space based on one memory cell array as a unit. | 02-25-2010 |
20100054020 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell having a resistance which differs based on stored data, a bit line connected to the memory cell, a first MOSFET which clamps the bit line to a read voltage when reading data, a sense amplifier which detects the stored data in the memory cell based on a current flowing through the bit line, a first switch element which connects the sense amplifier to a drain of the first MOSFET, a second switch element which connects a source of the first MOSFET to the bit line, a third switch element which connects the drain of the first MOSFET to a ground terminal, and a fourth switch element which connects the source of the first MOSFET to a ground terminal. | 03-04-2010 |
20100067283 | SENSE AMPLIFIER - A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation. | 03-18-2010 |
20100073992 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell having a first resistance state and a second resistance state, a bit line connected to the memory cell, a reference cell fixed to the first resistance state, a reference bit line connected to the reference cell, and a generation circuit configured to generate a reading voltage and a reference voltage. The generation circuit includes a constant current source connected to a first node, a first replica cell connected between the first node and a second node and fixed to the first resistance state, a second replica cell connected between the second node and a third node and fixed to the second resistance state, a first resistance element connected between the first node and a fourth node, and a second resistance element connected between the fourth node and the third node. | 03-25-2010 |
20100165701 | RESISTIVE MEMORY - A resistive memory includes a plurality of memory cells, a plurality of reference cells having mutually different resistance values, at least one sense amplifier having a first input terminal connected to one selected memory cell which is selected from the plurality of memory cells at a time of read, and a second input terminal connected to one selected reference cell which is selected from the plurality of reference cells at the time of read, and one latch circuit which holds offset information of the at least one sense amplifier. The resistive memory further includes a decoder which selects, in accordance with the offset information, the one selected reference cell from the plurality of reference cells, and connects the one selected reference cell to the second input terminal of the at least one sense amplifier. | 07-01-2010 |
20100208512 | SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH RESISTANCE CHANGE ELEMENT - A latch circuit is connected to a first common node, a first, second output node, and a first, second connection node. A first resistance change element is connected to the first connection node, and a second common node. A second resistance change element is connected to the second connection node, and the second common node. When a first data is stored, voltages of the first common node, second common node, and first output node are set at a first reference voltage, and a voltage of the second output node is set at a second reference voltage. When a second data is stored, voltages of the first common node, second common node, and second output node are set at the first reference voltage, and a voltage of the first output node is set at the second reference voltage. | 08-19-2010 |
20100277972 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY CELL ARRAYS - First and second memory cell arrays are adjacent in a first direction. First and second areas are positioned adjacent to one and the other side of the first memory array in a second direction. Third and fourth areas are positioned adjacent to one and the other side of the second memory array in a second direction. A sense amplifier is arranged in the first area and a current sink is arranged in the fourth area. The sense amplifier compares a read current which flows into the current sink via a memory cell in the first memory cell array and the second area from the sense amplifier with a reference current which flows into the current sink via the third area and a reference memory cell in the second memory cell array from the sense amplifier. | 11-04-2010 |
20110063900 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes a magnetoresistive element includes a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is variable and a nonmagnetic layer disposed between the fixed layer and the recording layer. A direction of a read current is set to a first direction in a case where an expression of MR ratio ≧|I | 03-17-2011 |
20110235402 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first cell array includes memory cells and reference cells, a second cell array located adjacent to the first cell array in a first direction, a third cell array located adjacent to the first cell array in a second direction crossing the first direction, a fourth cell array located adjacent to the second cell array in the second direction, and a sense amplifier connected to the first to fourth cell array and configured to compare a current through a memory cell with a current through a reference cell to determine the data of the memory cell. A reference cell is selected from a cell array which is diagonally opposite to a cell array as a read target. | 09-29-2011 |
20110305067 | SEMICONDUCTOR MEMORY DEVICE IN WHICH RESISTANCE STATE OF MEMORY CELL IS CONTROLLABLE - According to one embodiment, a semiconductor memory device includes memory cells and sense amplifiers. One end of the memory cell is connected to each of bit lines. The other end of the memory cell is connected to a source line. The sense amplifiers are connected to the bit lines. First writing changes the resistance of the memory cells connected to a first state by a current running from the source line to the bit lines. Second writing changes the resistance of the memory cells to a second state by a current running from the bit lines to the source line on the basis of data retained by the sense amplifiers after the first writing. Before the first writing, data is read from the memory cells, and the read data is retained in the sense amplifiers, and the data retained by the sense amplifiers is overwritten in accordance with write data. | 12-15-2011 |
20120063215 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current. | 03-15-2012 |
20120069629 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first reference cell being arranged in a first cell array, and a plurality of first fuse cells being arranged in the first cell array. The first reference cell and the plurality of first fuse cells are arranged on the same row or column. | 03-22-2012 |
20120155146 | RESISTANCE-CHANGE MEMORY - According to one embodiment, a resistance-change memory includes memory cells between a bit line and a source line, each of the memory cells including a memory element and a cell transistor having a gate connected to a word line, an n-channel transistor having a gate to which a first control voltage is applied, and a current path connected to the bit line, and a p-channel transistor having a gate to which a second control voltage is applied, and a current path connected to the source line. When the memory cell is read, the potential of the bit line is controlled by the first control voltage, and the potential of the source line is controlled by the second control voltage. | 06-21-2012 |
20120230090 | SEMICONDUCTOR MEMORY - A semiconductor memory has a first switch circuit and a second switch circuit. The semiconductor memory has a row decoder that controls a voltage of a word line. The semiconductor memory has a first writing circuit including a first signal terminal connected to one end of the first switch circuit to input and output a writing current. The semiconductor memory has a second writing circuit including a second signal terminal connected to a one end of the second switch circuit to input and output the writing current. The semiconductor memory has a select transistor including a control terminal connected to the word line. The semiconductor memory has a resistance change element that is connected in series with the select transistor between the first bit line and the second bit line and varies in resistance value depending on an applied current. | 09-13-2012 |
20120243297 | RESISTANCE CHANGE TYPE MEMORY - According to one embodiment, a resistance change type memory includes first to third bit lines, a word line and a memory cell connected to the first to third bit lines and the word line. The memory cell includes a first transistor and a first memory element between the first and third bit lines, a second transistor and a second memory element between the second and third bit lines. Control terminals of the first and second transistors are connected to the word line. The resistance states of the first and second memory elements change to the first or second resistance state in accordance with a write pulse. | 09-27-2012 |
20120320665 | SEMICONDUCTOR MEMORY - A semiconductor memory includes a first memory cell including: a first resistance change element and a first select transistor. The semiconductor memory includes a second memory cell including: a second select transistor and a second resistance change element. The semiconductor memory includes a third memory cell including: a third select transistor and a third resistance change element, the third memory cell acting as a reference cell. The semiconductor memory includes a fourth memory cell including: a fourth resistance change element and a fourth select transistor, the fourth memory cell acting as a reference cell. | 12-20-2012 |
20130229861 | DRIVING METHOD OF SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE - In a memory, a signal holder holds voltages according to data in the storage elements. A busy-signal controller controls a busy-signal. The busy-signal determines whether to permit or reject reception of a read/write enable signal. During reception of the read/write enable signal is rejected, the signal holder holds a first to a third voltages. The first voltage corresponds to target data stored in a first storage element. The second voltage corresponds to first sample data of first logic written to the first storage element. The third voltage corresponds to second sample data of second logic. A sense amplifier detects logic of the target data by comparing a read signal of the first voltage with a reference signal generated by the second and third voltages. The write driver writes the target data/write data to the first storage element. After writing, the reception of the read/write enable signal is permitted. | 09-05-2013 |
20130250653 | DRIVING METHOD OF SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE - A memory includes storage elements, a signal holding part and a sense amplifier. A driving-method includes a read operation for reading target data stored in a first storage element of the storage elements. In the read operation, the signal holding part holds a first voltage according to the target data. First sample data of a first logic is written to the first storage element. The signal holding part holds a second voltage according to the first sample data. Second sample data of a second logic opposite to the first logic is written to the first storage element. The signal holding part holds a third voltage according to the second sample data. The sense amplifier compares a read signal based on the first voltage with a reference signal generated based on the second and third voltages to detect a logic of the target data stored in the first storage element. | 09-26-2013 |
20130322163 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first cell array includes memory cells and reference cells, a second cell array located adjacent to the first cell array in a first direction, a third cell array located adjacent to the first cell array in a second direction crossing the first direction, a fourth cell array located adjacent to the second cell array in the second direction, and a sense amplifier connected to the first to fourth cell array and configured to compare a current through a memory cell with a current through a reference cell to determine the data of the memory cell. A reference cell is selected from a cell array which is diagonally opposite to a cell array as a read target. | 12-05-2013 |
20140085972 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM AND ACCESS METHOD TO SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection circuit configured to select a row in the block array as a page to be selected, and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page. Each of the memory blocks includes a memory cell array having a plurality of memory cells, a row selection circuit configured to select a row of the memory cell array, and a column selection circuit configured to select a column of the memory cell array. | 03-27-2014 |
20150036424 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM AND ACCESS METHOD TO SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection circuit configured to select a row in the block array as a page to be selected, and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page. Each of the memory blocks includes a memory cell array having a plurality of memory cells, a row selection circuit configured to select a row of the memory cell array, and a column selection circuit configured to select a column of the memory cell array. | 02-05-2015 |