Patent application number | Description | Published |
20080283901 | NONVOLATILE MEMORY WITH MULTIPLE BITS PER CELL - A dual-gate memory cell includes a first memory device and a second memory device each having a gate electrode and a charge storage gate dielectric layer. The first and second memory devices share a channel region and source and drain regions. Such a memory cell is read by sensing the charge in one of the dielectric layers by applying a first voltage in the gate electrode associated with the dielectric layer sensed, and applying a second voltage substantially different than the first voltage in the other dielectric layer. | 11-20-2008 |
20080283921 | DUAL-GATE NMOS DEVICES WITH ANTIMONY SOURCE-DRAIN REGIONS AND METHODS FOR MANUFACTURING THEREOF - A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located above a semiconductor or channel region in the active layer defined by spaced-apart diffusion regions formed by implanting antimony ions. The antimony-doped diffusion regions are particularly suitable in the dual-gate device because it can be implanted and activated at a temperature less than 900° C. and show little movement of the implanted antimony ions even after numerous thermal steps in the manufacturing process. As a result, dual-gate devices with well-controlled channel lengths may be achieved. | 11-20-2008 |
20080285349 | NONVOLATILE MEMORY WITH BACKPLATE - The present invention provides a non-volatile memory string having serially connected dual-gate devices, in which a first gate dielectric layer adjacent a first gate electrode layer in each dual-gate device is charge-storing and in which the second gate electrode adjacent a non-charge storing gate dielectric layer are connected in common. In one implementation, the second gate electrodes of the dual-gate devices in the memory string are provided by a continuous layer of doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more of these conductors. | 11-20-2008 |
20080286925 | NONVOLATILE MEMORY WITH BACKPLATE - The present invention provides a non-volatile memory string having serially connected dual-gate devices, in which a first gate dielectric layer adjacent a first gate electrode layer in each dual-gate device is charge-storing and in which the second gate electrode adjacent a non-charge storing gate dielectric layer are connected in common. In one implementation, the second gate electrodes of the dual-gate devices in the memory string are provided by a continuous layer of doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more of these conductors. | 11-20-2008 |
20080315294 | DUAL-GATE DEVICE AND METHOD - A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices. | 12-25-2008 |
20080318380 | DUAL-GATE DEVICE AND METHOD - A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices. | 12-25-2008 |
20090067246 | Methods to Prevent Program Disturb in Nonvolatile Memory - Methods are provided to be used individually or in any combination that reduce program disturb in a non-volatile memory consisting of dual-gate memory cells. These methods counteract the effect of a leakage current in reducing a boosted voltage in a non-selected dual-gate memory string. According to one approach, a voltage applied to the gate electrode of an access device of a dual-gate memory cell is increased during a programming event. According to a second approach, the gate electrodes of an access device of a dual-gate memory cell is applied a series of electrical pulses synchronously with programming the memory device of the dual-gate memory cell by a second series of electrical pulses. According to a third approach, multiple dual-gate select devices are provided between a string of dual-gate memory devices and either a source line or a bit line, or both. | 03-12-2009 |
20090080258 | ERASE METHOD IN THIN FILM NONVOLATILE MEMORY - An erase method applicable to dual-gate memory strings has key advantages over erase methods for other thin-film non-volatile memory strings. The advantages include (a) fast erase without any source-to-body short; (b) flexible erase which erases any number of memory cells in a block (i.e., from none to all cells); (c) source voltage may be set to optimize non-selected string channel boosting; and (d) the thickness of the thin-film device's body can be optimized for scalability. The method uses the access devices of the dual-gate memory cells in a memory string to form inversion channels, so as to provide conductive paths between the memory cells to be erased and a node at a more positive voltage than the erase voltage applied to the gate electrodes of the memory devices to be erased. | 03-26-2009 |
20090087973 | RETENTION IMPROVEMENT IN DUAL-GATE MEMORY - A manufacturing process improves retention capabilties of dual-gate non-volatile memory cells by limiting the effects of lateral charge movement. The process limits lateral extents of the charge storage medium that is an integral part of the memory device within the dual-gate device. | 04-02-2009 |
20090090913 | DUAL-GATE MEMORY DEVICE WITH CHANNEL CRYSTALLIZATION FOR MULTIPLE LEVELS PER CELL (MLC) - A method and a dual-gate memory device having a memory transistor and an access transistor are provided to allow multiple bits to be stored in the dual-gate memory device. The memory transistor and the access transistor each have a channel region formed in a mobility enhanced material crystallized from an amorphous semiconductor material. The amorphous semiconductor material may include, for example, silicon. Mobility enhancement may be achieved by: (a) Excimer laser annealing; (b) lateral crystallization; (c) metal-induced lateral crystallization; (d) a combination of laser annealing and metal-induced laterally crystallization steps; or (e) solid-phase, epitaxially growth. | 04-09-2009 |
20090191680 | DUAL-GATE MEMORY DEVICE WITH CHANNEL CRYSTALLIZATION FOR MULTIPLE LEVELS PER CELL (MLC) - A method and a dual-gate memory device having a memory transistor and an access transistor are provided to allow multiple bits to be stored in the dual-gate memory device. The memory transistor and the access transistor each have a channel region formed in a mobility enhanced material crystallized from an amorphous semiconductor material. The amorphous semiconductor material may include, for example, silicon. Mobility enhancement may be achieved by: (a) Excimer laser annealing; (b) lateral crystallization; (c) metal-induced lateral crystallization; (d) a combination of laser annealing and metal-induced laterally crystallization steps; or (e) solid-phase, epitaxially growth. | 07-30-2009 |
20090258462 | METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS - The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells. | 10-15-2009 |
20100140679 | STACKED DUAL-GATE NMOS DEVICES WITH ANTIMONY SOURCE-DRAIN REGIONS AND METHODS FOR MANUFACTURING THEREOF - A three-dimensional memory structure includes multiple layers of memory devices, each memory device including a dual-gate device. A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located above a semiconductor or channel region in the active layer defined by spaced-apart diffusion regions formed by implanting antimony ions. The antimony-doped diffusion regions are particularly suitable in stacked memory devices because antimony can be implanted and activated at a temperature less than 900° C. and show little movement of the implanted antimony ions even after numerous thermal steps in the manufacturing process. As a result, dual-gate devices in a stacked memory device with well-controlled channel lengths may be achieved. | 06-10-2010 |
20110021019 | METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS - The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells. | 01-27-2011 |
20110156044 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. | 06-30-2011 |
20120223380 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. | 09-06-2012 |