Patent application number | Description | Published |
20080283839 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A non-volatile semiconductor storage device includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed of polysilicon on the first insulating layer, a pair of conductor regions formed on the first insulating layer to pass through the semiconductor layer and to sandwich a part of the semiconductor layer, and formed of a metal or a silicide, a tunnel layer formed on the part of the semiconductor layer sandwiched between the pair of conductor regions, a charge storage layer formed on the tunnel layer, a second insulating layer formed on the charge storage layer, and a control gate formed on the second insulating layer. | 11-20-2008 |
20080305300 | Composition for matte layer formation, release sheet using the same, and synthetic leather produced using said release sheet - There are provided a composition for matte layer formation suitable for the production of a matte synthetic leather having a matte surface with a high level of jet-blackness even without the practice of embossing, raising, etc., and a release sheet for the production of a matte synthetic leather by using the composition. The composition for matte layer formation suitable for the production of a matte synthetic leather comprises a thermosetting resin and a matting agent as indispensable components. The matting agent comprises one or at least two types of organic or/and inorganic porous fine particles. The porous fine particles have a mean particle diameter in the range of 0.5 to 20 μm and a specific surface area in the range of 1 to 1000 m | 12-11-2008 |
20090015074 | ELECTRONIC DEVICE - An electronic device includes a substrate, a first chip mounted on the substrate and having a first terminal, a second terminal, an input pad and a semiconductor time switch connected to the first terminal and the second terminal and configured to disconnect the first terminal and the second terminal upon lapse of a prescribed lifetime, the input pad being configured to set the prescribed lifetime, a second chip mounted on the substrate and incorporating an operational device having a third terminal connected to the first terminal and a fourth terminal serving as an input terminal for an external device, a first memory device mounted on the substrate, having a fifth terminal connected to the second terminal and storing information required for operating the operational device, and an encapsulater covering at least the input pad of the first chip. | 01-15-2009 |
20090020803 | AGING DEVICE - An aging device according to an embodiment of the present invention includes a semiconductor substrate, first and second diffusion layers provided in a first element region, a floating gate provided above a channel region between the first and second diffusion layers, and a control gate electrode provided beside the floating gate with an interval in the lateral direction. A coupling capacitance between the floating gate and the control gate electrode is larger than a coupling capacitance between the floating gate and the semiconductor substrate. | 01-22-2009 |
20090058501 | SEMICONDUCTOR DEVICE - A semiconductor device includes an input terminal, a first aging device whose source is connected to the input terminal to turn on at τ | 03-05-2009 |
20090186474 | Nonvolatile semiconductor storage device and manufacturing method therefor - A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the element-forming region; a floating gate electrode which is provided on the first gate insulating film and in which a width of a lower hem facing the element-forming region is narrower than a width of the element-forming region in a section taken in a direction perpendicular to a direction in which the isolation regions extend; a second gate insulating film provided on the floating gate electrode; and a control gate electrode provided on the second gate insulating film. | 07-23-2009 |
20090218613 | SEMICONDUCTOR TIME SWITCH SUITABLE FOR EMBEDDING IN NAND FLASH MEMORY DEVICE - A semiconductor time switch includes a cell portion and an electron booster. The cell portion contains parallel linear semiconductor layers provided on a substrate as active areas, first and second linear conductor layers alternately formed on the linear semiconductor layers through a gate insulating film as control gates and extending so as to cross the linear semiconductor layers, and floating gates inserted into respective intersections of the linear semiconductor layers and the first linear conductor layers, and coupled to the first linear conductor layers through an inter-gate insulating film. The electron booster is provided on the substrate and includes a MOS transistor having a booster gate electrode connected to the second linear conductor layers. Both ends of the linear semiconductor layers are connected to first and second I/O terminals of the switch, respectively. | 09-03-2009 |
20090321807 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM - A semiconductor device includes a semiconductor substrate, a first and second semiconductor regions formed on the semiconductor substrate insulated and separated from each other, a gate dielectric film formed on the substrate to overlap the first and second semiconductor regions, a floating gate electrode formed on the gate dielectric film and in which a coupling capacitance of the first semiconductor region is larger than that of the second semiconductor region, first source and drain layers formed on the first semiconductor region to interpose the floating gate electrode therebetween, a first and second wiring lines connected to the first source and drain layers, respectively, second source and drain layers formed on the second semiconductor region to interpose the floating gate electrode therebetween, and a third wiring line connected to the second source and drain layers in common. | 12-31-2009 |
20100101722 | Composition for matte layer formation, release sheet using the same, and synthetic leather produced using said release sheet - There are provided a composition for matte layer formation suitable for the production of a matte synthetic leather having a matte surface with a high level of jet-blackness even without the practice of embossing, raising, etc., and a release sheet for the production of a matte synthetic leather by using the composition. The composition for matte layer formation suitable for the production of a matte synthetic leather comprises a thermosetting resin and a matting agent as indispensable components. The matting agent comprises one or at least two types of organic or/and inorganic porous fine particles. The porous fine particles have a mean particle diameter in the range of 0.5 to 20 μm and a specific surface area in the range of 1 to 1000 m | 04-29-2010 |
20100214840 | MULTI-DOT FLASH MEMORY AND METHOD OF MANUFACTURING THE SAME - A multi-dot flash memory includes active areas arranged in a first direction, which extend to a second direction crossed to the first direction, the first and second direction being parallel to a surface of a semiconductor substrate, floating gates arranged in the first direction, which are provided above the active areas, a word line provided above the floating gates, which extends to the first direction, and bit lines provided between the floating gates, which extend to the second direction. Each of the floating gates has two side surfaces in the first direction, shapes of the two side surfaces are different from each other, and shapes of the facing surfaces of the floating gates which are adjacent to each other in the first direction are symmetrical. | 08-26-2010 |
20100265418 | DISPLAY APPARATUS - A display apparatus provided on a surface of a panel, the display apparatus includes a quadrangular window section provided in the surface, an image display surface disposed in and recessed from the quadrangular window section, a frame configured to surround the image display surface and extend from the image display surface to the quadrangular window section, in which the frame includes an inside edge formed in a substantially trapezoidal shape having a shorter upper edge and a longer lower edge, and an outside edge formed in a quadrangular shape conforming to the quadrangular window section, in which a difference in length in a lateral direction between the shorter edge of the inside edge and an upper edge of the outside edge is set larger than a difference in length in the lateral direction between the longer edge of the inside edge and a lower edge of the outside edge. | 10-21-2010 |
20100270607 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell. | 10-28-2010 |
20110032762 | MULTI-DOT FLASH MEMORY - According to one embodiment, a multi-dot flash memory includes an active area, a floating gate arranged on the active area via a gate insulating film and having a first side and a second side facing each other in a first direction, a word line arranged on the floating gate via an inter-electrode insulating film, a first bit line arranged on the first side of the floating gate via a first tunnel insulating film and extending in a second direction intersecting the first direction, and a second bit line arranged on the second side of the floating gate via a second tunnel insulating film and extending in the second direction. The active area has a width in the first direction narrower than that between a center of the first bit line and a center of the second bit line. | 02-10-2011 |
20110038213 | MULTI-DOT FLASH MEMORY - A multi-dot flash memory set potentials of bit lines being disposed at a left side of a selected floating gate to V | 02-17-2011 |
20110134700 | Nonvolatile Semiconductor Memory - A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode. | 06-09-2011 |
20120075903 | Nonvolatile Semiconductor Memory - A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode. | 03-29-2012 |
20120241880 | MAGNETIC MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element. | 09-27-2012 |
20140027870 | MAGNETIC MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element. | 01-30-2014 |