Patent application number | Description | Published |
20080227253 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which includes a first gate wiring layer and a second gate wiring layer adjacent to each other; a first diffused layer provided on a side between the wiring layers; a second diffused layer provided on one side external to the side between the wiring layers; and a third diffused layer provided on the other side external to the side between the wiring layers, the method including: forming a first mask including an opening; implanting a channel impurity for threshold voltage control using the first mask; forming a first diffused layer using the first mask by implanting a first impurity; forming a first gate wiring layer and a second gate wiring layer after removing the first mask; and forming a second diffused layer and a third diffused layer using the first gate wiring layer and the second gate wiring layer as a second mask by implanting a second impurity. | 09-18-2008 |
20080283816 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided with silicon pillars arranged in a matrix and formed substantially perpendicularly to a main surface of a substrate, bit lines provided above the silicon pillars, gate electrodes covering a side surface of each silicon pillars via gate insulation films, first and second diffusion layers provided at an upper part and a lower part of the silicon pillar, respectively, a reference potential wiring provided in common to the plural silicon pillars for supplying a reference potential to the first diffusion layers, and memory elements connected between the second diffusion layers and the bit lines. The gate electrodes covering the silicon pillars adjacent in a first direction crossing the bit line are in contact with each other, and gate electrodes covering the silicon pillars adjacent in a second direction parallel with the bit line are isolated from each other. | 11-20-2008 |
20080283907 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided with first and second silicon pillars formed substantially perpendicularly to a main surface of a substrate, a gate electrode covering side surfaces of the first and second silicon pillars via a gate insulation film, first and second diffusion layers provided on a lower part and an upper part of the first silicon pillar, respectively, a cap insulation film covering an upper part of the second silicon pillar, a gate contact connected to the gate electrode, and a protection insulation film in contact with the upper surfaces of the first and second silicon pillars. The gate contact is connected to an upper region of the gate electrode provided at the periphery of the cap insulation film. An opening is formed on the protection insulation film provided at the side of the first silicon pillar. | 11-20-2008 |
20080296671 | SEMICONDUCTOR MEMORY DEVICE, MANUFACTURING METHOD THEREOF, AND DATA PROCESSING SYSTEM - A semiconductor memory device includes a silicon pillar, a gate electrode covering a side surface of the silicon pillar via a gate insulation film, diffusion layers ( | 12-04-2008 |
20080296677 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME AND DATA PROCESSING SYSTEM - A semiconductor device is provided with a silicon pillar formed substantially perpendicularly to a main surface of a substrate, a gate electrode covering side surface of the silicon pillar via a gate insulation film, a conductive layer provided on an upper part of the silicon pillar, a cylindrical sidewall insulation film intervening between the conductive layer and the gate electrode so as to insulate therebetween. An inner wall of the side wall insulation film is in contact with the conductive layer, and an outer wall of the side wall insulation film is in contact with the gate electrode. | 12-04-2008 |
20080308854 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF - A semiconductor memory device including a cylinder hole extended in a thickness direction of an insulating film; a capacitor configured from a lower electrode, which is formed on an inner surface of the cylinder hole, and an upper electrode, which is formed on a surface of the lower electrode via a capacitance insulating film; and a capacitance contact plug which is embedded in the insulating film and a portion thereof is exposed inside the cylinder hole so as to be electrically connected with the lower electrode due to the lower electrode covering a surface of this exposed portion, wherein the capacitance contact plug is provided by the portion, which is exposed inside the cylinder hole, being extended from a bottom portion side towards an upper portion side of the cylinder hole. | 12-18-2008 |
20090065856 | Semiconductor device having vertical MOS transistor and method for manufacturing the semiconductor device - In a vertical MOS transistor in which a semiconductor pillar is formed by etching a semiconductor substrate in a portion surrounded by an isolation film, the semiconductor pillar is covered with a gate insulating film and a gate electrode to be made a channel part, and diffusion layers to be a source and a drain are included on a top and a bottom of the channel part, electrode | 03-12-2009 |
20090072291 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: first word lines; second word lines, each of the second word lines being electrically connected to a corresponding one of the first word lines; bit lines; and memory cells, each of the memory cells including a transistor and a capacitor. The semiconductor memory device includes: a first cell array portion in which the memory cells are arrayed; and a second cell array portion in which dummy cells, the first word lines and the bit lines are located in the same layout as the first cell array portion. In the second cell array portion, conductive plugs are provided, each of the conductive plugs connecting one of the first word lines and a corresponding one of the second word lines. | 03-19-2009 |
20090085088 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME AS WELL AS DATA PROCESSING SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes low voltage and high voltage transistors over a substrate. The low voltage transistor is configured by at least one unit transistor. The high voltage transistor is configured by a greater number of the unit transistors than the at least one unit transistor that configures the low voltage transistor. Each of the unit transistors may include a vertically extending portion of semiconductor providing a channel region and having a uniform height, a gate insulating film extending along a side surface of the vertically extending portion of semiconductor, a gate electrode separated by the gate insulating film from the vertically extending portion of semiconductor, and upper and lower diffusion regions being respectively disposed near the top and bottom of the vertically extending portion of semiconductor. The greater number of the unit transistors are connected in series to each other and have gate electrodes eclectically connected to each other. | 04-02-2009 |
20090085102 | SEMICONDUCTOR DEVICE HAVING VERTICAL SURROUNDING GATE TRANSISTOR STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND DATA PROCESSING SYSTEM - A semiconductor device is provided which includes: semiconductor pillars which include impurity diffused layers, each semiconductor pillar having a width which allows full depletion of a semiconductor forming each semiconductor pillar, the impurity diffused layers being electrically connected to each other; and a common gate section which covers side faces of the pillars. | 04-02-2009 |
20090206445 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions each may include an active region, a device isolation groove that defines the active region, and a device isolation insulating film that fills the device isolation groove. The first and second well regions may include first and second well layers, respectively. The well isolation region may include a well isolation groove, a well isolation insulating film that fills the well isolation groove, and a diffusion stopper layer disposed under a bottom of the well isolation groove. The first and second well layers have first and second bottoms respectively, which are deeper in depth than a bottom of the device isolation groove and shallower in depth than the bottom of the well isolation groove. | 08-20-2009 |
20100078712 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor pillar, a first gate insulating film, a gate electrode, and a first contact. The first semiconductor pillar extends upwardly from a semiconductor substrate. The first gate insulating film covers side surfaces of the first semiconductor pillar. The gate electrode covers the first gate insulating film. The first gate insulating film insulates the gate electrode from the first semiconductor pillar. The first contact partially overlaps, in plane view, the first semiconductor pillar and the gate electrode. The first contact includes a silicon layer having a top level which is higher than a top level of the gate electrode. | 04-01-2010 |
20100252879 | Semiconductor device and method of forming the same - A semiconductor device includes a semiconductor substrate; a well of a first conductivity type in the semiconductor substrate; a first element; and a first vertical transistor. The first element supplies potential to the well, the first element being in the well. The first element may include, but is not limited to, a first pillar body of the first conductivity type. The first pillar body has an upper portion that includes a first diffusion layer of the first conductivity type. The first diffusion layer is greater in impurity concentration than the well. The first vertical transistor is in the well. The first vertical transistor may include a second pillar body of the first conductivity type. The second pillar body has an upper portion that includes a second diffusion layer of a second conductivity type. | 10-07-2010 |
20100295110 | DEVICE AND MANUFACTURING METHOD THEREOF - A device manufacturing method includes forming a first insulation film on a semiconductor substrate. A first mask is formed on the first insulation film to extend in a first direction and have a linear pattern. The first insulation film is etched using the first mask as mask to process the insulation film into a linear body. A second mask is formed on the linear body to extend in a second direction different from the first direction and have a linear pattern. The linear body is etched using the second mask as mask to process the linear body into a pillar element. A first conductive film is formed to cover the pillar body. The first conductive film is etched to form a first electrode of the first conductive film on side surfaces of the pillar body. | 11-25-2010 |
20100330774 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions each may include an active region, a device isolation groove that defines the active region, and a device isolation insulating film that fills the device isolation groove. The first and second well regions may include first and second well layers, respectively. The well isolation region may include a well isolation groove, a well isolation insulating film that fills the well isolation groove, and a diffusion stopper layer disposed under a bottom of the well isolation groove. The first and second well layers have first and second bottoms respectively, which are deeper in depth than a bottom of the device isolation groove and shallower in depth than the bottom of the well isolation groove. | 12-30-2010 |
20110183488 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method for forming a semiconductor device includes the following processes. A substrate structure having an insulating upper surface is formed. The insulating upper surface has a step. An insulating layer is formed over the insulating upper surface. The insulating layer covers the step. The insulating layer includes first and second portions which are bounded by the step. The first portion is thinner than the second portion. First and second grooves are formed in the first and second portions, respectively. The first groove is shallower than the second groove. First and second conductive films which fill up the first and second grooves, respectively are formed. The first conductive film is thinner than the second conductive film. | 07-28-2011 |
20110215391 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an isolation region, a semiconductor region, a groove, and an insulating film. The semiconductor region is defined by the isolation region. The groove is in the semiconductor region. The groove has first and second ends. At least one of the first and second ends reaches the isolation region. The insulating film is in the groove. | 09-08-2011 |
20120025324 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME AS WELL AS DATA PROCESSING SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes low voltage and high voltage transistors over a substrate. The low voltage transistor is configured by at least one unit transistor. The high voltage transistor is configured by a greater number of the unit transistors than the at least one unit transistor that configures the low voltage transistor. Each of the unit transistors may include a vertically extending portion of semiconductor providing a channel region and having a uniform height, a gate insulating film extending along a side surface of the vertically extending portion of semiconductor, a gate electrode separated by the gate insulating film from the vertically extending portion of semiconductor, and upper and lower diffusion regions being respectively disposed near the top and bottom of the vertically extending portion of semiconductor. The greater number of the unit transistors are connected in series to each other and have gate electrodes eclectically connected to each other. | 02-02-2012 |
20120032256 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a first island and a first electrode. The first island includes a first semiconductor region, a first insulation region, and a first insulating film. The first semiconductor region has first and second side surfaces adjacent to the first insulation region and the first insulating film, respectively. The first electrode is adjacent to the first insulation region and the first insulating film. The first insulating film is between the first electrode and the first semiconductor region. | 02-09-2012 |
20120100682 | Manufactruing method of semiconductor device having vertical type transistor - A manufacturing method of a semiconductor device includes the steps of: forming an insulating pillar on the main surface of a silicon substrate; forming a protective film on the side surface of the insulating pillar; forming a silicon pillar on the main surface of the silicon substrate; forming a gate insulating film on the side surface of the silicon pillar; and forming first and second gate electrodes so as to contact each other and so as to cover the side surfaces of the silicon pillar and insulating pillar, respectively. According to the present manufacturing method, the protective film is formed on the side surface of the insulating pillar as a dummy pillar, thus preventing the dummy pillar from being eroded when the silicon pillar for channel is processed into a transistor. Therefore, it is possible to reduce a probability of occurrence of gate electrode disconnection. | 04-26-2012 |
20120104487 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include, but is not limited to, a transistor and a contact plug pillar of an impurity-diffused semiconductor. The transistor includes a semiconductor channel pillar having a vertical channel; and a first diffusion region adjacent to a lower portion of the semiconductor channel pillar. The contact plug pillar of an impurity-diffused semiconductor is coupled to the first diffusion region. | 05-03-2012 |
20120292681 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a groove in a periphery, a gate electrode partially embedded in the groove to sandwich the substrate from opposite directions by side walls of the groove, and a diffusion layer formed over the substrate and surrounded by the gate electrode. A resistance value of the diffusion layer is changed by changing a potential between the gate electrode and the diffusion layer. | 11-22-2012 |
20130093004 | SEMICONDUCTOR DEVICE INCLUDING DUMMY PILLAR NEAR INTERMEDIATE PORTION OF SEMICONDUCTOR PILLAR GROUP - A semiconductor device includes a semiconductor pillar group having semiconductor pillars which are formed in a first direction with a space left therebetween. A dummy pillar is disposed near a particular semiconductor pillar in the semiconductor pillar group in a second direction perpendicular to the first direction that is any one of the semiconductor pillars which are positioned in an intermediate portion exclusive of both end portions. Gate insulating films are formed on outer circumferential surfaces of the semiconductor pillars. One gate insulating film is formed on a part of an outer circumferential surface of the dummy pillar. Formed over side faces of the semiconductor pillars and over a side face of the dummy pillar via the gate insulating films, gate electrodes fill gaps between the semiconductor pillars and a gap between the particular semiconductor pillar and the dummy pillar. | 04-18-2013 |
20130134507 | SEMICONDUCTOR DEVICE INCLUDING SHARED PILLAR LOWER DIFFUSION LAYER - A semiconductor device includes a high-breakdown voltage transistor in which at least first and second vertical transistor are connected in series to each other. The first vertical transistor includes a first unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The second vertical transistor includes a second unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The plurality of unit transistors constituting the first and the second unit transistor groups have pillar lower diffusion layers which are shared. | 05-30-2013 |
20130161738 | SEMICONDUCTOR DEVICE - A semiconductor device | 06-27-2013 |
20130307056 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device comprising a semiconductor substrate including first, second and third surfaces, the second surface being placed above the first surface, the third surface having first and second edges connecting to the first and second surfaces, respectively; an isolation region including an insulator and formed on the first and third surfaces; an active region including the second surface and fenced with the insulator of the isolation region; and first and second semiconductor pillars each protruding upwardly from the second surface in the active region, wherein the first semiconductor pillar is thinner than the second semiconductor pillar. | 11-21-2013 |
20140015035 | SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR - Disclosed herein is a semiconductor device that includes: a semiconductor pillar projecting from a main surface of the semiconductor substrate, the semiconductor pillar having a first side surface extending in a first direction that is parallel to the main surface of the semiconductor substrate and a second side surface extending in a second direction crossing to the first direction and parallel to the main surface of the semiconductor substrate; a first impurity diffusion layer formed in an upper portion of the semiconductor pillar; a second impurity diffusion layer formed in the semiconductor substrate near a lower portion of the semiconductor pillar; an insulating pillar covering the first side surface; and a gate electrode covering the second side surface with an intervention of a gate insulating film. A width in the first direction of the semiconductor pillar is narrowed at the first side surface. | 01-16-2014 |
20140038375 | SEMICONDUCTOR DEVICE HAVING VERTICAL MOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device including a vertical MOS transistor, includes forming a trench for shallow trench isolation in a semiconductor substrate, and burying an element isolation insulating film in the trench, forming an insulating film to be a mask for forming a semiconductor pillar, in a region subjected to shallow trench isolation, etching the semiconductor substrate in the region subjected to the shallow trench isolation with the insulating film as a mask, and forming a semiconductor pillar for the vertical MOS transistor, implanting an impurity onto the semiconductor substrate, and forming a lower diffusion layer in the portion shallower than the depth of the shallow trench isolation, and forming a gate insulating film on the semiconductor substrate and the side surface of the semiconductor pillar for the vertical MOS transistor. | 02-06-2014 |
20140042555 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR PILLAR - Disclosed herein is a device that includes: a semiconductor substrate including an active region having a semiconductor pillar, the semiconductor pillar having first and second side surfaces substantially perpendicular to a main surface of the semiconductor substrate; an element isolation region surrounding the active region, the element isolation region including a first insulating pillar that is in contact with the first side surface of the semiconductor pillar; a gate electrode that covers the second side surface of the semiconductor pillar with an intervention of a gate insulating film; a first impurity diffusion layer formed on an upper surface of the semiconductor pillar; a second impurity diffusion layer formed in the active region located below the semiconductor pillar; and an etching protection wall that is arranged to surround the semiconductor pillar. | 02-13-2014 |
20140048860 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR PILLAR - Disclosed herein is a device that includes: first to fourth conductive lines embedded in a semiconductor substrate; a first semiconductor pillar located between the first and second conductive lines; a second semiconductor pillar located between the second and third conductive lines; a third semiconductor pillar located between the third and fourth conductive lines; a first storage element connected to an upper portion of the first semiconductor pillar; a second storage element connected to an upper portion of the third semiconductor pillar; and a bit line embedded in the semiconductor substrate connected to lower portions of the first to third semiconductor pillars. At least one of the first and second conductive lines and at least one of the third and fourth conductive lines being supplied with a potential so as to form channels in the first and third semiconductor pillars. | 02-20-2014 |
20140239384 | SEMICONDUCTOR DEVICE HAVING VERTICAL SURROUNDING GATE TRANSISTOR STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND DATA PROCESSING SYSTEM - A semiconductor device is provided which includes: semiconductor pillars which include impurity diffused layers, each semiconductor pillar having a width which allows full depletion of a semiconductor forming each semiconductor pillar, the impurity diffused layers being electrically connected to each other; and a common gate section which covers side faces of the pillars. | 08-28-2014 |
20150084122 | Semiconductor Device - A semiconductor device has an active region defined by a device isolation region arranged on a surface of a semiconductor substrate, a plurality of transistor pillars arranged along a first direction within the active region, and a first dummy pillar disposed in the device isolation region. The first dummy pillar is arranged on a line extending along the first direction from the transistor pillars. The semiconductor device also has a second dummy pillar disposed between the transistor pillars and the first dummy pillar, a gate electrode continuously extending so as to surround each of side surfaces of the transistor pillars, a first power supply gate electrode surrounding a side surface of the first dummy pillar, and a second power supply gate electrode surrounding a side surface of the second dummy pillar. The second power supply gate electrode is connected to the gate electrode and the first power supply gate electrode. | 03-26-2015 |