Patent application number | Description | Published |
20150041909 | COMPLETING MIDDLE OF LINE INTEGRATION ALLOWING FOR SELF-ALIGNED CONTACTS - In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET having complete middle of line integration. Specifically, a hard mask layer and set of spacers are removed from the gate stacks leaving behind (among other things) a set of dummy gates. A liner layer is formed over the set of dummy gates and over a source-drain region adjacent to the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates and the source-drain region. An inter-layer dielectric (ILD) is then deposited over the set of dummy gates and over the source-drain region, and the set of dummy gates are then removed. The result is an environment in which a self-aligned contact to the source-drain region can be deposited. | 02-12-2015 |
20150091093 | INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME - Integrated circuits with dual silicide contacts and methods for fabricating integrated circuits with dual silicide contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having PFET areas and NFET areas. The method selectively forms first silicide contacts from a first metal in the PFET areas. Further, the method selectively forms second silicide contacts from a second metal in the NFET areas. The second metal is different from the first metal. | 04-02-2015 |
20150091094 | DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION - Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate. | 04-02-2015 |
20150214059 | INTEGRATED CIRCUITS WITH METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTACT STRUCTURES AND METHODS FOR FABRICATING SAME - Integrated circuits having metal-insulator-semiconductor (MIS) contact structures and methods for fabricating integrated circuits having metal-insulator-semiconductor (MIS) contact structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure formed from semiconductor material overlying a semiconductor substrate. The method includes depositing a layer of high-k dielectric material over the fin structure. Further, the method includes forming a metal layer or layers over the layer of high-k dielectric material to provide the fin structure with a metal-insulator-semiconductor (MIS) contact structure. | 07-30-2015 |
20150214113 | METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOUS FORMATION OF LOCAL CONTACT OPENINGS - A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings. | 07-30-2015 |
20150214228 | IINTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME - Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having selected source/drain regions and non-selected source/drain regions. The method forms a contact resistance modulation material over the selected source/drain regions. Further, the method forms a metal layer over the selected and non-selected source/drain regions. The method includes annealing the metal layer to form silicide contacts on the selected and non-selected source/drain regions. | 07-30-2015 |
20150214330 | REPLACEMENT LOW-K SPACER - A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer. | 07-30-2015 |
20150236106 | METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS - Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips. | 08-20-2015 |
20150279738 | SELF-ALIGNED CONTACTS AND METHODS OF FABRICATION - Embodiments of the present invention provide an improved contact and method of fabrication. A dielectric layer is formed over transistor structures which include gates and source/drain regions. A first etch, which may be a reactive ion etch, is used to partially recess the dielectric layer. A second etch is then used to continue the etch of the dielectric layer to form a cavity adjacent to the gate spacers. The second etch is highly selective to the spacer material, which prevents damage to the spacers during the exposure (opening) of the source/drain regions. | 10-01-2015 |
20150287636 | TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS - Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them. | 10-08-2015 |
20150303273 | PATTERNING MULTIPLE, DENSE FEATURES IN A SEMICONDUCTOR DEVICE USING A MEMORIZATION LAYER - Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures. | 10-22-2015 |
20150303295 | SELF-ALIGNED CONTACT OPENINGS OVER FINS OF A SEMICONDUCTOR DEVICE - Approaches for forming a set of contact openings in a semiconductor device (e.g., a FinFET device) are provided. Specifically, the semiconductor device includes a set of fins formed in a substrate, a gate structure (e.g., replacement metal gate (RMG)) formed over the substrate, and a set of contact openings adjacent the gate structure, each of the set of contact openings having a top section and a bottom section, wherein a width of the bottom section, along a length of the gate structure, is greater than a width of the top section. The semiconductor device further includes a set of metal contacts formed within the set of contact openings. | 10-22-2015 |
20150311082 | SELF-ALIGNED GATE CONTACT FORMATION - Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch. | 10-29-2015 |
20150311199 | MULTIPLE FIN FINFET WITH LOW-RESISTANCE GATE STRUCTURE - Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density. | 10-29-2015 |
20150325473 | INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS - Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device. | 11-12-2015 |
20150333067 | DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION - Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate. | 11-19-2015 |
20150333162 | METHODS OF FORMING NANOWIRE DEVICES WITH METAL-INSULATOR-SEMICONDUCTOR SOURCE/DRAIN CONTACTS AND THE RESULTING DEVICES - A device includes a gate structure and a nanowire channel structure positioned under the gate structure. The nanowire channel structure includes first and second end surfaces. The device further includes a first insulating liner positioned on the first end surface and a second insulating liner positioned on the second end surface. The device further includes a metal-containing source contact positioned on the first insulating liner and a metal-containing drain contact positioned on the second insulating liner. | 11-19-2015 |
20150340467 | MERGED GATE AND SOURCE/DRAIN CONTACTS IN A SEMICONDUCTOR DEVICE - Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged. | 11-26-2015 |
20150372111 | METHODS OF FORMING NANOWIRE DEVICES WITH SPACERS AND THE RESULTING DEVICES - A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers. | 12-24-2015 |
20150372115 | METHODS OF FORMING NANOWIRE DEVICES WITH DOPED EXTENSION REGIONS AND THE RESULTING DEVICES - A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device. | 12-24-2015 |
20150380250 | SEMICONDUCTOR CONTACTS AND METHODS OF FABRICATION - Embodiments of the present invention provide an improved structure and method of contact formation. A cap nitride is removed from a gate in a region that is distanced from a fin. This facilitates reduced process steps, allowing the gate and the source/drain regions to be opened in the same process step. Extreme Ultraviolet Lithography (EUVL) may be used to pattern the resist to form the contacts. | 12-31-2015 |
20160027685 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DIRECTED SELF-ASSEMBLY - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a graphoepitaxy DSA directing confinement well using a sidewall of an etch layer that overlies a semiconductor substrate. The graphoepitaxy DSA directing confinement well is filled with a block copolymer. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etchable phase is etched while leaving the etch resistant phase substantially in place to define an etch mask with a nanopattern. The nanopattern is transferred to the etch layer. | 01-28-2016 |
20160049489 | INTEGRATED CIRCUITS WITH NANOWIRES AND METHODS OF MANUFACTURING THE SAME - Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a layered fin overlying a substrate, where the layered fin includes an SiGe layer and an Si layer. The SiGe layer and the Si layer alternate along a height of the layered fin. A dummy gate is formed overlying the substrate and the layered fin, and a source and a drain area formed in contact with the layered fin. The dummy gate is removed to expose the SiGe layer and the Si layer, and the Si layer is removed to produce an SiGe nanowire. A high K dielectric layer that encases the SiGe nanowire between the source and the drain is formed, and a replacement metal gate is formed so that the replacement metal gate encases the high K dielectric layer and the SiGe nanowire between the source and drain. | 02-18-2016 |
20160049490 | INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME - Integrated circuits with dual silicide contacts are provided. In an embodiment, an integrated circuit includes a semiconductor substrate including a first area and a second area. The integrated circuit includes a first source/drain region in and/or overlying the first area of the semiconductor substrate and a second source/drain region in and/or overlying the second area of the semiconductor substrate. The integrated circuit further includes a first contact over the first source/drain region and comprising a first metal silicide. The integrated circuit also includes a second contact over the second source/drain region and comprising a second metal silicide different from the first metal silicide. | 02-18-2016 |
20160056075 | PRECUT METAL LINES - Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided. | 02-25-2016 |
20160056104 | SELF-ALIGNED BACK END OF LINE CUT - Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. Spacers are formed on each Mx+1 sacrificial line. The gap between the spacers is used to determine the location and thickness of cuts to the Mx metal lines. This ensures that the Mx metal line cuts do not encroach on vias that interconnect the Mx and Mx+1 levels. It also allows for reduced limits in terms of via enclosure rules, which enables increased circuit density. | 02-25-2016 |
20160064514 | BORDERLESS CONTACT FORMATION THROUGH METAL-RECESS DUAL CAP INTEGRATION - An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s). | 03-03-2016 |
20160071774 | OPPOSITE POLARITY BORDERLESS REPLACEMENT METAL CONTACT SCHEME - An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A set of masks is formed over a portion of the semiconductor structure. Each mask in this set of masks covers at least one source/drain (s/d) contact location. An oxide layer is removed from remainder portions of the semiconductor structure that are not covered by the set of masks. Then an opposite-mask fill layer is formed in the remainder portions from which the oxide layer was removed. The oxide layer is then removed from the remainder of the semiconductor structure, i.e., the portion previously covered by the set of masks and contacts are formed to the at least s/d contact location in the recesses formed by the removal of the remainder of the oxide layer. | 03-10-2016 |
20160079168 | INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS - Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device. | 03-17-2016 |
20160079242 | PATTERNING MULTIPLE, DENSE FEATURES IN A SEMICONDUCTOR DEVICE USING A MEMORIZATION LAYER - Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures. | 03-17-2016 |
20160093704 | METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS - Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips. | 03-31-2016 |