Patent application number | Description | Published |
20090282315 | LDPC coding systems for 60 GHz millimeter wave based physical layer extension - LDPC coding systems for 60 GHz millimeter wave based physical layer extension. LDPC (Low Density Parity Check) encoding in cooperation with sub-carrier interleaving, in the context of orthogonal frequency division multiplexing (OFDM), and appropriate symbol mapping is performed in accordance with transmit processing as may be performed within a communication device. In a receiving communication device, receive processing may be performed on a received signal based on the type of LDPC, sub-carrier interleaving, and symbol mapping thereof. The LDPC code employed in accordance with such LDPC encoding may have a partial-tree like structure. In addition, appropriate manipulation of the bits assigned to respective sub-carriers may be performed to ensure that the bits emplaced in the MSB (Most Significant Bit) location of various symbols has some desired diversity (e.g., from different codewords, from appropriately different locations within a given codeword, etc.). | 11-12-2009 |
20100031118 | Accumulating LDPC (Low Density Parity Check) decoder - Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size. | 02-04-2010 |
20100031119 | Permuted accelerated LDPC (Low Density Parity Check) decoder - Permuted accelerated LDPC (Low Density Parity Check) decoder. This decoding approach operates by processing, in parallel, selected rows for multiple individual LDPC matrix rows from various sub-matrix rows (e.g., first group of rows from a first sub-matrix row, second group of rows from a second sub-matrix row, etc.). A memory structure of daisy chains is employed for memory management of APP (a posteriori probability) values and also for check edge messages/intrinsic information (λ) values. A first group of daisy chains may be employed for memory management of the APP values, and a second group of daisy chains may be employed for memory management of the check edge messages. These daisy chains operate to effectuate the proper alignment of APP (or gamma(γ)) values and check edge message/intrinsic information (λ) values for their respective updating in successive decoding iterations. | 02-04-2010 |
20100111145 | BASEBAND UNIT HAVING BIT REPETITIVE ENCODED/DECODING - A baseband unit includes an input/output interface and a processing module. The input/output interface module receives a data word of outbound data and outputs a plurality of outbound symbols. The processing module converts the data word into a bit repetitive data word; encodes the bit repetitive data word to produce an encoded data block; and converts the encoded data block into the plurality of outbound symbols. | 05-06-2010 |
20100115371 | Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding - Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding. Multiple LDPC matrices may be generated from a base code, such that multiple/distinct LDPC coded signals may be encoded and/or decoded within a singular communication device. Generally speaking, a first LDPC matrix is modified in accordance with one or more operations thereby generating a second LDPC matrix, and the second LDPC matrix is employed in accordance with encoding an information bit thereby generating an LDPC coded signal (alternatively performed using an LDPC generator matrix corresponding to the LDPC matrix) and/or decoding processing of an LDPC coded signal thereby generating an estimate of an information bit encoded therein. The operations performed on the first LDPC matrix may be any one of, or combination of, selectively merging, deleting, partially re-using one or more sub-matrix rows, and/or partitioning sub-matrix rows. | 05-06-2010 |
20100281330 | Low complexity communication device employing in-place constructed LDPC (Low Density Parity Check) code - Low complexity communication device employing in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform decoding of more than one type of LDPC coded signals. A common basis of decoder hardware (e.g., decoder circuitry) is employed when decoding all of the various types of LDPC coded signals that such a communication device can decode. However, all of the decoder hardware is only employed to decode signals corresponding to the lowest code rate LDPC code supported by the communication device. A first subset of the decoder hardware is employed to decode signals corresponding to the second to lowest code rate LDPC code, a second subset (being less than the first subset) is employed to decode signals corresponding to the third to lowest code rate LDPC code, etc. | 11-04-2010 |
20100281335 | Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code - Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform encoding of respective information bit groups using more than one type of LDPC codes. A switching module can select any one of the LDPC codes within an in-place LDPC code for use by an LDPC encoder circuitry to generate an LDPC coded signal. Depending on which sub-matrices of a superimposed LDPC matrix are enabled or disabled, one of the LDPC matrices from within an in-place LDPC code matrix set may be selected. A corresponding, respective generator matrix may be generated from each respective LDPC matrix. Selection among the various LDPC codes may be in accordance with a predetermined sequence, of based operating conditions of the communication device or communication system. | 11-04-2010 |
20110202816 | Distributed processing LDPC (Low Density Parity Check) decoder - Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed processing technique (e.g., daisy chain) to increase data throughput and reduce memory storage requirements. Routing congestion and critical path latency are also improved thereby. Each daisy chain includes a number of registers, and a number of localized MUXs (e.g., MUXs having merely 2 inputs each). The means presented herein also does not contain any barrel shifters, high fan-in multiplexers, or interconnection networks; therefore, the critical path is relatively short and it can also be pipelined to further increase data throughput. If desired, a communication device can include multiple configurations of such daisy chains to accommodate the decoding of various LDPC coded signals (e.g., such as for an application and/or communication device that must decoded LDPC codes using different low density parity check matrices). | 08-18-2011 |
20110283161 | Multi-code LDPC (Low Density Parity Check) decoder - Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals. | 11-17-2011 |
Patent application number | Description | Published |
20080282129 | Operational parameter adaptable LDPC (Low Density Parity Check) decoder - Operational parameter adaptable LDPC (Low Density Parity Check) decoder. A novel means is presented by which LDPC coded signal can be decoded, and any one or more operational parameters can be adjusted during the decoding processing. For example, the original information extracted from a received LDPC coded signal (e.g., log likelihood ratios (LLRs)), can be modified during (or before) the iterative decoding processing performed in accordance with decoding an LDPC coded signal. Such modification of an operational parameter can include any one or combination of scaling, compression (and expansion/decompression), adding an offset to or subtracting an offset from, scaling, rounding, and/or some other modification of an operational parameter. The bit (or variable) edge messages and/or the check edge messages can also undergo modification during decoding processing. In addition, the operational parameter modification can be selective, in that, different modification can be performed to different parameters and/or during different decoding iterations. | 11-13-2008 |
20090013237 | DISTRIBUTED PROCESSING LDPC (LOW DENSITY PARITY CHECK) DECODER - Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed processing technique (e.g., daisy chain) to increase data throughput and reduce memory storage requirements. Routing congestion and critical path latency are also improved thereby. Each daisy chain includes a number of registers, and a number of localized MUXs (e.g., MUXs having merely 2 inputs each). The means presented herein also does not contain any barrel shifters, high fan-in multiplexers, or interconnection networks; therefore, the critical path is relatively short and it can also be pipelined to further increase data throughput. If desired, a communication device can include multiple configurations of such daisy chains to accommodate the decoding of various LDPC coded signals (e.g., such as for an application and/or communication device that must decoded LDPC codes using different low density parity check matrices). | 01-08-2009 |
20090013238 | Multi-code LDPC (Low Density Parity Check) decoder - Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals. | 01-08-2009 |
20090013239 | LDPC (Low Density Parity Check) decoder employing distributed check and/or variable node architecture - LDPC (Low Density Parity Check) decoder employing distributed check into variable node architecture. A means of decoding processing is presented in which at least one portion of the check node processing functionality is actually integrated into the variable/bit node processing functionality (e.g., distributed check node embodiment). In alternative embodiments, at least one portion of the variable/bit node processing functionality is actually integrated into the check node processing functionality (e.g., distributed variable/bit node embodiment). In even other embodiments, some check node processing functionality is moved and integrated into the variable/bit node processing functionality, and some variable/bit node processing functionality is also moved and integrated into the check node processing functionality (e.g., combined distributed embodiment). It is also noted that, when appropriately selected, the modification of the check engine and bit engine can also allow for reduction in routing layout between such a check engine and bit engine within a communication device. | 01-08-2009 |
Patent application number | Description | Published |
20120198301 | Operational parameter adaptable LDPC (Low Density Parity Check) decoder - Operational parameter adaptable LDPC (Low Density Parity Check) decoder. A novel means is presented by which LDPC coded signal can be decoded, and any one or more operational parameters can be adjusted during the decoding processing. For example, the original information extracted from a received LDPC coded signal (e.g., log likelihood ratios (LLRs)), can be modified during (or before) the iterative decoding processing performed in accordance with decoding an LDPC coded signal. Such modification of an operational parameter can include any one or combination of scaling, compression (and expansion/decompression), adding an offset to or subtracting an offset from, scaling, rounding, and/or some other modification of an operational parameter. The bit (or variable) edge messages and/or the check edge messages can also undergo modification during decoding processing. In addition, the operational parameter modification can be selective, in that, different modification can be performed to different parameters and/or during different decoding iterations. | 08-02-2012 |
20120269294 | Modulation code set (MCS) and LDPC (Low Density Parity Check) coding within multiple user, multiple access, and/or MIMO wireless communications - Modulation code set (MCS) and LDPC (Low Density Parity Check) coding within multiple user, multiple access, and/or MIMO wireless communications. Selective operation in accordance with different operational modes is performed. Operation within a first mode may correspond to that which is in full compliance with a given protocol, standard, and/or recommended practice, while operation within a second mode may correspond to that which provides additional/augmented capability and/or functionality with respect to that protocol, standard, and/or recommended practice. Operational modes selectivity may be made between proprietary and non-proprietary modes of operation. All available modulation coding sets (MCSs) may be in employed by providing such multi-mode operation. When operating within one of the operational modes (e.g., proprietary), a signal is generated to include an integer number of data bits per orthogonal frequency division multiplexing (OFDM) symbol using any desired operation (e.g., floor, ceiling, rounding, etc.). | 10-25-2012 |
20130139026 | ACCUMULATING LDPC (LOW DENSITY PARITY CHECK) DECODER - The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size. | 05-30-2013 |
20130179756 | Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding - Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding. Multiple LDPC matrices may be generated from a base code, such that multiple/distinct LDPC coded signals may be encoded and/or decoded within a singular communication device. Generally speaking, a first LDPC matrix is modified in accordance with one or more operations thereby generating a second LDPC matrix, and the second LDPC matrix is employed in accordance with encoding an information bit thereby generating an LDPC coded signal (alternatively performed using an LDPC generator matrix corresponding to the LDPC matrix) and/or decoding processing of an LDPC coded signal thereby generating an estimate of an information bit encoded therein. The operations performed on the first LDPC matrix may be any one of, or combination of, selectively merging, deleting, partially re-using one or more sub-matrix rows, and/or partitioning sub-matrix rows. | 07-11-2013 |
20130223561 | LDPC coding systems for 60 GHz millimeter wave based physical layer extension - LDPC coding systems for 60 GHz millimeter wave based physical layer extension. LDPC (Low Density Parity Check) encoding in cooperation with sub-carrier interleaving, in the context of orthogonal frequency division multiplexing (OFDM), and appropriate symbol mapping is performed in accordance with transmit processing as may be performed within a communication device. In a receiving communication device, receive processing may be performed on a received signal based on the type of LDPC, sub-carrier interleaving, and symbol mapping thereof. The LDPC code employed in accordance with such LDPC encoding may have a partial-tree like structure. In addition, appropriate manipulation of the bits assigned to respective sub-carriers may be performed to ensure that the bits emplaced in the MSB (Most Significant Bit) location of various symbols has some desired diversity (e.g., from different codewords, from appropriately different locations within a given codeword, etc.). | 08-29-2013 |
20130238953 | Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code - Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform encoding of respective information bit groups using more than one type of LDPC codes. A switching module can select any one of the LDPC codes within an in-place LDPC code for use by an LDPC encoder circuitry to generate an LDPC coded signal. Depending on which sub-matrices of a superimposed LDPC matrix are enabled or disabled, one of the LDPC matrices from within an in-place LDPC code matrix set may be selected. A corresponding, respective generator matrix may be generated from each respective LDPC matrix. Selection among the various LDPC codes may be in accordance with a predetermined sequence, of based operating conditions of the communication device or communication system. | 09-12-2013 |
20140059408 | ACCUMULATING LDPC (LOW DENSITY PARITY CHECK) DECODER - Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size. | 02-27-2014 |