Patent application number | Description | Published |
20090242413 | Electroplating Head and Method for Operating the Same - An electroplating head is disposed above and proximate to an upper surface of a wafer. Cations are transferred from an anode to an electroplating solution within the electroplating head. The electroplating solution flows downward through a porous electrically resistive material at an exit of the electroplating head to be disposed on the upper surface of the wafer. An electric current is established between the anode and the upper surface of the wafer through the electroplating solution. The electric current is uniformly distributed by the porous electrically resistive material present between the anode and the upper surface of the wafer. The electric current causes the cations to be attracted to the upper surface of the wafer. | 10-01-2009 |
20100170803 | Method and Apparatus for Plating Semiconductor Wafers - First and second electrodes are disposed at first and second locations, respectively, proximate to a periphery of a wafer support, wherein the first and second location are substantially opposed to each other relative to the wafer support. Each of the first and second electrodes can be moved to electrically connect with and disconnect from a wafer held by the wafer support. An anode is disposed over and proximate to the wafer such that a meniscus of electroplating solution is maintained between the anode and the wafer. As the anode moves over the wafer from the first location to the second location, an electric current is applied through the meniscus between the anode and the wafer. Also, as the anode is moved over the wafer, the first and second electrodes are controlled to connect with the wafer while ensuring that the anode does not pass over an electrode that is connected. | 07-08-2010 |
20110081779 | Method and Apparatus for Material Deposition - Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer (“wafer”). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to the wafer surface. The selective heating of the wafer surface causes a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase at the interface in turn causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source. | 04-07-2011 |
20110155563 | APPARATUS AND METHOD FOR DEPOSITING AND PLANARIZING THIN FILMS OF SEMICONDUCTOR WAFERS - An electroplating apparatus for depositing a metallic layer on a surface of a wafer is provided. In one example, a proximity head capable of being electrically charged as an anode is placed in close proximity to the surface of the wafer. A plating fluid is provided between the wafer and the proximity head to create localized metallic plating. | 06-30-2011 |
Patent application number | Description | Published |
20090222519 | COMPUTER-BASED METHODS FOR ARRANGING MEETINGS AND SYSTEMS FOR PERFORMING THE SAME - Methods and systems for assisting individuals arrange meetings such as networking meetings with other individuals at a specified time (or within a specified time range) and at a specified place (or within a specified geographic region). More specifically, methods and systems for allowing individuals to post an invitation to for a meeting on an on-line network. | 09-03-2009 |
20110022659 | Location-Based Networking Methods and Systems for Performing the Same - Methods and systems for assisting individuals arrange meetings such as networking meetings with other individuals at a specified time (or within a specified time range) and/or at a specified place (or within a specified geographic region). More specifically, methods and systems for allowing individuals to post an invitation for a meeting on an on-line network and for allowing one or more other individuals to accept such invitation. | 01-27-2011 |
20110270926 | Computer-based Methods and Systems for Arranging Meetings Between Users and Methods and Systems for Verifying Background Information of Users - Methods and systems for verifying, authenticating, and/or rating the identity or profile characteristics of users of online social networks and other websites and applications. And improved systems and methods that allow one or more individuals to meet or otherwise network or connect or transact or exchange information, tangibles or intangibles with other individuals and methods and systems for verifying and/or rating the identity or profiles of users of online social networks and other websites or applications. | 11-03-2011 |
20110288917 | SYSTEMS AND METHODS FOR PROVIDING MOBILE TARGETED ADVERTISEMENTS - Methods and systems for displaying advertising or other promotional information to users via mobile devices. In particular, methods and systems that target advertisements using real-time information including location-based, defined geolocation territory rights (e.g., GeoEstate rights) and weather-related information. | 11-24-2011 |
20130254300 | Computer-based Methods and Systems for Verifying User Affiliations for Private or White Label Services - Systems and methods that allow one or more individuals to verify or authenticate their affiliation or status and thereby join or have access to multiple private or white label deals, offerings or services. | 09-26-2013 |
Patent application number | Description | Published |
20090304914 | Self assembled monolayer for improving adhesion between copper and barrier layer - The embodiments fill the need enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect with good electro-migration performance and with reduced risk of stress-induce voiding of copper interconnect. Electromigration and stress-induced voiding are affected by the adhesion between the barrier layer and the copper layer. A functionalization layer is deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect. The functionalization layer forms strong bonds with barrier layer and with copper to improve adhesion property between the two layers. An exemplary method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in order to improve electromigration performance of the copper interconnect is provided. The method includes depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, and oxidizing a surface of the metallic barrier layer. The method also includes depositing the functionalization layer over the oxidized surface of the metallic barrier layer, and depositing the copper layer in the copper interconnect structure after the funcationalization layer is deposited over the metallic barrier layer. | 12-10-2009 |
20100009535 | METHODS AND SYSTEMS FOR BARRIER LAYER SURFACE PASSIVATION - This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and subjecting the barrier layer to a process condition so as to form a removable passivated surface on the barrier layer. The method further includes removing the passivated surface from the barrier layer and depositing the gapfill copper layer onto the barrier layer. Another aspect of the present invention is an integrated system for depositing a copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the integrated system comprises at least one process module configured for barrier layer deposition and passivated surface formation and at least one other process module configured for passivated surface removal and deposition of copper onto the barrier layer. The system further includes at least one transfer module coupled so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment. | 01-14-2010 |
20100181025 | APPARATUS FOR THE REMOVAL OF A FLUORINATED POLYMER FROM A SUBSTRATE - An apparatus generating a plasma for removing fluorinated polymer from a substrate is provided. The apparatus includes a powered electrode assembly, which includes a powered electrode, a first dielectric layer, and a first wire mesh disposed between the powered electrode and the first dielectric layer. The apparatus also includes a grounded electrode assembly disposed opposite the powered electrode assembly so as to form a cavity wherein the plasma is generated. The first wire mesh is shielded from the plasma by the first dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the fluorinated polymer. | 07-22-2010 |
20100267229 | METHODS AND SYSTEMS FOR LOW INTERFACIAL OXIDE CONTACT BETWEEN BARRIER AND COPPER METALLIZATION - The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment. | 10-21-2010 |
20120269987 | Processes and Systems for Engineering a Barrier Surface for Copper Deposition - An integrated system for processing a substrate in controlled environment to enable deposition of a thin copper seed layer on a surface of a metallic barrier layer of a copper interconnect is provided. The system includes a lab-ambient transfer chamber, a vacuum transfer chamber, a vacuum process module for cleaning an exposed surface of a metal oxide of a underlying metal, a vacuum process module for depositing the metallic barrier layer, and a controlled-ambient transfer chamber filled with an inert gas, wherein at least one controlled-ambient process module is coupled to the controlled-ambient transfer chamber. In addition, the system includes an electroless copper deposition process module used to deposit the thin layer of copper seed layer on the surface of the metallic barrier layer. | 10-25-2012 |
20140322446 | PROCESSES AND SYSTEMS FOR ENGINEERING A COPPER SURFACE FOR SELECTIVE METAL DEPOSITION - An integrated system for transferring and processing a substrate in a controlled environment to enable selective deposition of a thin layer of a cobalt-alloy material on a copper surface of a copper interconnect to improve electromigration performance of the copper interconnect, comprising: a lab-ambient transfer chamber; a substrate cleaning reactor coupled to the lab-ambient transfer chamber, wherein the substrate cleaning reactor cleans the substrate surface to remove metal-organic complex contaminants on the substrate surface; a vacuum transfer chamber; a vacuum process module for removing organic contaminants from the substrate surface; a controlled-ambient transfer chamber filled with an inert gas; and an electroless cobalt-alloy material deposition process module used to deposit the thin layer of cobalt-alloy material on the copper surface of the copper interconnect after the substrate surface has been removed of metallic contaminants and organic contaminants, and the copper surface has been removed of copper oxide. | 10-30-2014 |
Patent application number | Description | Published |
20080280456 | Thermal methods for cleaning post-CMP wafers - Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating. | 11-13-2008 |
20080314756 | Methods and systems for three-dimensional integrated circuit through hole via gapfill and overburden removal - Presented are methods and systems for fabricating three-dimensional integrated circuits having large diameter through-hole vias. One embodiment of the present invention provides a method of processing a wafer having holes for through-hole vias. The method comprises plating a gapfill metal on the wafer. The method also comprises chemically or electrochemically deplating a portion of the overburden metal. The method further comprises using chemical mechanical planarization to planarize the gapfill metal and to remove the remaining overburden metal. Another embodiment of the present invention is an integrated system comprising a process chamber for containing the wafer, a plating component integrated with the process chamber, and a deplating component integrated with the process chamber. The plating component is configured to electrochemically plate a gapfill metal onto the wafer to a least partially fill the holes. The deplating component is configured to chemically or to electrochemically remove a portion of the overburden metal formed by the plating component. | 12-25-2008 |
20080315418 | Methods of post-contact back end of line through-hole via integration - Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention. | 12-25-2008 |
20080315422 | Methods and apparatuses for three dimensional integrated circuits - Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit. | 12-25-2008 |
20100044867 | METHODS OF POST-CONTACT BACK END OF LINE THROUGH-HOLE VIA INTEGRATION - Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention. | 02-25-2010 |
20120205807 | DEVICE WITH POST-CONTACT BACK END OF LINE THROUGH-HOLE VIA INTEGRATION - Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention. | 08-16-2012 |
Patent application number | Description | Published |
20130297390 | System, Method, and Computer-Readable Storage Medium for Payment of Online Purchases via a Portable Computing Device - A system, method, and computer-readable storage medium for enabling an individual to use a purchase-proxy mechanism to conduct a financial transaction from a computing device with an online merchant, whereby the individual is enabled to use stored personal data, such as financial account information and fulfillment information, without having to store the personal data with the online merchant. The system, method, and computer-readable storage medium furthermore enable an individual to change a payment and/or fulfillment option at the time of purchase with minimal inconvenience. | 11-07-2013 |
20130297464 | System, Method, and Computer-Readable Storage Medium For Identifying A Product - A system, method, and computer-readable storage medium for enabling the accurate identification of a product identified by a multiple product identifiers and offered by one or more merchants by using a product-data-identification mechanism via a computing device. The mechanism may enable accurate product-data identification by receiving a product identifier from a computing device, using the received product identifier to obtain one or more forms of data associated with the product identifier from one or more data sources, thereby enabling the mechanism to evaluate data from multiple sources to identify the most accurate product data associated with the product identifier. Data sources accessed by the mechanism may be scored according to the accuracy of their data, and a data system's score may affect how its data is evaluated by the mechanism. | 11-07-2013 |