Patent application number | Description | Published |
20090222603 | BUS COMMUNICATION SYSTEM - The invention relates to a bus communication system for serialized data transmission comprising: a transmitter, a receiver, and a data line, whereby said transmitter is arranged for transmitting a data signal over said data line; said receiver is arranged for receiving said data signal from said data line, wherein said transmitter is arranged for transmitting an end of transmission signal over said data line after transmission of said data signal is completed; and said receiver is arranged for receiving said end of transmission signal from said data line. | 09-03-2009 |
20100067633 | FAST POWERING-UP OF DATA COMMUNICATION SYSTEM - A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up. | 03-18-2010 |
20100085093 | MULTI-PHASE CLOCK SYSTEM - The invention relates to multi-phase clock system for receiving a plurality of clock signals (CLK | 04-08-2010 |
20100091921 | FAST POWERING-UP OF DATA COMMUICATION SYSTEM - A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up. | 04-15-2010 |
20100232304 | Mode switching of a data communications link - A method and apparatus for determining a time-out period used for switching between a first operational mode and a second operational mode of a data communications link, comprising detecting a signal used to request switching from the first operational mode to the second operational mode; measuring the duration of the signal; and determining the time-out period in dependence on the measured duration of the signal. | 09-16-2010 |
Patent application number | Description | Published |
20080279225 | Synchronized Receiver - There is provided a method of operating a communications system comprising a transmitting station and a receiving station, the method in the transmitting station comprising encoding a clock signal with data to form encoded signals for transmission; transmitting the encoded signals to the receiving station; the method in the receiving station comprising decoding the encoded signals to extract the clock signal and data; processing the data under the control of the decoded clock signal. The method further comprises, when no data is required to be transmitted to the receiving station, transmitting further encoded signals to the receiving station in order for the receiving station to decode the further encoded signals and extract a clock signal. | 11-13-2008 |
20080313375 | Bus Station and System and Method of Maintaining Synchronizing of a Bus Station - A bus station circuit ( | 12-18-2008 |
20090219983 | DATA COMMUNICATION CIRCUIT WITH EQUALIZATION CONTROL - An adaptive equalizer comprises an adjustable equalizer circuit that allows to enhance the frequency dependence of contents of the transmitted signals which suffer from losses in the connected transmission channel. A blind equalization tuning procedure is proposed that operates without knowledge about the characteristic of transmission channel. Phase positions of transitions in the equalized signal are detected. A digital post-processing circuit evaluates a measure for spread of the detected phase positions of transitions, accumulated over a plurality of the symbol periods. The digital post-processing circuit controls the adjustable equalizer, setting the adjustable equalizer to a setting wherein the detected spread is minimized. | 09-03-2009 |
20100172457 | METHOD AND CIRCUIT FOR RECEIVING DATA - The invention relates to a circuit and method for receiving a signal of which—at the receiver end—the frequency is basically unknown. By sampling the data and deriving the frequency of the signal (or actually: the data rate of the data carried by the signal) and setting a phase locked loop in the receiver to the derived—estimated—circuit, the receiver can very quickly tune in to the frequency of the signal. Hence, no embedded or accompanying clock is required for the signal. Oversampling of the signal by the receiver front end is preferred, though. | 07-08-2010 |
20100260283 | DUTY-CYCLE MODULATED TRANSMISSION - A duty-cycle modulated bit signalling method and circuit, comprising: signaling bits by virtue of a duty-cycle ratio; wherein the duty-cycle ratio is varied dependent upon the transmission rate of the signalling. A bit period comprises a long phase and a short phase and the duty-cycle therebetween is varied such that the ratio between the duration of the long phase and the duration of the short phase is increased for decreasing transmission rate. The duty-cycle ratio is varied dependent upon the transmission rate of the signalling according to one or more ranges of transmission rate. In a higher transmission rate range the duty-cycle is defined as a fixed ratio, and in a lower transmission range the duty-cycle is defined by a fixed length of the short phase of the bit period. | 10-14-2010 |
20110025382 | FREQUENCY DIVIDER - A frequency divider ( | 02-03-2011 |
20120119821 | INTEGRATED CIRCUIT FOR EMULATING A RESISTOR - An integrated circuit for emulating a resistor is based on the output resistance of a non-linear circuit element, such as a transistor. In the case of a transistor, it is biased into operation in its linear region, and a voltage dependent on the ac source-drain voltage is coupled to the gate voltage, thereby to improve linearity of the drain-source resistance with respect to the drain-source voltage. This modification to the gate voltage can be used to alter the transfer function such that the drain-source resistance is no longer dependent on the drain-source voltage. | 05-17-2012 |
20120146705 | CONTROL-VOLTAGE OF PASS-GATE FOLLOWS SIGNAL - A pass-gate has a passageway between an input node and an output node. The pass-gate selectively opens or closes the passageway for a signal at the input node under control of a voltage. The pass-gate has a field-effect transistor with a gate electrode and a current channel. The current channel is arranged between the input node and the output node. The gate electrode receives the voltage. The pass-gate is configured so as to have the voltage at the control electrode substantially follow the signal at the input node when the passageway is open to the signal. | 06-14-2012 |
20120154059 | MULTI PHASE CLOCK AND DATA RECOVERY SYSTEM - A multi-phase clock and data recovery circuit system including a voltage controlled oscillator including plural identical structural cells coupled in a ring, the voltage controlled oscillator providing plural phased shifted signals having the same frequency. The circuit further includes a feedback loop including plural data samplers adapted to receive the plural phase shifted signals provided by the voltage controlled oscillator and a phase detector coupled to coupled to a phase alignment circuit receiving output signals generated by the plural data samplers and generating control signals to the voltage controlled oscillator at a bit rate of the input signal. | 06-21-2012 |
20120155589 | FREQUENCY ACQUISITION UTILIZING A TRAINING PATTERN WITH FIXED EDGE DENSITY - A method for frequency acquisition comprising steps of, acquiring samples of an input signal, each sample having edges, making sets with a fixed number of consecutively taken samples, numbering the edges in each set and determining a number of edges, comparing the number of edges in each set with an expected number of edges in the sets, increasing a frequency of a reference oscillator used in acquiring samples if the actual number of edges exceeds the expected number of edges, and decreasing the frequency of the reference oscillator used in acquiring samples if the expected number of edges exceeds the actual number of edges in a set. | 06-21-2012 |
20120286588 | MEMS SWITCHING CIRCUIT - A switching circuit employs MEMS devices. In connection with various example embodiments, signal switching circuit couples primary and secondary data link connectors having at least two channels and an electrode for each channel. A MEMS switch is coupled to each channel in of the secondary data link connectors, and includes a suspended membrane, first and second contact electrodes (one being in the membrane) and a biasing circuit that biases the membrane for moving the membrane between open and closed positions to contact the electrodes. A switch controller circuit selectively controls the application of an actuation voltage to each of the biasing circuits, thereby selectively actuating the membranes between the open and closed positions for routing signals between the primary and secondary data link connectors. | 11-15-2012 |
20120286846 | SWITCHING CIRCUIT - A switching circuit employs switches operating at low on resistance and high off capacitance. In connection with various example embodiments, a switching circuit selectively couples a communication port to one of two or more internal circuits based upon a type of input at the communication port. A sensor circuit senses the type of the input and, based upon the sensed input type, actuates one or more switches in the switching circuit. | 11-15-2012 |
20140266394 | HIGH-SPEED SWITCH WITH SIGNAL-FOLLOWER CONTROL OFFSETTING EFFECTIVE VISIBLE-IMPEDANCE LOADING - A data link circuit switches high-speed signals through FET-based circuitry between channels. A FET responds to control signals at the gate terminal to operate in either a signal-passing mode or another (blocking) mode. In the passing mode, an AC (high-speed) signal is passed between the S-D terminals by coupling a first signal portion (of the AC signal) and with another signal portion diverted by the inherent capacitances associated with the FET. For offsetting the loading caused by the inherent capacitances associated with the FET-based switch, a biasing circuit is configured and arranged to bias the back-gate terminal of the FET transistor with a follower signal. | 09-18-2014 |
20140268445 | CROSS TALK MITIGATION - Cross-talk is mitigated in a switching circuit. In accordance with one or more embodiments, an apparatus includes a multi-pin connector having signal-carrying electrodes that communicate with a device external to the apparatus, and respective field-effect switches that couple the signal-carrying electrodes to respective communication channels in the apparatus. The switches include a first field-effect semiconductor switch having a gate electrode adjacent a channel region that connects electrodes (e.g., source and drain regions) when a threshold switching voltage is applied to the gate, in which the electrodes are connected between one of the signal-carrying electrodes and a first channel coupled to an electrostatic discharge (ESD) circuit. A bias circuit mitigates cross-talk between the communication channels by biasing the channel region of the first field-effect semiconductor switch (in an off state) to boost the threshold switching voltage over a threshold discharge voltage of the ESD circuit. | 09-18-2014 |
20150256063 | CHARGE PUMP CIRCUIT - A charge pump circuit is disclosed. The charge pump circuit includes a first circuit powered by a first supply voltage and configured to adjust a voltage of an output in response to first and second sets of control signals. The first circuit includes a set of transistors having respective switching voltages. A control circuit powered by a second voltage, less than the first supply voltage, is configured to generate the first and second sets of control signals. A voltage shifting circuit is configured to bias voltages of the first and second sets of control signals relative to the switching voltages. | 09-10-2015 |
20150256362 | SPEED IMPROVEMENT FOR A DECISION FEEDBACK EQUALIZER - Circuits, apparatus, and methods are disclosed for decision feedback equalization. In one embodiment, an apparatus includes a plurality of time-interleaved slices for processing an input data stream. Each of the slices includes a sampler circuit, a multiplexer, and a latch. In each slice, the multiplexer and the sampler circuit provide sampled output data corresponding to one of a plurality of different versions of the input data stream at times designated uniquely for the slice, according to one or more selection signals. The selection signals are derived from a output of the multiplexer of at least one other of the time-interleaved slices. The latch provides a controlled output in response to the multiplexer and the sampler circuit, as a function of the designated unique times. | 09-10-2015 |