Patent application number | Description | Published |
20080203487 | FIELD EFFECT TRANSISTOR HAVING AN INTERLAYER DIELECTRIC MATERIAL HAVING INCREASED INTRINSIC STRESS - By providing a highly stressed interlayer dielectric material, the performance of at least one type of transistor may be increased due to an enhanced strain-inducing mechanism. For instance, by providing a highly compressive silicon dioxide of approximately 400 Mega Pascal and more as an interlayer dielectric material, the drive current of the P-channel transistors may be increased by 2% and more while not unduly affecting the performance of the N-channel transistors. | 08-28-2008 |
20080286966 | METHOD OF FORMING A DIELECTRIC CAP LAYER FOR A COPPER METALLIZATION BY USING A HYDROGEN BASED THERMAL-CHEMICAL TREATMENT - A new technique is disclosed in which a barrier/cap layer for a copper based metal line is formed by using a thermal-chemical treatment based on hydrogen with a surface modification on the basis of a silicon-containing precursor followed by an in situ plasma based deposition of silicon based dielectric barrier material. The thermal-chemical cleaning process is performed in the absence of any plasma ambient. | 11-20-2008 |
20090001453 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FIELD EFFECT TRANSISTOR HAVING A STRESSED CHANNEL REGION - A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising at least one transistor element. An etch stop layer is formed over the transistor element. A stressed first dielectric layer is formed over the etch stop layer. A protective layer adapted to reduce an intrusion of moisture into the first dielectric layer is formed over the first dielectric layer. At least one electrical connection to the transistor element is formed. At least a portion of the protective layer remains over the first dielectric layer after completion of the formation of the at least one electrical connection. | 01-01-2009 |
20090057809 | STRESS TRANSFER IN AN INTERLAYER DIELECTRIC BY PROVIDING A STRESSED DIELECTRIC LAYER ABOVE A STRESS-NEUTRAL DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE - By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor. | 03-05-2009 |
20090108335 | STRESS TRANSFER BY SEQUENTIALLY PROVIDING A HIGHLY STRESSED ETCH STOP MATERIAL AND AN INTERLAYER DIELECTRIC IN A CONTACT LAYER STACK OF A SEMICONDUCTOR DEVICE - By forming two or more individual dielectric layers of high intrinsic stress levels with intermediate interlayer dielectric material, the limitations of respective deposition techniques, such as plasma enhanced chemical vapor deposition, may be respected while nevertheless providing an increased amount of stressed material above a transistor element, even for highly scaled semiconductor devices. | 04-30-2009 |
20090166800 | INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING A DOUBLET STRUCTURE OF STRESSED MATERIALS - By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed. | 07-02-2009 |
20090166814 | INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING STRESSED LAYERS WITH AN INTERMEDIATE BUFFER MATERIAL - A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased. | 07-02-2009 |
20100109131 | REDUCED WAFER WARPAGE IN SEMICONDUCTORS BY STRESS ENGINEERING IN THE METALLIZATION SYSTEM - In complex metallization systems of sophisticated semiconductor devices, appropriate stress compensation mechanisms may be implemented in order to reduce undue substrate deformation during the overall manufacturing process. For example, additional dielectric material and/or functional layers of one or more metallization layers may be provided with appropriate internal stress levels so as to maintain substrate warpage at a non-critical level, thereby substantially reducing yield losses in the manufacturing process caused by non-reliable attachment of substrates to substrate holders in process and transport tools. | 05-06-2010 |
20100221911 | PROVIDING SUPERIOR ELECTROMIGRATION PERFORMANCE AND REDUCING DETERIORATION OF SENSITIVE LOW-K DIELECTRICS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES - During the formation of complex metallization systems, a conductive cap layer may be formed on a copper-containing metal region in order to enhance the electromigration behavior without negatively affecting the overall conductivity. At the same time, a thermo chemical treatment may be performed to provide superior surface conditions of the sensitive dielectric material and also to suppress carbon depletion, which may conventionally result in a significant variability of material characteristics of sensitive ULK materials. | 09-02-2010 |
20100276790 | INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING STRESSED LAYERS WITH AN INTERMEDIATE BUFFER MATERIAL - A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased. | 11-04-2010 |
20100327362 | NON-INSULATING STRESSED MATERIAL LAYERS IN A CONTACT LEVEL OF SEMICONDUCTOR DEVICES - In sophisticated semiconductor devices, non-insulating materials with extremely high internal stress level may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors, wherein the non-insulating material may be appropriately “encapsulated” by dielectric material. Consequently, a desired high strain level may be obtained on the basis of a reduced layer thickness, while still providing the insulating characteristics required in the contact level. | 12-30-2010 |
20110073959 | STRESS ENGINEERING IN A CONTACT LEVEL OF SEMICONDUCTOR DEVICES BY STRESSED CONDUCTIVE LAYERS AND AN ISOLATION SPACER - In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements. | 03-31-2011 |
20120235285 | PROTECTION OF REACTIVE METAL SURFACES OF SEMICONDUCTOR DEVICES DURING SHIPPING BY PROVIDING AN ADDITIONAL PROTECTION LAYER - When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process. | 09-20-2012 |
20140048912 | COMPRESSIVE STRESS TRANSFER IN AN INTERLAYER DIELECTRIC OF A SEMICONDUCTOR DEVICE BY PROVIDING A BI-LAYER OF SUPERIOR ADHESION AND INTERNAL STRESS - The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer. | 02-20-2014 |