Patent application number | Description | Published |
20080203467 | NROM FLASH MEMORY DEVICES ON ULTRATHIN SILICON - An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top. | 08-28-2008 |
20080217676 | ZIRCONIUM SILICON OXIDE FILMS - Electronic apparatus and systems include structures having a dielectric layer containing a zirconium silicon oxide film. A zirconium silicon oxide film may be disposed in an integrated circuit, as well as in a variety of other electronic devices. Additional apparatus, systems, and methods are disclosed. | 09-11-2008 |
20080220618 | ZIRCONIUM SILICON OXIDE FILMS - Electronic apparatus, systems, and methods include structures having a dielectric layer containing zirconium silicon oxide film. The zirconium silicon oxide film may be disposed in an integrated circuit, as well as in a variety of other electronic devices. Additional apparatus, systems, and methods are disclosed. | 09-11-2008 |
20080224240 | ATOMIC LAYER DEPOSITION OF Zrx Hfy Sn1-x-y O2 FILMS AS HIGH k GATE DIELECTRICS - The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO | 09-18-2008 |
20080226219 | Zinc oxide optical waveguides - The present disclosure includes methods, devices, and systems having zinc oxide waveguides for optical signal interconnections. One optical signal interconnect system includes an oxide layer on a semiconductor substrate. A ZnO waveguide can be provided in the oxide layer and connected to a silicon detector to receive optical signals having a wavelength, for example, between 500 and 375 nanometers (nm). | 09-18-2008 |
20080226220 | Zinc oxide diodes for optical interconnections - The present disclosure includes methods, devices, and systems for zinc oxide diodes for optical interconnections. One system includes a ZnO emitter confined within a circular geometry in an oxide layer on a silicon substrate. An optical waveguide is formed in the oxide layer and has an input coupled to the ZnO emitter. A detector is coupled to an output of the optical waveguide. | 09-18-2008 |
20080227262 | Vertically base-connected bipolar transistor - Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor. | 09-18-2008 |
20080233725 | Methods for stressing semiconductor material structures to improve electron and/or hole mobility of transistor channels fabricated therefrom, and semiconductor devices including such structures - Semiconductor material strips are secured to substrates in such a way as to stress the semiconductor material. The strips of semiconductor material may be compressively stressed, subjected to tensile stress, or some strips may be compressively stressed while other strips are tensilely stressed. Stress may be induced by forming non-planarities on the surface of the substrate to which the strips are to be secured. The non-planarities may be configured to stress strips of semiconductor material as the strips are secured thereover and over an intervening surface of the substrate, or to stress strips as the non-planarities are removed from beneath the strips. The strain that ultimately results from stressing the strips improves carrier mobility (i.e., electron mobility, electron hole pair, or “hole,” mobility) relative to the carrier mobilities of unstrained semiconductor materials. The strained strips of semiconductor material may be used in the fabrication of semiconductor device structures such as transistors. | 09-25-2008 |
20080237802 | STRUCTURES INCLUDING PASSIVATED GERMANIUM - A method of passivating germanium that comprises providing a germanium material and carburizing the germanium material to form a germanium carbide material. The germanium carbide material may be formed by microwave-plasma enhanced chemical vapor deposition by exposing the germanium material to a microwave generated plasma that is formed from a carbon-containing source gas and hydrogen. The source gas may be a carbon-containing gas selected from the group consisting of ethylene, acetylene, ethanol, a hydrocarbon gas having from one to ten carbon atoms per molecule, and mixtures thereof. The resulting germanium carbide material may be amorphous and hydrogenated. The germanium material may be carburized without forming a distinct boundary at an interface between the germanium material and the germanium carbide material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the germanium carbide material, are also disclosed. | 10-02-2008 |
20080246578 | OPEN PATTERN INDUCTOR - Various embodiments includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. Embedding the stacked open pattern inductor in a magnetic oxide or in an insulator and a magnetic material increases the inductance of the inductor and allows the magnetic flux to be confined to the area of the inductor. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems. | 10-09-2008 |
20080248618 | ATOMIC LAYER DEPOSITION OF CeO2/Al2O3 FILMS AS GATE DIELECTRICS - The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric layer is described. The described arrangement produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. The dielectric structure is formed by depositing cerium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing aluminum oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric layer of cerium oxide and aluminum oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memory, or as a dielectric in an NROM device, because the high dielectric constant (high-k) of the film provides the functionality of a much thinner silicon dioxide film. | 10-09-2008 |
20080258245 | Semiconductor Constructions and Transistor Gates - One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first layered defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second layer defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide. | 10-23-2008 |
20080265243 | Magnetic floating gate flash memory structures - Methods of forming ferromagnetic floating gate structures are described. The methods include atomic layer deposition of multiple precursor films, followed by alloying the metals in the precursor films, to form a ferromagnetic floating gate. Devices that include ferromagnetic floating gates formed with these methods are also described. | 10-30-2008 |
20080268605 | Capacitors and methods with praseodymium oxide insulators - Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties. | 10-30-2008 |
20080274625 | METHODS OF FORMING ELECTRONIC DEVICES CONTAINING Zr-Sn-Ti-O FILMS - A dielectric film containing Zr—Sn—Ti—O and methods of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO | 11-06-2008 |
20080277734 | IMPLANTATION PROCESSES FOR STRAINING TRANSISTOR CHANNELS OF SEMICONDUCTOR DEVICE STRUCTURES AND SEMICONDUCTOR DEVICES WITH STRAINED TRANSISTOR CHANNELS - The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavties, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed. | 11-13-2008 |
20080283830 | Zinc-tin oxide thin-film transistors - Methods of forming transparent zinc-tin oxide structures are described. Devices that include transparent zinc-tin oxide structures as at least one of a channel layer in a transistor or a transparent film disposed over an electrical device that is at a substrate. | 11-20-2008 |
20080283940 | LOW-TEMPERATURE GROWN HIGH QUALITY ULTRA-THIN CoTiO3 GATE DIELECTRICS - A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO | 11-20-2008 |
20080296650 | High-k dielectrics with gold nano-particles - A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory device, a persistent memory device, a capacitor, as well as other devices and systems. The insulator layer may be formed using atomic layer deposition (ALD) to reduce the overall device thermal exposure. The insulator layer may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or semiconductor oxide oxycarbide, and the gold nano-particles in insulator layer increase the work function of the insulator layer and affect the tunneling current and the threshold voltage of the transistor. | 12-04-2008 |
20080296652 | SPLIT GATE FLASH MEMORY CELL WITH BALLISTIC INJECTION - A split floating gate flash memory cell is comprised of source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The sections of the floating gate are isolated from each other by a depression in the control gate. The cell is programmed by creating a positive charge on the floating gate and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the floating gate section adjacent to the pinched off channel region. | 12-04-2008 |
20080297249 | CMOS AMPLIFIERS WITH FREQUENCY COMPENSATING CAPACITORS - The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier. | 12-04-2008 |
20080308855 | Memory devices with isolation structures and methods of forming and programming the same - Memory devices and methods of programming and forming the same are disclosed. In one embodiment, a memory device has memory cells contained within dielectric isolation structures to isolate them from at least those memory cells in communication with other bit lines, such as to facilitate forward-bias write operations. The dielectric isolation structures contain an upper well having a first conductivity type and a buried well having a second conductivity type. By forward biasing the junction from the buried well to the upper well, electrons can be injected into charge-storage nodes of memory cells that are contained within the dielectric isolation structures. | 12-18-2008 |
20080315279 | NANOWIRE TRANSISTOR WITH SURROUNDING GATE - One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein. | 12-25-2008 |
20080315917 | Programmable computing array - Methods, devices, and systems for programmable computing arrays have been described. One or more embodiments include programming both a first and a second floating gate of a combined memory and logic element to one of at least two states, wherein programming the floating gates to one of the at least two states causes the combined memory and logic element to operate as a first logic gate type. One or more embodiments also include programming both the first and the second floating gates of the combined memory and logic element to another of the at least two states, wherein programming the floating gates to another of the at least two states causes the combined memory and logic element to operate as a second logic gate type, the second logic gate type being different from the first logic gate type. | 12-25-2008 |
20080316828 | Memory in logic cell - Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type. | 12-25-2008 |
20090002025 | MEMORY UTILIZING OXIDE NANOLAMINATES - Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers. | 01-01-2009 |
20090004759 | Cobalt-doped indium-tin oxide films and methods - Methods of forming cobalt-doped indium-tin oxide structures are shown. Properties of structures include transparency, conductivity, and ferromagnetism. Monolayers that contain indium, monolayers that contain tin, and monolayers that contain cobalt are deposited onto a substrate and subsequently processed to form cobalt-doped indium-tin oxide. Devices that include oxide structures formed with these methods should have better step coverage over substrate topography and more robust film mechanical properties. | 01-01-2009 |
20090004801 | Method of forming lutetium and lanthanum dielectric structures - Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide. Specific methods shown include monolayer deposition which yields process improvements such as chemistry control, step coverage, crystallinity/microstructure control. | 01-01-2009 |
20090008697 | SRAM CELLS WITH REPRESSED FLOATING GATE MEMORY, LOW TUNNEL BARRIER INTERPOLY INSULATORS - Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell which can be programmed to provide the SRAM cell with a definitive asymmetry so that the cell always starts in a particular state. The SRAM cells include a pair of cross coupled transistors. At least one of the cross coupled transistors includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. | 01-08-2009 |
20090010075 | NROM memory cell, memory array, related devices and methods - An array of memory cells configured to store at least one bit per one F | 01-08-2009 |
20090014783 | ULTRA-THIN BODY VERTICAL TUNNELING TRANSISTOR - A vertical tunneling, ultra-thin body transistor is formed on a substrate out of a vertical oxide pillar having active regions of opposing conductivity on opposite ends of the pillar. In one embodiment, the source region is a p+ region in the substrate under the pillar and the drain region is an n+ region at the top of the pillar. A gate structure is formed along the pillar sidewalls and over the body layers. The transistor operates by electron tunneling from the source valence band to the gate bias-induced n-type channels, along the ultra-thin silicon bodies, thus resulting in a drain current. | 01-15-2009 |
20090032910 | DIELECTRIC STACK CONTAINING LANTHANUM AND HAFNIUM - Dielectric layers containing a dielectric layer including lanthanum and hafnium and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices. | 02-05-2009 |
20090040810 | SWITCHED CAPACITOR DRAM SENSE AMPLIFIER WITH IMMUNITY TO MISMATCH AND OFFSETS - A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals. | 02-12-2009 |
20090042360 | STRAINED SEMICONDUCTOR BY FULL WAFER BONDING - One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein. | 02-12-2009 |
20090046504 | DRAM TUNNELING ACCESS TRANSISTOR - In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side at the top of the pillar. A second transistor is comprised of a second p+ source region doped into the second side of the top of the pillar and serially coupled to the top drain region for the first transistor. A second n+ drain region is doped into the substrate adjacent the pillar. Ultra-thin body layer run along each pillar sidewall between their respective active regions. A gate structure is formed along the pillar sidewalls and over the body layers. The transistors operate by electron tunneling from the source valence band to the gate bias-induced n-type channels, along the ultra-thin silicon bodies, thus resulting in a drain current. | 02-19-2009 |
20090072303 | NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS - An array of memory cells configured to store at least one bit per one F | 03-19-2009 |
20090073782 | SYSTEM, APPARATUS, AND METHOD TO INCREASE READ AND WRITE STABILITY OF SCALED SRAM MEMORY CELLS - Circuits, systems, and methods are disclosed for SRAM memories. An SRAM includes memory cells wherein read stability and write stability can be modified by adjusting a well bias signal operably coupled to an N-well of the memory cell. The well bias signal is generated at VDD or at a bias offset from VDD for both the read and the write operations. The memory cells may be adjusted for operation by designing the memory device to be stable relative to local parameter variations with a well bias substantially equal to VDD. The memory cells are then tested for stable read operations and stable write operations. If the write operations are unstable or the read operations are unstable, the well bias is modified and the memory cells are tested again. | 03-19-2009 |
20090090950 | SEMICONDUCTOR DEVICES - Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, with the first wafer being bonded and electrically coupled to the second wafer to form at least one CMOS device. Another embodiment includes a number of DRAM capacitors formed on a first wafer and support circuitry associated with the DRAM capacitors formed on a second wafer, with the first wafer being bonded and electrically coupled to the second wafer to form a number of DRAM cells. Another embodiment includes a first wafer having a number of vertical transistors coupled to a data line and a second wafer having amplifier circuitry associated with the number of vertical transistors, with the first wafer being bonded and electrically coupled to the second wafer. | 04-09-2009 |
20090108363 | STRAINED SEMICONDUCTOR, DEVICES AND SYSTEMS AND METHODS OF FORMATION - In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to provide the channel region with a desired strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from a crystalline region to an amorphous region to expand the volumes of the isolation regions and provide the channel region with a desired compressive strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from an amorphous region to a crystalline region to contract the volumes of the isolation regions to provide the channel region with a desired tensile strain. Other aspects and embodiments are provided herein. | 04-30-2009 |
20090127592 | FIN-JFET - Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate. | 05-21-2009 |
20090128195 | INTEGRATED CIRCUIT COMPARATOR OR AMPLIFIER - An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit. | 05-21-2009 |
20090134499 | ATOMIC LAYER DEPOSITION OF Hf3N4/HfO2 FILMS AS GATE DIELECTRICS - The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf | 05-28-2009 |
20090137067 | METHOD FOR FORMING AN INDUCTOR - A spiral inductor fabricated above a semiconductor substrate provides a large inductance while occupying only a small surface area. Including a layer of magnetic material above and below the inductor increases the inductance of the inductor. The magnetic material also acts as barrier that confines electronic noise generated in the spiral inductor to the area occupied by the spiral inductor. Inductance in a pair of stacked spiral inductors is increased by including a layer of magnetic material between the stacked spiral inductors. | 05-28-2009 |
20090146200 | MAGNESIUM-DOPED ZINC OXIDE STRUCTURES AND METHODS - Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties. | 06-11-2009 |
20090152620 | ATOMIC LAYER DEPOSITION OF GdScO3 FILMS AS GATE DIELECTRICS - The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of gadolinium oxide (Gd | 06-18-2009 |
20090155966 | DRAM WITH NANOFIN TRANSISTORS - One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein. | 06-18-2009 |
20090155976 | ATOMIC LAYER DEPOSITION OF DY-DOPED HFO2 FILMS AS GATE DIELECTRICS - The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO | 06-18-2009 |
20090167332 | ELECTRICAL PROBE - Methods, devices, and systems for probing electrical circuits without loading the circuits are described herein. One embodiment of an electrical probe includes a coaxial cable having an inner conductor and an outer conductor, an extension portion of the inner conductor extending beyond the outer conductor at a probe end of the cable. The electrical probe includes a conductive whisker having a first portion separated from and extending a distance along the extension portion such that the first portion and the extension portion form a first capacitor and a second portion having a probe tip for receiving an input test signal from a circuit node under test. | 07-02-2009 |
20090173979 | ALD OF AMORPHOUS LANTHANIDE DOPED TiOX FILMS - The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiO | 07-09-2009 |
20090191676 | FLASH MEMORY HAVING A HIGH-PERMITTIVITY TUNNEL DIELECTRIC - A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed above the substrate. The high-k tunneling dielectric can be deposited using evaporation techniques or atomic layer deposition techniques. The floating gate is formed on top of the high-k dielectric layer with an oxide gate insulator on top of that. A polysilicon control gate is formed on the top gate insulator. | 07-30-2009 |
20090191677 | MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES - A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration. | 07-30-2009 |
20090200602 | COMBINED VOLATILE AND NON-VOLATILE MEMORY DEVICE WITH GRADED COMPOSITION INSULATOR STACK - A memory device is fabricated with a graded composition tunnel insulator layer. This layer is formed over a substrate with a drain and a source region. The tunnel insulator is comprised of a graded SiC—GeC—SiC composition. A charge blocking layer is formed over the tunnel insulator. A trapping layer of nano-crystals is formed in the charge blocking layer. In one embodiment, the charge blocking layer is comprised of germanium carbide and the nano-crystals are germanium. The thickness and/or composition of the tunnel insulator determines the functionality of the memory cell such as the volatility level and speed. A gate is formed over the charge blocking layer. | 08-13-2009 |
20090207641 | NOVEL TRANSMISSION LINES FOR CMOS INTEGRATED CIRCUITS - Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application. | 08-20-2009 |
20090218566 | LOCALIZED COMPRESSIVE STRAINED SEMICONDUCTOR - One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein. | 09-03-2009 |
20090218611 | HIGH DENSITY STEPPED, NON-PLANAR FLASH MEMORY - A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column. The second plurality of memory cells are coupled to the first plurality of memory cells through a series connection of their source/drain regions. | 09-03-2009 |
20090218612 | MEMORY UTILIZING OXIDE-CONDUCTOR NANOLAMINATES - Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes oxide-conductor nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers. | 09-03-2009 |
20090236650 | TANTALUM LANTHANIDE OXYNITRIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film. | 09-24-2009 |
20090256181 | MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES - A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure. | 10-15-2009 |
20090294830 | MEMORY DEVICE WITH HIGH DIELECTRIC CONSTANT GATE DIELECTRICS AND METAL FLOATING GATES - A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are greater than silicon dioxide. Each memory cell has a plurality of doped source/drain regions in a substrate. A pair of transistors in a row are separated by an oxide isolation region comprising a low dielectric constant oxide material. A control gate is formed over the inter-gate insulator. | 12-03-2009 |
20090294924 | HAFNIUM LANTHANIDE OXYNITRIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium lanthanide oxynitride film. | 12-03-2009 |
20090314345 | ATOMIC LAYER DEPOSITED TITANIUM-DOPED INDIUM OXIDE FILMS - An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations and systems. The film of transparent conductive titanium-doped indium oxide may be structured as one or more monolayers. The film of transparent conductive titanium-doped indium oxide may be formed using atomic layer deposition. | 12-24-2009 |
20090315089 | ATOMIC LAYER DEPOSITED BARIUM STRONTIUM TITANIUM OXIDE FILMS - Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium titanium oxide layer, or a combination thereof. Embodiments of methods of fabricating such dielectric layers provide dielectric layers for use in a variety of devices. Embodiments include forming barium strontium titanium oxide film using atomic layer deposition. Embodiments include forming erbium-doped barium strontium titanium oxide film using atomic layer deposition. | 12-24-2009 |
20100006918 | HAFNIUM TANTALUM TITANIUM OXIDE FILMS - Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using atomic layer deposition. | 01-14-2010 |
20100014805 | ZINC OXIDE DIODES FOR OPTICAL INTERCONNECTIONS - The present disclosure includes methods, devices, and systems for zinc oxide diodes for optical interconnections. One system includes a ZnO emitter confined within a circular geometry in an oxide layer on a silicon substrate. An optical waveguide is formed in the oxide layer and has an input coupled to the ZnO emitter. A detector is coupled to an output of the optical waveguide. | 01-21-2010 |
20100027345 | ERASABLE NON-VOLATILE MEMORY DEVICE USING HOLE TRAPPING IN HIGH-K DIELECTRICS - A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control gate and a channel region of a transistor to trap positively charged holes. The multilayer charge trapping dielectric comprises at least one layer of high-K. | 02-04-2010 |
20100029054 | HAFNIUM TANTALUM OXIDE DIELECTRICS - A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers. | 02-04-2010 |
20100041244 | HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC - Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film. | 02-18-2010 |
20100044771 | Zr-Sn-Ti-O FILMS - A dielectric layer containing a Zr—Sn—Ti—O film and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO | 02-25-2010 |
20100052033 | LANTHANIDE YTTRIUM ALUMINUM OXIDE DIELECTRIC FILMS - Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by atomic layer deposition. | 03-04-2010 |
20100055871 | MEMORY IN LOGIC CELL - Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type. | 03-04-2010 |
20100067304 | WRITE ONCE READ ONLY MEMORY EMPLOYING CHARGE TRAPPING IN INSULATORS - Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. A plug couples the first source/drain region to an array plate. A bitline is coupled to the second source/drain region. The MOSFET can be programmed by operation in a reverse direction trapping charge in the gate insulator adjacent to the first source/drain region such that the programmed MOSFET operates at reduced drain source current when read in a forward direction. | 03-18-2010 |
20100173460 | VERTICAL TRANSISTOR, MEMORY CELL, DEVICE, SYSTEM AND METHOD OF FORMING SAME - A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the substrate and a body region and a second source/drain region are formed within the pillar. A first gate is coupled to a first side of the pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region. | 07-08-2010 |
20100176442 | STRUCTURES CONTAINING TITANIUM SILICON OXIDE - A dielectric containing a titanium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric provide a dielectric for use in a variety of electronic devices. Embodiments include a dielectric containing a titanium silicon oxide film arranged as one or more monolayers. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium silicon oxide film, and methods for forming such structures. | 07-15-2010 |
20100201388 | ELECTRICAL PROBE - Methods, devices, and systems for probing electrical circuits without loading the circuits are described herein. One embodiment of an electrical probe includes a coaxial cable having an inner conductor and an outer conductor, an extension portion of the inner conductor extending beyond the outer conductor at a probe end of the cable. The electrical probe includes a conductive whisker having a first portion separated from and extending a distance along the extension portion such that the first portion and the extension portion form a first capacitor and a second portion having a probe tip for receiving an input test signal from a circuit node under test. | 08-12-2010 |
20100207181 | CONDUCTIVE LAYERS FOR HAFNIUM SILICON OXYNITRIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a HfSiON film on a substrate for use in a variety of electronic systems. The HfSiON film may be structured as one or more monolayers. Electrodes to a dielectric containing a HfSiON may be structured as one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum. | 08-19-2010 |
20100216297 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES - Methods for fabricating semiconductor device structures are disclosed. In some embodiments, methods for fabricating semiconductor device structures may comprising forming at least one raised element on a surface of a substrate, the at least one raised element of the plurality including sloped sides and a peak, aligning a strip comprising conductive material at least partially over the at least one raised element, and at least partially securing the strip to a surface of the at least one raised element and the surface of the substrate. | 08-26-2010 |
20100224944 | RUTHENIUM FOR A DIELECTRIC CONTAINING A LANTHANIDE - A gate containing ruthenium for a dielectric having an oxide containing a lanthanide and a method of fabricating such a combination gate and dielectric produce a reliable structure for use in a variety of electronic devices. A ruthenium or a conductive ruthenium oxide gate may be formed on a lanthanide oxide. A ruthenium-based gate on a lanthanide oxide provides a gate structure that can effectively prevent a reaction between the gate and the lanthanide oxide. | 09-09-2010 |
20100237403 | ZrAlON FILMS - Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories. | 09-23-2010 |
20100244117 | NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS - An array of memory cells configured to store at least one bit per one F | 09-30-2010 |
20100244122 | MEMORY UTILIZING OXIDE NANOLAMINATES - Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers. | 09-30-2010 |
20100270590 | ALD OF SILICON FILMS ON GERMANIUM - The use of atomic layer deposition (ALD) to form a semiconductor structure of a silicon film on a germanium substrate is disclosed. An example embodiment includes a tantalum nitride gate electrode on a hafnium dioxide gate dielectric on the silicon film (TaN/HfO | 10-28-2010 |
20100270610 | NROM FLASH MEMORY DEVICES ON ULTRATHIN SILICON - An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top. | 10-28-2010 |
20100276748 | METHOD OF FORMING LUTETIUM AND LANTHANUM DIELECTRIC STRUCTURES - Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide. Specific methods shown include monolayer deposition which yields process improvements such as chemistry control, step coverage, crystallinity/microstructure control. | 11-04-2010 |
20100283537 | TANTALUM ALUMINUM OXYNITRIDE HIGH-K DIELECTRIC - Electronic apparatus and methods of forming the electronic apparatus may include a tantalum aluminum oxynitride film for use in a variety of electronic systems and devices. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film. | 11-11-2010 |
20100289559 | DRAM TUNNELING ACCESS TRANSISTOR - In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side at the top of the pillar. A second transistor is comprised of a second p+ source region doped into the second side of the top of the pillar and serially coupled to the top drain region for the first transistor. A second n+ drain region is doped into the substrate adjacent the pillar. Ultra-thin body layer run along each pillar sidewall between their respective active regions. A gate structure is formed along the pillar sidewalls and over the body layers. The transistors operate by electron tunneling from the source valence band to the gate bias-induced n-type channels, along the ultra-thin silicon bodies, thus resulting in a drain current. | 11-18-2010 |
20100301406 | ZIRCONIUM-DOPED TANTALUM OXIDE FILMS - Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices. | 12-02-2010 |
20100301428 | TANTALUM SILICON OXYNITRIDE HIGH-K DIELECTRICS AND METAL GATES - Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using a monolayer or partial monolayer sequencing process. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film. | 12-02-2010 |
20100330759 | NANOWIRE TRANSISTOR WITH SURROUNDING GATE - One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein. | 12-30-2010 |
20110014767 | LOW-TEMPERATURE GROWN HIGH QUALITY ULTRA-THIN CoTiO3 GATE DIELECTRICS - A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO | 01-20-2011 |
20110018045 | DRAM Arrays, Vertical Transistor Structures, and Methods of Forming Transistor Structures and DRAM Arrays - The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to form a source/drain region that extends less than an entirety of the trench width. The invention includes a semiconductor construction having a bit line disposed within a semiconductor substrate below a first elevation. A wordline extends elevationally upward from the first elevation and substantially orthogonal relative to the bit line. A vertical transistor structure is associated with the wordline. The transistor structure has a channel region laterally surrounded by a gate layer and is horizontally offset relative to the bit line. | 01-27-2011 |
20110037117 | LANTHANUM-METAL OXIDE DIELECTRIC APPARATUS, METHODS, AND SYSTEMS - Lanthanum-metal oxide dielectrics and methods of fabricating such dielectrics provide an insulating layer in a variety of structures for use in a wide range of electronic devices and systems. In an embodiment, a lanthanum-metal oxide dielectric is formed using a trisethylcyclopentadionatolanthanum precursor and/or a trisdipyvaloylmethanatolanthanum precursor. Additional apparatus, systems, and methods are disclosed. | 02-17-2011 |
20110037500 | INTEGRATED CIRCUIT COMPARATOR OR AMPLIFIER - An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit. | 02-17-2011 |
20110070717 | CAPACITORS AND METHODS WITH PRASEODYMIUM OXIDE INSULATORS - Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties. | 03-24-2011 |
20110121378 | ZrXHfYSn1-X-YO2 FILMS AS HIGH K GATE DIELECTRICS - The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO | 05-26-2011 |
20110121383 | MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES - A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration. | 05-26-2011 |
20110140106 | Backside naoscale texturing to improve IR response of silicon solar cells and photodetectors - The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing with diffusive scattering and with a smooth front surface of the solar cell results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy. | 06-16-2011 |
20110140184 | SURROUND GATE ACCESS TRANSISTORS WITH GROWN ULTRA-THIN BODIES - A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes. | 06-16-2011 |
20110163321 | NROM FLASH MEMORY DEVICES ON ULTRATHIN SILICON - An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top. | 07-07-2011 |
20110165744 | MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES - A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure. | 07-07-2011 |
20110169007 | STRUCTURES INCLUDING PASSIVATED GERMANIUM - A passivated germanium surface that is a germanium carbide material formed on and in contact with the termanium material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the passivated germanium having germanium carbide material thereon, are also disclosed. | 07-14-2011 |
20110204431 | FULLY DEPLETED SILICON-ON-INSULATOR CMOS LOGIC - A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects. | 08-25-2011 |
20110210379 | FIN-JFET - Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate. | 09-01-2011 |
20110220971 | PHOTOSENSITIVE IMAGING DEVICES AND ASSOCIATED METHODS - Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction. | 09-15-2011 |
20110227138 | Photosensitive Imaging Devices And Associated Methods - Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region. | 09-22-2011 |
20110248265 | Backside texturing by cusps to improve IR response of silicon solar cells and photodetectors - The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing comprises a plurality of cusped features providing diffusive scattering. Constructing the solar cell with a smooth front surface results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy. | 10-13-2011 |
20110248353 | METHODS OF FORMING STRAINED SEMICONDUCTOR CHANNELS - In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein. | 10-13-2011 |
20110260215 | GALLIUM LATHANIDE OXIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition. | 10-27-2011 |
20110272606 | ZINC OXIDE DIODES FOR OPTICAL INTERCONNECTIONS - The present disclosure includes methods, devices, and systems for zinc oxide diodes for optical interconnections. One system includes a ZnO emitter confined within a circular geometry in an oxide layer on a silicon substrate. An optical waveguide is formed in the oxide layer and has an input coupled to the ZnO emitter. A detector is coupled to an output of the optical waveguide. | 11-10-2011 |
20110275163 | Zr-SUBSTITUTED BaTiO3 FILMS - The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition (ALD), to form a zirconium substituted layer of barium titanium oxide (BaTiO | 11-10-2011 |
20110281407 | STRAINED SEMICONDUCTOR BY FULL WAFER BONDING - One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein. | 11-17-2011 |
20110287601 | METHODS OF FORMING A DIELECTRIC CONTAINING DYSPROSIUM DOPED HAFNIUM OXIDE - The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition, to form a dielectric layer of hafnium oxide doped with dysprosium and a method of fabricating such a combination produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure can include depositing hafnium oxide onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric layer of dysprosium doped hafnium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or as a dielectric in NROM devices, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of dysprosium doping is optimized improves memory function. | 11-24-2011 |
20110298028 | HAFNIUM TANTALUM TITANIUM OXIDE FILMS - Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as atomic layer deposition. | 12-08-2011 |
20110300701 | APPARATUS HAVING A DIELECTRIC CONTAINING SCANDIUM AND GADOLINIUM - Apparatus having a dielectric containing scandium and gadolinium can provide a reliable structure with a high dielectric constant (high k). In an embodiment, a monolayer or partial monolayer sequence process, such as for example atomic layer deposition (ALD), can be used to form a dielectric containing gadolinium oxide and scandium oxide. In an embodiment, a dielectric structure can be formed by depositing gadolinium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing scandium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric containing scandium and gadolinium may be used as gate insulator of a MOSFET, a capacitor dielectric in a DRAM, as tunnel gate insulators in flash memories, as a NROM dielectric, or as a dielectric in other electronic devices, because the high dielectric constant (high k) of the film provides the functionality of a much thinner silicon dioxide film. | 12-08-2011 |
20110308072 | OPEN PATTERN INDUCTOR - Various embodiments includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. Embedding the stacked open pattern inductor in a magnetic oxide or in an insulator and a magnetic material increases the inductance of the inductor and allows the magnetic flux to be confined to the area of the inductor. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems. | 12-22-2011 |
20120015488 | HIGH-K GATE DIELECTRIC OXIDE - A dielectric such as a gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide. | 01-19-2012 |
20120068272 | CONDUCTIVE LAYERS FOR HAFNIUM SILICON OXYNITRIDE - Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum. | 03-22-2012 |
20120074480 | METHOD OF FORMING LUTETIUM AND LANTHANUM DIELECTRIC STRUCTURES - Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide. Specific methods shown include monolayer deposition which yields process improvements such as chemistry control, step coverage, crystallinity/microstructure control. | 03-29-2012 |
20120074487 | APPARATUS CONTAINING COBALT TITANIUM OXIDE - Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition. | 03-29-2012 |
20120080676 | Backside nanoscale texturing to improve IR response of silicon solar cells and photodetectors - The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing with diffusive scattering and with a smooth front surface of the solar cell results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy. | 04-05-2012 |
20120080740 | CHARGE TRAPPING DIELECTRIC STRUCTURES - A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems. | 04-05-2012 |
20120088373 | METHODS OF FORMING TITANIUM SILICON OXIDE - A dielectric containing a titanium silicon oxide film and a method of fabricating such a dielectric provide a dielectric for use in a variety of electronic devices. Embodiments may include a dielectric containing a titanium silicon oxide film arranged as one or more monolayers. Embodiments may include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium silicon oxide film, and methods for forming such structures. | 04-12-2012 |
20120094477 | HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC - Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film. | 04-19-2012 |
20120108052 | ELECTRONIC APPARATUS CONTAINING LANTHANIDE YTTRIUM ALUMINUM OXIDE - Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by a monolayer or partial monolayer sequencing process such as using atomic layer deposition. | 05-03-2012 |
20120112251 | Reduction of random telegraph signal (RTS) and 1/f noise in silicon MOS devices, circuits, and sensors - The effects of random telegraph noise signal (RTS) or equivalently l/f noise on MOS devices, circuits, and sensors is described. Techniques are disclosed for minimizing this RTS and low frequency noise by minimizing the number of ionized impurity atoms in the wafer, substrate, well, pillar, or fin behind the channel of the MOS transistors. This noise reduction serves to reduce the errors in devices, sensors, and analog integrated circuits and error rates in digital integrated circuits and memories. | 05-10-2012 |
20120119279 | DRAM WITH NANOFIN TRANSISTORS - One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein. | 05-17-2012 |
20120122287 | LOCALIZED COMPRESSIVE STRAINED SEMICONDUCTOR - One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein. | 05-17-2012 |
20120133428 | DIELECTRICS CONTAINING AT LEAST ONE OF A REFRACTORY METAL OR A NON-REFRACTORY METAL - Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film. | 05-31-2012 |
20120146132 | MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES - A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration. | 06-14-2012 |
20120168855 | NANOWIRE TRANSISTOR WITH SURROUNDING GATE - One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein. | 07-05-2012 |
20120196448 | METHODS OF FORMING AN INSULATING METAL OXIDE - A dielectric containing an insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric produce a reliable dielectric for use in a variety of electronic devices. Embodiments include a titanium aluminum oxide film structured as one or more monolayers. Embodiments also include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium aluminum oxide film. | 08-02-2012 |
20120205720 | TANTALUM SILICON OXYNITRIDE HIGH-K DIELECTRICS AND METAL GATES - Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using a monolayer or partial monolayer sequencing process. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film. | 08-16-2012 |
20120276699 | MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES - A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure. | 11-01-2012 |
20120289016 | LOCALIZED COMPRESSIVE STRAINED SEMICONDUCTOR - One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein. | 11-15-2012 |
20120292619 | BACKSIDE TEXTURING BY CUSPS TO IMPROVE IR RESPONSE OF SILICON SOLAR CELLS AND PHOTODETECTORS - The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing comprises a plurality of cusped features providing diffusive scattering. Constructing the solar cell with a smooth front surface results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy. | 11-22-2012 |
20120313097 | FLASH MEMORY DEVICE HAVING A GRADED COMPOSITION, HIGH DIELECTRIC CONSTANT GATE INSULATOR - A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator comprises amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate. | 12-13-2012 |
20120313204 | Process Module for Increasing the Response of Backside Illuminated Photosensitive Imagers and Associated Methods - Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction. The dielectric region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction. | 12-13-2012 |
20120319105 | ZINC-TIN OXIDE THIN-FILM TRANSISTORS - Methods of forming transparent zinc-tin oxide structures are described. Devices that include transparent zinc-tin oxide structures as at least one of a channel layer in a transistor or a transparent film disposed over an electrical device that is at a substrate. | 12-20-2012 |
20130000544 | TITANIUM-DOPED INDIUM OXIDE FILMS - An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations and systems. The film of transparent conductive titanium-doped indium oxide may be structured as one or more monolayers. The film of transparent conductive titanium-doped indium oxide may be formed using atomic layer deposition. | 01-03-2013 |
20130001575 | METHODS FOR STRESSING TRANSISTOR CHANNELS OF A SEMICONDUCTOR DEVICE STRUCTURE, AND A RELATED SEMICONDUCTOR DEVICE STRUCTURE - The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed. | 01-03-2013 |
20130012031 | HAFNIUM TANTALUM OXIDE DIELECTRICS - A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers. | 01-10-2013 |
20130012034 | ZIRCONIUM-DOPED TANTALUM OXIDE FILMS - Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer can be formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices. | 01-10-2013 |
20130045578 | DEVICES AND METHODS TO IMPROVE CARRIER MOBILITY - Electronic apparatus and methods of forming the electronic apparatus include a silicon oxynitride layer on a semiconductor device for use in a variety of electronic systems. The silicon oxynitride layer may be structured to control strain in a silicon channel of the semiconductor device to modify carrier mobility in the silicon channel, where the silicon channel is configured to conduct current under appropriate operating conditions of the semiconductor device. | 02-21-2013 |
20130095645 | MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES - A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration. | 04-18-2013 |
20130112982 | METHOD FOR FORMING NANOFIN TRANSISTORS - One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin is formed from a crystalline substrate. A first source/drain region is formed in the substrate beneath the fin. A surrounding gate insulator is formed around the fin. A surrounding gate is formed around the fin and separated from the fin by the surrounding gate insulator. A second source/drain region is formed in a top portion of the fin. Various embodiments etch a hole in a layer over the substrate, form sidewall spacers in the hole, form a fin pattern from the sidewall spacers, and etch into the crystalline substrate to form the fin from the substrate using a mask corresponding to the fin pattern. Other aspects are provided herein. | 05-09-2013 |
20130122609 | Zr-SUBSTITUTED BaTiO3 FILMS - The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition (ALD), to form a zirconium substituted layer of barium titanium oxide, produces a reliable ferroelectric structure for use in a variety of electronic devices such as a dielectric in nonvolatile random access memories (NVRAM), tunable dielectrics for multi layer ceramic capacitors (MLCC), infrared sensors and electro-optic modulators. In various embodiments, structures can be formed by depositing alternating layers of barium titanate and barium zirconate by ALD on a substrate surface using precursor chemicals, and repeating to form a sequentially deposited interleaved structure of desired thickness and composition. The properties of the dielectric may be tuned by adjusting the percentage of zirconium to titanium to optimize properties such as a dielectric constant, Curie point, film polarization, ferroelectric property and a desired relaxor response. | 05-16-2013 |
20130153902 | STRUCTURES INCLUDING PASSIVATED GERMANIUM - A passivated germanium surface that is a germanium carbide material formed on and in contact with the germanium material. A semiconductor device structure having the passivated germanium having germanium carbide material on the substrate surface is also disclosed. | 06-20-2013 |
20130153986 | HIGH-K DIELECTRICS WITH GOLD NANO-PARTICLES - A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory device, a persistent memory device, a capacitor, as well as other devices and systems. The insulator layer may be formed using atomic layer deposition (ALD) to reduce the overall device thermal exposure. The insulator layer may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or semiconductor oxide oxycarbide, and the gold nano-particles in insulator layer increase the work function of the insulator layer and affect the tunneling current and the threshold voltage of the transistor. | 06-20-2013 |
20130168792 | Three Dimensional Architecture Semiconductor Devices and Associated Methods - Semiconductor devices having three dimensional (3D) architectures and methods form making such devices are provided. In one aspect, for example, a method for making a semiconductor device can include forming a device layer on a front side of a semiconductor layer that is substantially defect free, bonding a carrier substrate to the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a smart substrate to the processed surface. In some aspects, the method can also include removing the carrier substrate from the semiconductor layer to expose the device layer. | 07-04-2013 |
20130168803 | Semiconductor-On-Insulator Devices and Associated Methods - Semiconductor-on-insulator (SOI) devices and associated methods are provided. In one aspect, for example, a method for making a SOI device can include forming a device layer on a front side of a semiconductor layer, bonding a first substrate to the front side of the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a second substrate to the processed surface. In some aspects, the method can further include removing the first substrate from the front side to expose the device layer. In one aspect, forming the device layer can include forming optoelectronic circuitry at the front side of the semiconductor layer. | 07-04-2013 |
20130214847 | VERTICALLY BASE-CONNECTED BIPOLAR TRANSISTOR - Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor. | 08-22-2013 |
20130224916 | HAFNIUM TANTALUM TITANIUM OXIDE FILMS - Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in a transistor. An embodiment may include forming a hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as reaction sequence atomic layer deposition. | 08-29-2013 |
20130258756 | VERTICAL TRANSISTOR, MEMORY CELL, DEVICE, SYSTEM AND METHOD OF FORMING SAME - A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is fowled in the substrate and a body region and a second source/drain region are formed within the pillar. A first gate is coupled to a first side of the pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region. | 10-03-2013 |
20130264625 | COBALT TITANIUM OXIDE DIELECTRIC FILMS - Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition. | 10-10-2013 |
20130279259 | HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC - Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film. | 10-24-2013 |
20130292782 | MEMORY DEVICE HAVING A DIELECTRIC CONTAINING DYSPROSIUM DOPED HAFNIUM OXIDE - The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition, to form a dielectric layer of hafnium oxide doped with dysprosium and a method of fabricating such a combination produces a reliable structure for use in a variety of electronic devices. The dielectric structure can include hafnium oxide on a substrate surface followed by dysprosium oxide, and repeating to form a thin laminate structure. A dielectric layer of dysprosium doped hafnium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or as a dielectric in NROM devices. | 11-07-2013 |
20130313618 | FIN-JFET - Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate. | 11-28-2013 |
20140035101 | DIELECTRICS CONTAINING AT LEAST ONE OF A REFRACTORY METAL OR A NON-REFRACTORY METAL - Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film. | 02-06-2014 |
20140038401 | RUTHENIUM FOR A DIELECTRIC CONTAINING A LANTHANIDE - A gate containing ruthenium for a dielectric having an oxide containing a lanthanide and a method of fabricating such a combination gate and dielectric produce a reliable structure for use in a variety of electronic devices. A ruthenium or a conductive ruthenium oxide gate may be formed on a lanthanide oxide. A ruthenium-based gate on a lanthanide oxide provides a gate structure that can effectively prevent a reaction between the gate and the lanthanide oxide. | 02-06-2014 |
20140065806 | ELECTRONIC DEVICES INCLUDING BARIUM STRONTIUM TITANIUM OXIDE FILMS - Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium titanium oxide layer, or a combination thereof. Embodiments of methods of fabricating such dielectric layers provide dielectric layers for use in a variety of devices. Embodiments include forming barium strontium titanium oxide film using atomic layer deposition. Embodiments include forming erbium-doped barium strontium titanium oxide film using atomic layer deposition. | 03-06-2014 |
20140084355 | APPARATUS HAVING A DIELECTRIC CONTAINING SCANDIUM AND GADOLINIUM - Apparatus having a dielectric containing scandium and gadolinium can provide a reliable structure with a high dielectric constant (high k). In an embodiment, a monolayer or partial monolayer sequence process, such as for example atomic layer deposition (ALD), can be used to form a dielectric containing gadolinium oxide and scandium oxide. In an embodiment, a dielectric structure can be formed by depositing gadolinium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing scandium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric containing scandium and gadolinium may be used as gate insulator of a MOSFET, a capacitor dielectric in a DRAM, as tunnel gate insulators in flash memories, as a NROM dielectric, or as a dielectric in other electronic devices, because the high dielectric constant (high k) of the film provides the functionality of a much thinner silicon dioxide film. | 03-27-2014 |
20140138795 | CAPACITORS AND METHODS WITH PRASEODYMIUM OXIDE INSULATORS - Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties. | 05-22-2014 |
20140167186 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING STRAINED TRANSISTOR CHANNELS - The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed. | 06-19-2014 |
20140169103 | METHODS OF FORMING AND PROGRAMMING MEMORY DEVICES WITH ISOLATION STRUCTURES - Methods of programming and forming memory devices. Methods of programming include biasing a control gate of a selected memory cell of the memory device to a first voltage, the control gate being over a first conductive region having a first conductivity type and the first conductive region being over a second conductive region having a second conductivity type different than the first conductivity type; biasing the second conductive region to a second voltage to forward bias the junction from the second conductive region to the first conductive region; and injecting electrons into a charge-storage node of the selected memory cell from the second conductive region. The first conductive region and the second conductive region are contained within a dielectric isolation structure in which at least the selected memory cell is contained. | 06-19-2014 |
20140197509 | PHOTOSENSITIVE IMAGING DEVICES AND ASSOCIATED METHODS - Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction. | 07-17-2014 |
20140246651 | GROWN NANOFIN TRANSISTORS - One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallise the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The fin has a cross-sectional thickness in at least one direction less than a minimum feature size. The transistor body is formed in the crystallised semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein. | 09-04-2014 |
20140264555 | SILICON ON GERMANIUM - A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide. | 09-18-2014 |
20140306307 | BACKSIDE NANOSCALE TEXTURING TO IMPROVE IR RESPONSE OF SILICON SOLAR CELLS AND PHOTODETECTORS - The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing with diffusive scattering and with a smooth front surface of the solar cell results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy. | 10-16-2014 |
20140307059 | THREE DIMENSIONAL IMAGING UTILIZING STACKED IMAGER DEVICES AND ASSOCIATED METHODS - Stacked imager devices that can determine distance and generate three dimensional representations of a subject and associated methods are provided. In one aspect, an imaging system can include a first imager array having a first light incident surface and a second imager array having a second light incident surface. The second imager array can be coupled to the first imager array at a surface that is opposite the first light incident surface, with the second light incident surface being oriented toward the first imager array and at least substantially uniformly spaced. The system can also include a system lens positioned to direct incident light along an optical pathway onto the first light incident surface. The first imager array is operable to detect a first portion of the light passing along the optical pathway and to pass through a second portion of the light, where the second imager array is operable to detect at least a part of the second portion of light. | 10-16-2014 |
20140322923 | DIELECTRICS CONTAINING AT LEAST ONE OF A REFRACTORY METAL OR A NON-REFRACTORY METAL - Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film. | 10-30-2014 |
20140327065 | CONDUCTIVE LAYERS FOR HAFNIUM SILICON OXYNITRIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum. | 11-06-2014 |
20150035043 | CHARGE TRAPPING DIELECTRIC STRUCTURES - A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems. | 02-05-2015 |
20150035119 | CAPACITORS AND METHODS WITH PRASEODYMIUM OXIDE INSULATORS - Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties. | 02-05-2015 |