Patent application number | Description | Published |
20080278247 | Calibration of Voltage Controlled Oscillators - A calibration circuit ( | 11-13-2008 |
20080278252 | Calibration of Voltage Controlled Oscillators - A calibration circuit ( | 11-13-2008 |
20090015342 | Fast startup resonant element oscillator - A startup circuit | 01-15-2009 |
20090033298 | Voltage regulator with a hybrid control loop - A voltage regulator circuit and method are provided for regulating a voltage accurately in response to rapid variations in the regulator's load. The voltage regulator utilizes a hybrid loop; an embodiment of such utilization is exemplified by circuit | 02-05-2009 |
20090052099 | Hybrid Circuit for Circuit Protection and Switching - A hybrid circuit ( | 02-26-2009 |
20090052220 | ONE-TIME PROGRAMMABLE NON-VOLATILE MEMORY - An apparatus includes a semiconductor substrate, elongated diffused well regions, and elongated conductors. The semiconductor substrate has a first electrical conductivity type. The elongated diffused well regions are in the semiconductor substrate. The diffused well regions have a second electrical conductivity type opposite the first electrical conductivity type. Each of the elongated electrical conductors crosses the diffused well regions at respective locations of one-time programmable memory cells. Each of the memory cells includes a antifuse structure between the respective diffused well region and the respective electrical conductor. Each of the memory cells has a first state in which the antifuse structure has a first electrical resistance and a second state in which the antifuse structure has a second electrical resistance lower than the first electrical resistance. In the second state, each of the memory cells includes a rectifying junction between the respective diffused well region and the respective electrical conductor. | 02-26-2009 |
20090195946 | Electrostatic Discharge Protection Using an Intrinsic Inductive Shunt - In one embodiment of the present invention, an electrostatic discharge protection circuit provides efficient electrostatic discharge protection to an RFIC. The circuit includes several parts such as an inductor coupled from a first rail to an internal node. A power amplifier transistor having a transconductance control node is coupled to internal circuitry, a first terminal coupled to a second rail, and a second terminal coupled to an internal node. The circuit also comprises a pad coupled to an internal node, and this pad is capable of being coupled to off chip systems such as an antenna. The power amplifier transistor serves as the active device for an RF power amplifier. The inductor serves as one of either a bias inductor or a tank inductor for the RF power amplifier. Additionally the inductor acts as a low impedance path to the first rail to protect the power amplifier transistor during an ESD pulse. | 08-06-2009 |
20090197557 | Differential diversity antenna - A differential diversity antenna is provided. In one embodiment, a differential diversity antenna is used in a wireless system comprising receiver circuitry. (and, in another embodiment, transmission circuitry). The differential diversity antenna comprises a plurality of antenna components that are aligned non-collinearly to achieve diversity. In another embodiment, the differential diversity antenna is used with a second differential diversity antenna. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination. | 08-06-2009 |
20090207824 | Wireless Access Point Device - A wireless (such as Wi-Fi or similar) access point is included in or attached to a device, such as a cellular phone, WiMAX device, other mobile device, etc. One or more wireless units wirelessly access a communication network (and in some cases the Internet) through the wireless access point device. Additionally, such a wireless access point device can receive a transmission from a wireless tag that has been attached to an object to be monitored and can forward information from the wireless tag to a target device along with location information. | 08-20-2009 |
20090216964 | VIRTUAL MEMORY INTERFACE - The embodiments that are described herein provide random access to individual data storage locations of a group of buffers, which may be scattered in the memory. These embodiments provide a virtual memory interface that applies virtual addresses in a flat memory linear addressing space as indices into the physical memory addresses that are ordered into a sequence in accordance with the group of buffers. In this way, these embodiments enable a device (e.g., a processor) to directly and sequentially access all of the scattered physical memory locations of a fragmented data item, such as a packet, without having to perform any memory segmentation or paging processes. In some embodiments, these accesses include both read and write accesses to the scattered data storage locations. | 08-27-2009 |
20090278517 | Regulator with Device Performance Dynamic Mode Selection - A voltage regulator device and accompanying methods are provided for providing efficient voltage regulation to an electronic device. Efficient regulator | 11-12-2009 |
20130173970 | MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-TESTING AND BACKGROUND BUILT-IN SELF-REPAIR - A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks. | 07-04-2013 |
20140317460 | MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-REPAIR USING BACKGROUND BUILT-IN SELF-TESTING - A memory device with a background built-in self-repair module (BBISRM) includes a main memory, an arbiter, and a redundant memory to repair a target memory under test (TMUT). The memory device also includes a background built-in self-test module (BBISTM) to identify portions of memory needing background built-in self-repair (BBISR). The BBISRM or the BBISTM can operate simultaneously while the memory device is operational for performing external accesses during field operation. The BBISR can detect and correct a single data bit error in the data stored in the TMUT. The arbiter configured to receive a read or write access memory request including a memory address, to determine if the memory address of the read or write access memory request matches the memory address mapped to the selected portion of the redundant memory, and to read or write data from the selected portion of the redundant memory, respectively. | 10-23-2014 |