Patent application number | Description | Published |
20080203408 | PROCESS FOR PRODUCING (Al, Ga)lnN CRYSTALS - The present invention relates to a novel process for producing (Al, Ga)InN and AlGaInN single crystals by means of a modified HVPE process, and also to (Al, Ga)InN and AlGaInN bulk crystals of high quality, in particular homogeneity. | 08-28-2008 |
20080203409 | PROCESS FOR PRODUCING (Al, Ga)N CRYSTALS - The present invention relates to a novel process for producing (Al, Ga)N and AlGaN single crystals by means of a modified HVPE process, and also to (Al, Ga)N and AlGaN single crystals of high quality. | 08-28-2008 |
20080213543 | Method and device for manufacturing semiconductor compound materials by means of vapour phase epitaxy - A semiconductor compound material, preferably a III-N-bulk crystal or a III-N-layer, is manufactured in a reactor by means of hydride vapour phase epitaxy (HVPE), wherein in a mixture of carrier gases a flow profile represented by local mass flow rates is formed in the reactor. The mixture can carry one or more reaction gases towards a substrate. Thereby, a concentration of hydrogen important for the reaction and deposition of reaction gases is adjusted at the substrate surface independently from the flow profile simultaneously formed in the reactor. | 09-04-2008 |
20100019352 | PROCESS FOR SMOOTHENING III-N SUBSTRATES - A process for preparing smoothened III-N, in particular smoothened III-N substrate or III-N template, wherein III denotes at least one element of group III of the Periodic System, selected from Al, Ga and In, utilizes a smoothening agent comprising cubic boron nitride abrasive particles. The process provides large-sized III-N substrates or III-N templates having diameters of at least 40 mm, at a homogeneity of very low surface roughness over the whole substrate or wafer surface. In a mapping of the wafer surface with a white light interferometer, the standard deviation of the rms-values is 5% or lower, with a very good crystal quality at the surface or in surface-near regions, measurable, e.g., by means of rocking curve mappings and/or micro-Raman mappings. | 01-28-2010 |
20120021163 | METHOD AND DEVICE FOR MANUFACTURING SEMICONDUCTOR COMPOUND MATERIALS BY MEANS OF VAPOUR PHASE EPITAXY - A semiconductor compound material, preferably a III-N-bulk crystal or a III-N-layer, is manufactured in a reactor by means of hydride vapour phase epitaxy (HVPE), wherein in a mixture of carrier gases a flow profile represented by local mass flow rates is formed in the reactor. The mixture can carry one or more reaction gases towards a substrate. Thereby, a concentration of hydrogen important for the reaction and deposition of reaction gases is adjusted at the substrate surface independently from the flow profile simultaneously formed in the reactor. | 01-26-2012 |
20140151716 | PROCESS FOR THE MANUFACTURE OF A DOPED III-N BULK CRYSTAL AND A FREE-STANDING III-N SUBSTRATE, AND DOPED III-N BULK CRYSTAL AND FREE-STANDING III-N SUBSTRATE AS SUCH - A process for producing a doped III-N bulk crystal, wherein III denotes at least one element of the main group III of the periodic system, selected from Al, Ga and In, wherein the doped crystalline III-N layer or the doped III-N bulk crystal is deposited on a substrate or template in a reactor, and wherein the feeding of at least one dopant into the reactor is carried out in admixture with at least one group III material. In this manner, III-N bulk crystals and III-N single crystal substrates separated therefrom can be obtained with a very homogeneous distribution of dopants in the growth direction as well as in the growth plane perpendicular thereto, a very homogeneous distribution of charge carriers and/or of the specific electric resistivity in the growth direction as well as in the growth plane perpendicular thereto, and a very good crystal quality. | 06-05-2014 |
Patent application number | Description | Published |
20080290419 | LOW ON RESISTANCE CMOS TRANSISTOR FOR INTEGRATED CIRCUIT APPLICATIONS - An array of power transistors on a semiconductor chip has serpentine gates separated by alternating source and drain regions. The gates combine rounded ends and rectangular sections joining the rounded ends. This geometry allows the metallization, in which the upper and lower metal layers are substantially congruent with each other, to have a design width that can be increased or decreased with the changes in width matched by the length of the rectangular sections thus allowing flexibility in the design of the power transistors. | 11-27-2008 |
20090250765 | LOW ON RESISTANCE CMOS "WAVE" TRANSISTOR FOR INTEGRATED CIRCUIT APPLICATIONS - In one embodiment of the present invention an array of power transistors on a semiconductor chip has repeating patterns of two “wave” gates which have alternating longer and shorter horizontal sections which are offset mirror images of each other together with a third straight horizontal section. Alternating source and drain regions lie between adjacent gates. Contacts are located adjacent each side of sections of the “wave” gates which connect the ends of the horizontal sections of the “wave” gates. | 10-08-2009 |
20100323485 | PN JUNCTION AND MOS CAPACITOR HYBRID RESURF TRANSISTOR - A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate with a drift region between source region and drain regions. The drift region includes a structure having a spaced trench capacitor extending between the source region and the drain region and a vertical stack extending between the source region and the drain region. When the device is in an on state, current flows between the source and drain regions; and, when the device is in an off/blocking state, the drift region is depleted into the stack. | 12-23-2010 |
20140120694 | USE OF PLATE OXIDE LAYERS TO INCREASE BULK OXIDE THICKNESS IN SEMICONDUCTOR DEVICES - Semiconductor devices and methods for making such devices are described. The semiconductor devices are made by providing a semiconductor substrate with an active region, providing a bulk oxide layer in a non-active portion of the substrate, the bulk oxide layer having a first thickness in a protected area of the device, providing a plate oxide layer over the bulk oxide layer and over the substrate in the active region, forming a gate structure on the active region of the substrate, and forming a self-aligned silicide layer on a portion of the substrate and the gate structure, wherein the final thickness of the bulk oxide layer in the protected area after these processes remains substantially the same as the first thickness. The thickness of the bulk oxide layer can be increased without any additional processing steps or any additional processing cost. Other embodiments are described. | 05-01-2014 |
20140213024 | PRODUCTION OF MULTIPLE SEMICONDUCTOR DEVICES USING A SEMICONDUCTOR PROCESS - In one general aspect, a method can include implanting a first dopant, simultaneously, in a portion of a laterally diffused metal oxide semiconductor (LDMOS) device and in a portion of a resistor device included in a semiconductor device. The method can also include implanting a second dopant, simultaneously, in a portion of the LDMOS device and in a portion of a bipolar junction transistor (BJT) device in the semiconductor device. | 07-31-2014 |
20140231911 | LDMOS DEVICE WITH DOUBLE-SLOPED FIELD PLATE - In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric The end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate. | 08-21-2014 |
20140231952 | PRODUCTION OF HIGH-PERFORMANCE PASSIVE DEVICES USING EXISTING OPERATIONS OF A SEMICONDUCTOR PROCESS - In one general aspect, a semiconductor processing method can include forming an N-type silicon region disposed within a P-type silicon substrate. The method can also include forming a field oxide (FOX) layer in the P-type silicon substrate where the FOX layer includes an opening exposing at least a portion of the N-type silicon region. The method can further include forming a reduced surface field (RESURF) oxide (ROX) layer having a first portion disposed on the exposed N-type silicon region and a second portion disposed on the FOX layer where the ROX layer includes a first dielectric layer in contact with the exposed N-type silicon region and a second dielectric layer disposed on the first dielectric layer. The method can further include forming a doped polysilicon layer having a first portion disposed on the first portion of the ROX layer and a second portion disposed on the second portion of the ROX layer. | 08-21-2014 |