Patent application number | Description | Published |
20080277799 | LOW TEMPERATURE METHODS OF FORMING BACK SIDE REDISTRIBUTION LAYERS IN ASSOCIATION WITH THROUGH WAFER INTERCONNECTS, SEMICONDUCTOR DEVICES INCLUDING SAME, AND ASSEMBLIES - Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the active surface devices of a semiconductor substrate using through wafer interconnects (TWIs). The TWIs may be formed prior to forming the RDLs, after forming the RDLs, or substantially simultaneously to forming the RDLs. The material for the back side RDLs and various other associated materials, such as dielectrics and conductive via filler materials, are processed at temperatures sufficiently low so as to not damage the semiconductor devices or associated components contained on the active surface of the semiconductor substrate. The low temperature processed back side RDLs of the present invention may be employed with optically interactive semiconductor devices and semiconductor memory devices, among many others. Semiconductor devices employing the RDLs of the present invention may be stacked and electrically connected theretogether. | 11-13-2008 |
20080290435 | WAFER LEVEL LENS ARRAYS FOR IMAGE SENSOR PACKAGES AND THE LIKE, IMAGE SENSOR PACKAGES, AND RELATED METHODS - Image sensor packages, lenses therefore, and methods for fabrication are disclosed. A substrate having through-hole vias may be provided, and an array of lenses may be formed in the vias. The lenses may be formed by molding or by tenting material over the vias. An array of lenses may provide a color filter array (CFA). Filters of the CFA may be formed in the vias, and lenses may be formed in or over the vias on either side of the filters. A substrate may include an array of microlenses, and each microlens of the array may correspond to a pixel of an associated image sensor. In other embodiments, each lens of the array may correspond to an imager array of an image sensor. A wafer having an array of lenses may be aligned with and attached to an imager wafer comprising a plurality of image sensor dice, then singulated to form a plurality of image sensor packages. | 11-27-2008 |
20080293179 | Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers - Microelectronic imagers with integrated optical devices and methods for manufacturing imagers. The imagers, for example, typically have an imaging unit including a first substrate and an image sensor on and/or in the first substrate. An embodiment of an optical device includes a stand-off having a compartment configured to contain the image sensor. The stand-off has a coefficient of thermal expansion at least substantially the same as that of the first substrate. The optical device can further include an optics element in alignment with the compartment of the stand-off. The stand-off can be formed by etching a compartment into a silicon wafer or a wafer of another material having a coefficient of thermal expansion at least substantially the same as that of the substrate upon which the image sensor is formed. The optics elements can be formed integrally with the stand-offs or separately attached to a cover supported by the stand-offs. | 11-27-2008 |
20090042360 | STRAINED SEMICONDUCTOR BY FULL WAFER BONDING - One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein. | 02-12-2009 |
20090090850 | Deep Recess Color Filter Array and Process of Forming the Same - Self-aligned color filter array and methods of forming same. Embodiments include an image sensor having a substrate with a fabrication element having a first recess, the first recess having a second recess, a color filter formed in the second recess, and a microlens formed over the color filter. | 04-09-2009 |
20090155949 | MICROELECTRONIC IMAGERS WITH OPTICAL DEVICES AND METHODS OF MANUFACTURING SUCH MICROELECTRONIC IMAGERS - Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports. | 06-18-2009 |
20090176362 | METHODS OF FORMING INTERCONNECTS IN A SEMICONDUCTOR STRUCTURE - A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed. | 07-09-2009 |
20090189238 | PACKAGED MICROELECTRONIC IMAGERS AND METHODS OF PACKAGING MICROELECTRONIC IMAGERS - Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends partially through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending partially through the substrate to the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, a conductive layer deposited onto at least a portion of the dielectric liner, a wetting agent deposited onto at least a portion of the conductive layer, and a conductive fill material deposited into the passage and electrically coupled to the bond-pad. | 07-30-2009 |
20090191701 | MICROELECTRONIC DEVICES AND METHODS FOR FORMING INTERCONNECTS IN MICROELECTRONIC DEVICES - Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material. | 07-30-2009 |
20090200633 | SEMICONDUCTOR STRUCTURES WITH DUAL ISOLATION STRUCTURES, METHODS FOR FORMING SAME AND SYSTEMS INCLUDING SAME - A semiconductor structure with dual isolation structures is disclosed. The semiconductor structure may include a protruding isolation structure in a pixel array region of a substrate and an embedded isolation structure in a peripheral device region of the same substrate. A region of the protruding isolation structure extends from an upper surface of the substrate, while another region of the protruding isolation structure may, optionally, be embedded within the substrate. The embedded isolation structure is formed within the substrate and includes an upper surface that is substantially coplanar with the upper surface of the substrate. A method of forming the semiconductor structure with dual isolation structure is also disclosed. | 08-13-2009 |
20090230087 | MICROELECTRONIC IMAGERS WITH INTEGRATED OPTICAL DEVICES AND METHODS FOR MANUFACTURING SUCH MICROELECTRONIC IMAGERS - Microelectronic imagers with integrated optical devices and methods for manufacturing imagers. The imagers, for example, typically have an imaging unit including a first substrate and an image sensor on and/or in the first substrate. An embodiment of an optical device includes a stand-off having a compartment configured to contain the image sensor. The stand-off has a coefficient of thermal expansion at least substantially the same as that of the first substrate. The optical device can further include an optics element in alignment with the compartment of the stand-off. The stand-off can be formed by etching a compartment into a silicon wafer or a wafer of another material having a coefficient of thermal expansion at least substantially the same as that of the substrate upon which the image sensor is formed. The optics elements can be formed integrally with the stand-offs or separately attached to a cover supported by the stand-offs. | 09-17-2009 |
20090231475 | METHOD AND APPARATUS FOR BREAKING SURFACE TENSION DURING A RECESSED COLOR FILTER ARRAY PROCESS - A method of making a color filter array of an imaging device comprises forming a main recess for a color filter array, forming a tension breaking feature at an edge of the main recess, and providing a color filter array material across the tension breaking feature and main recess as part of forming the color filter array. The tension breaking feature reduces the settling distance of the color filter array material. An imaging device having the thus formed color filter array is also described. | 09-17-2009 |
20090309142 | IMAGER DEVICES HAVING DIFFERING GATE STACK SIDEWALL SPACERS, METHOD FOR FORMING SUCH IMAGER DEVICES, AND SYSTEMS INCLUDING SUCH IMAGER DEVICES - Imager devices have a sensor array and a peripheral region at least partially surrounding the sensor array. At least one transistor in the peripheral region has a gate stack sidewall spacer that differs in composition from a gate stack sidewall spacer on at least one transistor in the sensor array. Imaging systems include such an imager device configured to communicate electrically with at least one electronic signal processor and at least one memory storage device. Methods of forming such imager devices include providing layers of oxide and nitride materials over transistors on a workpiece, and using etching processes to form gate stack sidewall spacers on the transistors. | 12-17-2009 |
20090309176 | METHODS FOR PROTECTING IMAGING ELEMENTS OF PHOTOIMAGERS DURING BACK SIDE PROCESSING, PHOTOIMAGERS AND SYSTEMS - Methods for processing photoimagers include forming one or more protective layers over the image sensing elements of a photoimager. Protective layers may facilitate thinning of the substrates of photoimagers, as well as prevent contamination of the image sensing elements and associated optical features during back side processing of the photoimagers. Blind vias, which extend from the back side of a photoimager to bond pads carried by an active surface of the photoimager, may be formed through the back side. The vias may be filled with conductive material and, optionally, redistribution circuitry may be fabricated over the back side of the photoimager. Photoimagers including features at result from such processes are also disclosed. | 12-17-2009 |
20090309222 | METHOD AND SEMICONDUCTOR DEVICE HAVING COPPER INTERCONNECT FOR BONDING - An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad. | 12-17-2009 |
20090321061 | METHODS AND APPARATUSES FOR TRANSFERRING HEAT FROM STACKED MICROFEATURE DEVICES - Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support member having terminals and a first microelectronic die having first external contacts carried by the support member. The first external contacts are operatively coupled to the terminals on the support member. The assembly also includes a second microelectronic die having integrated circuitry and second external contacts electrically coupled to the first external contacts. The first die is between the support member and the second die. The assembly can further include a heat transfer unit between the first die and the second die. The heat transfer unit includes a first heat transfer portion, a second heat transfer portion, and a gap between the first and second heat transfer portions such that the first external contacts and the second external contacts are aligned with the gap. | 12-31-2009 |
20100025746 | METHODS, STRUCTURES AND SYSTEMS FOR INTERCONNECT STRUCTURES IN AN IMAGER SENSOR DEVICE - Methods, structures and systems for a substantially non-light blocking conductive interconnect structure for an imager sensor device. | 02-04-2010 |
20100171217 | THROUGH-WAFER INTERCONNECTS FOR PHOTOIMAGER AND MEMORY WAFERS - A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths. | 07-08-2010 |
20110074043 | METHOD OF FORMING VIAS IN SEMICONDUCTOR SUBSTRATES AND RESULTING STRUCTURES - Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from a back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via. | 03-31-2011 |
20110089539 | PACKAGED MICROELECTRONIC IMAGERS AND METHODS OF PACKAGING MICROELECTRONIC IMAGERS - Methods for forming electrically conductive through-wafer interconnects in microelectronic devices and microelectronic devices are disclosed herein. In one embodiment, a microelectronic device can include a monolithic microelectronic substrate with an integrated circuit has a front side with integrated circuit interconnects thereon. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad. | 04-21-2011 |
20110095429 | METHODS FOR FABRICATING AND FILLING CONDUCTIVE VIAS AND CONDUCTIVE VIAS SO FORMED - Methods for forming conductive vias include foiling one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof A barrier layer may be fowled over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed. | 04-28-2011 |
20110136336 | METHODS OF FORMING CONDUCTIVE VIAS - Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer. | 06-09-2011 |
20110189809 | ELEVATED POCKET PIXELS, IMAGING DEVICES AND SYSTEMS INCLUDING THE SAME AND METHOD OF FORMING THE SAME - An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including, but not limited to, v-shaped, u-shaped, or other shaped features. Light sensors having such an indentation feature can redirect incident light that is not absorbed by one portion of the photosensor to another portion of the photosensor for additional absorption. In addition, the elevated photosensors reduce the size of the pixel cells while reducing leakage, image lag, and barrier problems. | 08-04-2011 |
20110233777 | THROUGH-WAFER INTERCONNECTS FOR PHOTOIMAGER AND MEMORY WAFERS - A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths. | 09-29-2011 |
20110272806 | SEMICONDUCTOR DICE INCLUDING AT LEAST ONE BLIND HOLE, WAFERS INCLUDING SUCH SEMICONDUCTOR DICE, AND INTERMEDIATE PRODUCTS MADE WHILE FORMING AT LEAST ONE BLIND HOLE IN A SUBSTRATE - Semiconductor dice comprise at least one bond pad on an active surface of the semiconductor die. At least one blind hole extends from a back surface of the semiconductor die opposing the active surface, through a thickness of the semiconductor die, to an underside of the at least one bond pad. At least one quantity of passivation material covers at least a sidewall surface of the at least one blind hole. At least one conductive material is disposed in the at least one blind hole adjacent and in electrical communication with the at least one bond pad and adjacent the at least one quantity of passivation material. | 11-10-2011 |
20110281407 | STRAINED SEMICONDUCTOR BY FULL WAFER BONDING - One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein. | 11-17-2011 |
20120009717 | PACKAGED MICROELECTRONIC IMAGERS AND METHODS OF PACKAGING MICROELECTRONIC IMAGERS - Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends partially through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending partially through the substrate to the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, a conductive layer deposited onto at least a portion of the dielectric liner, a wetting agent deposited onto at least a portion of the conductive layer, and a conductive fill material deposited into the passage and electrically coupled to the bond-pad. | 01-12-2012 |
20120104528 | WAFER-LEVEL PACKAGED MICROELECTRONIC IMAGERS AND PROCESSES FOR WAFER-LEVEL PACKAGING - The following disclosure describes several embodiments of (1) methods for wafer-level packaging of microelectronic imagers, (2) methods of forming electrically conductive interconnects in microelectronic imagers, (3) methods for forming optical devices for microelectronic imagers, and (4) microelectronic imagers that have been packaged using wafer-level packaging processes. Wafer-level packaging of microelectronic imagers is expected to significantly enhance the efficiency of manufacturing microelectronic imagers because a plurality of imagers can be packaged simultaneously using highly accurate and efficient processes developed for packaging semiconductor devices. Moreover, wafer-level packaging of microelectronic imagers is expected to enhance the quality and performance of such imagers because the semiconductor fabrication processes can reliably align an optical device with an image sensor and space the optical device apart from the image sensor by a desired distance with a higher degree of precision. | 05-03-2012 |
20120135567 | METHODS AND APPARATUSES FOR TRANSFERRING HEAT FROM STACKED MICROFEATURE DEVICES - Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support member having terminals and a first microelectronic die having first external contacts carried by the support member. The first external contacts are operatively coupled to the terminals on the support member. The assembly also includes a second microelectronic die having integrated circuitry and second external contacts electrically coupled to the first external contacts. The first die is between the support member and the second die. The assembly can further include a heat transfer unit between the first die and the second die. The heat transfer unit includes a first heat transfer portion, a second heat transfer portion, and a gap between the first and second heat transfer portions such that the first external contacts and the second external contacts are aligned with the gap. | 05-31-2012 |
20130043588 | SEMICONDUCTOR DICE INCLUDING AT LEAST ONE BLIND HOLE, WAFERS INCLUDING SUCH SEMICONDUCTOR DICE, AND INTERMEDIATE PRODUCTS MADE WHILE FORMING AT LEAST ONE BLIND HOLE IN A SUBSTRATE - Semiconductor dice comprise at least one bond pad on an active surface of the semiconductor die. At least one blind hole extends from a back surface of the semiconductor die opposing the active surface, through a thickness of the semiconductor die, to an underside of the at least one bond pad. At least one quantity of passivation material covers at least a sidewall surface of the at least one blind hole. At least one conductive material is disposed in the at least one blind hole adjacent and in electrical communication with the at least one bond pad and adjacent the at least one quantity of passivation material. | 02-21-2013 |
20130295766 | THROUGH-WAFER INTERCONNECTS FOR PHOTOIMAGER AND MEMORY WAFERS - A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths. | 11-07-2013 |
20140154879 | METHODS OF FORMING INTERCONNECTS AND SEMICONDUCTOR STRUCTURES - A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed. | 06-05-2014 |
20150014689 | ELEVATED POCKET PIXELS, IMAGING DEVICES AND SYSTEMS INCLUDING THE SAME AND METHOD OF FORMING THE SAME - An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including, but not limited to, v-shaped, u-shaped, or other shaped features. Light sensors having such an indentation feature can redirect incident light that is not absorbed by one portion of the photosensor to another portion of the photosensor for additional absorption. In addition, the elevated photosensors reduce the size of the pixel cells while reducing leakage, image lag, and barrier problems. | 01-15-2015 |