Patent application number | Description | Published |
20090201320 | TEMPORAL FILTERING OF VIDEO SIGNALS - A process for reducing noise and temporal artifacts (e.g. walking LEDs) on a dual modulation display system by applying temporal filtering to rear modulation signals of a sequence of video frames. Flare and dimming rates are calculated for a current frame in the video. If a flare rate threshold is exceeded, an intensity of the backlight is limited to a predetermined flare rate. If a dimming rate threshold is exceeded, the backlight intensity is limited to a predetermined dimming rate. The limitations are applied, for example, on an element-by-element basis. In the event of a scene change, the limitations do not need to be applied. A forward modulation signal is calculated by taking into account any applied backlight limitations. | 08-13-2009 |
20110305391 | Image Processing and Displaying Methods for Devices that Implement Color Appearance Models - Embodiments of the invention relate generally to image and display processing, and more particularly, to systems, apparatuses, integrated circuits, computer-readable media, and methods that facilitate the prediction of the appearance of color in images for different viewing environments, including high dynamic range images. In some embodiments a method can modify color associated with a source environment at a target environment. The method can include applying different non-linear functions to transform subsets of data representing a color of a sample at the source environment into transformed subsets of data, and generating data representing a chroma correlate as an appearance correlate independent of data representing a hue-related correlate. The chroma correlate can be configured to generate the color at a device at the target environment. | 12-15-2011 |
20120038693 | High Dynamic Range Projection System - Embodiments relate generally to computer-based image processing, and more particularly, to systems, computer-readable media, methods, integrated circuits, and apparatuses to facilitate operation of a projection system with relatively high dynamic range output by, among other things, providing subsets of light patterns along an optical path during respective first and second temporal fields associated with respective first and second illuminants. The projection system can synthesize color for projectable images by combining or otherwise using the subsets of light patterns with an array of color elements to produce projectable images with color in at least the visible spectrum. | 02-16-2012 |
20120212707 | Multi-Segment Imager - Several embodiments of projection systems are disclosed that comprise a plurality of controllable emitters, each said emitter providing light for a light path; a plurality of first optical elements, each said first optical element receiving light from one of said emitters; a controllable modulator receiving light from said plurality of first optical elements; a plurality of conduits, each said conduit disposed over a portion of said controllable modulator; a plurality of second optical elements, each of said second optical elements receiving light from at least one of said plurality of conduits, and a controller for sending control signals to said controllable emitters and said controllable modulator. The illumination from the emitters may form a plurality of overlapping areas of illumination upon a projection screen where the image is intended to be formed. | 08-23-2012 |
20120256941 | Local Definition of Global Image Transformations - A global image adjustment, such as dynamic range adjustment is established based on image characteristics. The image adjustment is based more heavily on pixel values in image areas identified as being important by one or more saliency mapping algorithms. In one application to dynamic range adjustment, a saliency map is applied to create a weighed histogram and a transformation is determined from the weighted histogram. Artifacts typical of local adjustment schemes may be avoided. | 10-11-2012 |
20120320342 | Multi-Segment Imager - Several embodiments of projection systems are disclosed that comprise a plurality of controllable emitters, each said emitter providing light for a light path; a plurality of first optical elements, each said first optical element receiving light from one of said emitters; a controllable modulator receiving light from said plurality of first optical elements; a plurality of conduits, each said conduit disposed over a portion of said controllable modulator; a plurality of second optical elements, each of said second optical elements receiving light from at least one of said plurality of conduits, and a controller for sending control signals to said controllable emitters and said controllable modulator. The illumination from the emitters may form a plurality of overlapping areas of illumination upon a projection screen where the image is intended to be formed. | 12-20-2012 |
20130038790 | Display Management Methods and Apparatus - Apparatus and methods for mapping video signal parameters such as tone and color may be applied at various points in a video generation and delivery pipeline. apparatus may be configured to control mappings based on a range of inputs which may include one or more of: ambient conditions, user inputs, control information, adaptation models. Apparatus and methods may be applied to display video or other images so as to preserve a creative intent embodied in video or other image data. | 02-14-2013 |
20140002737 | Generating Alternative Versions of Image Content Using Histograms | 01-02-2014 |
20140043352 | High Luminance Projection Displays And Associated Methods - Projection displays include a highlight projector and a main projector. Highlights projected by the highlight projector boost luminance in highlight areas of a base image projected by the main projector. Various highlight projectors including steerable beams, holographic projectors and spatial light modulators are described. | 02-13-2014 |
20140160143 | Method of Adapting a Source Image Content to a Target Display - Source image content is adapted to a target display. Target image content associated with the target display is provided. A histogram is computed for the target image content. A prominent feature present in the target histogram is determined. A histogram is computed for the source image content. The source content histogram is manipulated to reflect the determined target histogram prominent feature(s). Adapted source image content is generated based on the manipulated source histograms(s). Another prominent feature present in the target histogram is determined. The source histogram is further manipulated to reflect the other prominent determined target histogram features. Further adapted source image content is generated based on the further manipulated source histogram if the adapted source image content has insufficient image quality and perceptual color characteristics. | 06-12-2014 |
20150084978 | LOCAL DEFINITION OF GLOBAL IMAGE TRANSFORMATIONS - A global image adjustment, such as dynamic range adjustment is established based on image characteristics. The image adjustment is based more heavily on pixel values in image areas identified as being important by one or more saliency mapping algorithms. In one application to dynamic range adjustment, a saliency map is applied to create a weighed histogram and a transformation is determined from the weighted histogram. Artifacts typical of local adjustment schemes may be avoided. | 03-26-2015 |
Patent application number | Description | Published |
20080277775 | Ultra-thin near-hermetic package based on rainier - A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals. | 11-13-2008 |
20090071707 | Multilayer substrate with interconnection vias and method of manufacturing the same - A method is provided for manufacturing a multilayer substrate. An insulating layer can have a hole overlying a patterned second metal layer. In turn, the second metal layer can overlie a first metal layer. A third metal layer can be electroplated onto the patterned second metal layer within the hole, the third metal layer extending from the second metal layer onto a wall of the hole. When plating the third metal layer, the first and second metal layers can function as a conductive commoning element. | 03-19-2009 |
20100193970 | MICRO PIN GRID ARRAY WITH PIN MOTION ISOLATION - A microelectronic package includes a microelectronic element having faces and contacts, a flexible substrate overlying and spaced from a first face of the microelectronic element, and a plurality of conductive terminals exposed at a surface of the flexible substrate. The conductive terminals are electrically interconnected with the microelectronic element and the flexible substrate includes a gap extending at least partially around at least one of the conductive terminals. In certain embodiments, the package includes a support layer, such as a compliant layer, disposed between the first face of the microelectronic element and the flexible substrate. In other embodiments, the support layer includes at least one opening that is at least partially aligned with one of the conductive terminals. | 08-05-2010 |
20110147928 | MICROELECTRONIC ASSEMBLY WITH BOND ELEMENTS HAVING LOWERED INDUCTANCE - Microelectronic assemblies can have multiple conductive bond elements, e.g., bond wires, or a lead bond and a bond wire, extending between a pair of a substrate contact and a chip contact. E.g., a first bond wire can have ends joined to the contacts of the chip and substrate. A second bond wire can be joined to the ends of the first bond wire so that the second bond wire does not touch either the chip contact or the substrate contact to which the first bond wire is joined. In one example, a bond wire has a looped connection with first and second ends joined at a first contact and a middle portion joined to a second contact. In one example, first and second bond elements, e.g., bond wires or lead bonds can connect first and second pairs of a substrate contact with a chip contact. A third bond element, e.g., a bond wire or bond ribbon, can be joined to ends of the first and second bond elements. | 06-23-2011 |
20110147953 | MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED INDUCTANCE - A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact. | 06-23-2011 |
20110285020 | MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED INDUCTANCE - A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact. | 11-24-2011 |
20120068338 | IMPEDANCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL - A microelectronic assembly is disclosed that is capable of achieving a desired impedance for raised conductive elements. The microelectronic assembly may include an interconnection element, a surface conductive element, a microelectronic device, a plurality of raised conductive elements, and a bond element. The microelectronic device may overlie the dielectric element and at least one surface conductive element attached to the front surface. The plurality of raised conductive elements may connect the device contacts with the element contacts. The raised conductive elements may have substantial portions spaced a first height above and extending at least generally parallel to at least one surface conductive element, such that a desired impedance may be achieved for the raised conductive elements. A bond element may electrically connect at least one surface conductive element with at least one reference contact that may be connectable to a source of reference potential. | 03-22-2012 |
20120155055 | SEMICONDUCTOR CHIP ASSEMBLY AND METHOD FOR MAKING SAME - A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly. | 06-21-2012 |
20120286416 | SEMICONDUCTOR CHIP PACKAGE ASSEMBLY AND METHOD FOR MAKING SAME - A microelectronic assembly may include a microelectronic element having a plurality of element contacts at a face thereof, and a compliant dielectric element having a Young's modulus of less than about two gigapascal (GPa) and substrate contacts at a first surface joined to the element contacts. The substrate contacts may be electrically connected with terminals at a second surface of the compliant dielectric element that opposes the first surface, through conductive vias in the compliant dielectric element. A rigid underfill may be between the face of the microelectronic element and the first surface of the compliant dielectric element. The terminals may be usable for bonding the microelectronic assembly to corresponding contacts of a component external to the microelectronic assembly. | 11-15-2012 |
20120313228 | IMPEDENCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL - A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces. | 12-13-2012 |
20120313238 | SEMICONDUCTOR CHIP PACKAGE ASSEMBLY AND METHOD FOR MAKING SAME - A microelectronic assembly may include a substrate containing a dielectric element having first and second opposed surfaces. The dielectric element may include a first dielectric layer adjacent the first surface, and a second dielectric layer disposed between the first dielectric layer and the second surface. A Young's modulus of the first dielectric layer may be at least 50% greater than the Young's modulus of the second dielectric layer, which is less than two gigapascal (GPa). A conductive structure may extend through the first and second dielectric layers and electrically connect substrate contacts at the first surface with terminals at the second surface. The substrate contacts may be joined with contacts of a microelectronic element through conductive masses, and a rigid underfill may be between the microelectronic element and the first surface. The terminals may be usable to bond the microelectronic assembly to contacts of a component external to the microelectronic assembly. | 12-13-2012 |
20120313242 | SUBSTRATE AND ASSEMBLY THEREOF WITH DIELECTRIC REMOVAL FOR INCREASED POST HEIGHT - An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces. | 12-13-2012 |
20120313253 | FAN-OUT WLP WITH PACKAGE - A microelectronic package includes a microelectronic unit and a substrate. The microelectronic unit includes a microelectronic element having contacts on a front face. A dielectric material has a first surface substantially flush with the front face of the microelectronic element. Conductive traces have at least portions extending along the front face away from the contacts, at least some of which also extend along the first surface of the dielectric material. Contacts are connected with the traces, at least some of which are disposed at the first surface of the dielectric material. The substrate has first and second opposed surfaces and an edge extending therebetween, the first surface facing the front face of the microelectronic unit, and the second surface having a plurality of terminals thereon configured for electrical connection with at least one external component. Masses of conductive matrix material join the terminals with the redistribution contacts. | 12-13-2012 |
20120313264 | CHIP WITH SINTERED CONNECTIONS TO PACKAGE - A microelectronic package and method of making same are provided. The package includes a substrate having first and second opposed surfaces, an edge surface extending therebetween, a plurality of terminals, and a plurality of conductive elements electrically connected with the terminals. The edge surface can be disposed at a periphery of the substrate or can be the edge surface of an aperture within the substrate. A microelectronic element has a front face and contacts thereon, with at least some of the contacts being adjacent to the edge surface of the substrate. A dielectric material overlies the edge surface of the substrate and defines a sloping surface between the front face of the microelectronic element and the substrate. A conductive matrix material defines a plurality of conductive interconnects extending along the sloping surface. The conductive interconnects electrically interconnect respective ones of the contacts with the conductive elements. | 12-13-2012 |
20130093087 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 90° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds. | 04-18-2013 |
20130093088 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds. | 04-18-2013 |
20130095610 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 92° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds. | 04-18-2013 |
20130118784 | HIGH STRENGTH THROUGH-SUBSTRATE VIAS - A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter. | 05-16-2013 |
20130134602 | FLIP CHIP PACKAGE FOR DRAM WITH TWO UNDERFILL MATERIALS - A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill. | 05-30-2013 |
20130200533 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. | 08-08-2013 |
20130292834 | MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED INDUCTANCE - First and second bond elements, e.g., wire bonds, electrically connect a chip contact with one or more substrate contacts of a substrate, and can be arranged so that the second bond element is joined to the first bond element at each end and so that the second bond element does not touch the chip contact or one or more substrate contacts. A third bond element can be joined to ends of the first and second bond elements. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact. | 11-07-2013 |
20130316501 | ULTRA-THIN NEAR-HERMETIC PACKAGE BASED ON RAINIER - A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals. | 11-28-2013 |
20130328219 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer. | 12-12-2013 |
20140124565 | MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED INDUCTANCE - First and second bond elements, e.g., wire bonds, electrically connect a chip contact with one or more substrate contacts of a substrate, and can be arranged so that the second bond element is joined to the first bond element at each end and so that the second bond element does not touch the chip contact or one or more substrate contacts. A third bond element can be joined to ends of the first and second bond elements. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact. | 05-08-2014 |
20140141568 | FLIP CHIP PACKAGE FOR DRAM WITH TWO UNDERFILL MATERIALS - A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill. | 05-22-2014 |
20140220744 | METHOD OF MAKING WIRE BOND VIAS AND MICROELECTRONIC PACKAGE HAVING WIRE BOND VIAS - Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate. | 08-07-2014 |
20140291871 | IMPEDANCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL - A microelectronic assembly is disclosed that is capable of achieving a desired impedance for raised conductive elements. The microelectronic assembly may include an interconnection element, a surface conductive element, a microelectronic device, a plurality of raised conductive elements, and a bond element. The microelectronic device may overlie the dielectric element and at least one surface conductive element attached to the front surface. The plurality of raised conductive elements may connect the device contacts with the element contacts. The raised conductive elements may have substantial portions spaced a first height above and extending at least generally parallel to at least one surface conductive element, such that a desired impedance may be achieved for the raised conductive elements. A bond element may electrically connect at least one surface conductive element with at least one reference contact that may be connectable to a source of reference potential. | 10-02-2014 |
20150028480 | SUBSTRATE AND ASSEMBLY THEREOF WITH DIELECTRIC REMOVAL FOR INCREASED POST HEIGHT - An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces. | 01-29-2015 |
20150044824 | Fan-Out WLP With Package - The present disclosure is directed to a method for making a microelectronic package that includes assembling a microelectronic unit with a substrate, and electrically connecting redistribution contacts on the microelectronic unit and terminals on the substrate with a conductive matrix material extending within at least one opening extending through the substrate. | 02-12-2015 |