Patent application number | Description | Published |
20080277731 | BODY BIAS TO FACILITATE TRANSISTOR MATCHING - One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a gate-source bias having a first polarity to the first transistor. The magnitude of a potential barrier in a pocket implant region of the first transistor is reduced by applying a body-source bias having the first polarity to the first transistor. Current flow is facilitated across the channel by applying a drain-source bias having the first polarity to the first transistor. Other methods and circuits are also disclosed. | 11-13-2008 |
20090046823 | NEUTRON GENERATING DEVICE - A neutron generating device is described. In one embodiment, the device has a chamber filled with a gas containing deuterium or tritium together with a piezoelectric crystal having a mechanical excitation apparatus proximate thereto. The piezoelectric crystal has first and second metal electrodes located on opposing surfaces. The first metal electrode is in electrical contact with a neutral potential. A field emitter tip is located on the second metal electrode, which emits an electrical field to form deuterium or tritium ions upon the mechanical excitation of the piezoelectric crystal. The deuterium or tritium ions are accelerated by an electric potential differential between the first metal electrode and the second metal electrode into a target containing deuterium or tritium with sufficient energy to form neutrons. | 02-19-2009 |
20090056345 | NANOSCALE THERMOELECTRIC REFRIGERATOR - A nanoscale thermoelectric device, which may be operated as a refrigerator or as a thermoelectric generator includes N-type and p-type active areas connected to a central terminal and end electrodes made of interconnect metal. Reducing lateral dimensions of the active areas reduces vertical thermal conduction, thus improving the efficiency of the thermoelectric device. The thermoelectric device may be integrated into the fabrication process sequence of an IC without adding process cost or complexity. Operated as a refrigerator, the central terminal may be configured to cool a selected component in the IC, such as a transistor. Operated as a thermoelectric generator with a heat source applied to the central terminal, the end terminals may provide power to a circuit in the IC. | 03-05-2009 |
20090057651 | Gated Quantum Resonant Tunneling Diode Using CMOS Transistor with Modified Pocket and LDD Implants - A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode. | 03-05-2009 |
20090061606 | METHOD FOR REDUCING DISLOCATION THREADING USING A SUPPRESSION IMPLANT - The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well ( | 03-05-2009 |
20090079446 | Method to Accurately Estimate the Source and Drain Resistance of a MOSFET - Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections. | 03-26-2009 |
20090140346 | MATCHED ANALOG CMOS TRANSISTORS WITH EXTENSION WELLS - One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed. | 06-04-2009 |
20090159967 | SEMICONDUCTOR DEVICE HAVING VARIOUS WIDTHS UNDER GATE - One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the body about lateral edges of a gate electrode and are separated from one another by a gate length. A channel region, which is configured to allow charged carriers to selectively flow between the source and drain regions during operation of the device, has differing widths under the gate electrode. These widths are generally perpendicular to the gate length. Other devices, methods, and systems are also disclosed. | 06-25-2009 |
20100045365 | TWO TERMINAL QUANTUM DEVICE USING MOS CAPACITOR STRUCTURE - A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate. The device may be fabricated in either polarity, and integrated into a CMOS IC, configured as a quantum dot device or a quantum wire device. The device may be operated as a precision charge pump, with a minority carrier injection region added to speed well filling. | 02-25-2010 |
20100065823 | GATED RESONANT TUNNELING DIODE - A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer. | 03-18-2010 |
20100093140 | GATED RESONANT TUNNELING DIODE - A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer. | 04-15-2010 |
20100274506 | METHOD FOR MEASURING INTERFACE TRAPS IN THIN GATE OXIDE MOSFETS - A method for measuring interface traps in a MOSFET, includes measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points. | 10-28-2010 |
20110127572 | GATED RESONANT TUNNELING DIODE - A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer. | 06-02-2011 |
20110253999 | SEMICONDUCTOR WAFER HAVING SCRIBE LINE TEST MODULES INCLUDING MATCHING PORTIONS FROM SUBCIRCUITS ON ACTIVE DIE - A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at least two matched devices. The first subcircuit is arranged in a layout on the IC die. A plurality of scribe line areas having a scribe line width dimension are interposed between the plurality of IC die areas. At least one subcircuit-based test module (TM) is positioned within the scribe line areas, wherein the subcircuit-based TMs implement a schematic for the first subcircuit with a TM layout that copies the layout on the IC die for at least the two matched devices in the matched component portion and alters the layout on the IC die for a portion of the first subcircuit other than the matched devices in matched component portion to fit the TM layout of the first subcircuit within the scribe line width dimension. | 10-20-2011 |
20120098590 | QUANTUM ELECTRO-OPTICAL DEVICE USING CMOS TRANSISTOR WITH REVERSE POLARITY DRAIN IMPLANT - A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode. | 04-26-2012 |
20130255741 | STRUCTURE AND METHOD FOR COUPLING HEAT TO AN EMBEDDED THERMOELECTRIC DEVICE - An integrated circuit with an embedded heat exchanger for coupling heat to an embedded thermoelectric device from a thermal source that is electrically isolated from a thermoelectric device. A method for forming an integrated circuit with an embedded heat exchanger. | 10-03-2013 |