Patent application number | Description | Published |
20080316412 | LIQUID CRYSTAL DISPLAY PANEL AND PIXEL ARRAY STRUCTURE THEREOF - A liquid crystal display (LCD) panel including a first substrate, a second substrate, a liquid crystal layer, and a pixel array structure is provided. The first substrate includes a plurality of scan lines and a plurality of data lines, and the second substrate includes a common electrode. The liquid crystal layer is disposed between the first substrate and the second substrate. The pixel array structure includes a plurality of pixel units and a plurality of protrusions. The pixel units are arranged as an array, and each pixel unit includes an active device and a pixel electrode electrically connected the active device, wherein the pixel electrode has a plurality of electrode sections. The protrusions are substantially located in at least one junction region of the electrode sections. The liquid crystal molecules in the LCD panel have fast response speed and correct arrangement direction. | 12-25-2008 |
20090173942 | PIXEL STRUCTURE - A pixel structure formed on a substrate and electrically connected with a scan line and a data line, and including a semiconductor pattern and a pixel electrode is provided. The semiconductor pattern includes at least two channel areas, at least one doping area, a source area, and a drain area. The channel areas are located below the scan line and have different aspect ratios. The doping area is connected between the channel areas. The pixel electrode electrically connects the drain area, the source area is connected between one of the channel areas and the data line, and the drain area is connected between the other channel area and the pixel electrode. The scan line has different widths above different channel areas, and a length of each channel area is substantially equal to the width of the scan line. | 07-09-2009 |
20100025692 | PIXEL STRUCTURE - A pixel structure formed on a substrate and electrically connected with a scan line and a data line, and including a semiconductor pattern and a pixel electrode is provided. The semiconductor pattern includes at least two channel areas, at least one doping area, a source area, and a drain area. The channel areas are located below the scan line and have different aspect ratios. The doping area is connected between the channel areas. The pixel electrode electrically connects the drain area, the source area is connected between one of the channel areas and the data line, and the drain area is connected between the other channel area and the pixel electrode. The scan line has different widths above different channel areas, and a length of each channel area is substantially equal to the width of the scan line. | 02-04-2010 |
Patent application number | Description | Published |
20120293491 | 3-D TOUCH SENSOR AND 3-D TOUCH PANEL - A 3-D touch panel includes a 3-D touch sensor, a capacitance sensing unit electrically connected to the 3-D touch sensor, and a processing unit electrically connected to capacitance sensing unit. The 3-D touch sensor includes a flexible substrate, a flexible plane, a first electrode, and a second electrode. The flexible plane is configured on the flexible substrate and used for a user to touch thereon. The first electrode and the second electrode are correspondingly and respectively configured on the flexible substrate and the flexible plane, and a capacitance is formed between the first electrode and the second electrode. The capacitance sensing unit is used for sensing the value of the capacitance, and the processing unit calculates the shearing force, which the user applies on the flexible plane, according to the difference of the capacitance value. | 11-22-2012 |
20130033710 | NON-ENERGY DISSIPATING, CURVATURE SENSING DEVICE AND METHOD - A non-energy dissipating, curvature sensing device senses curvature variation of a sample and comprises an outer layer, an inner layer and at least one spacer. The outer layer is flexible, transparent material and has a shape. The inner layer is flexible, transparent material, has a shape corresponding to the shape of the outer layer, is positioned under the outer layer and is thicker and harder than the outer layer. At least one spacer is positioned between the outer layer and the inner layer and creates space between the outer layer and the inner layer. A non-energy dissipating, curvature sensing method is also disclosed. | 02-07-2013 |
20140043670 | Electro-wetting transmissive and interference display device with adjustable function - An electro-wetting transmissive and interference display device with adjustable function includes a lower electrode, an upper electrode and an droplet disposed between the upper electrode and the lower electrode, wherein the lower electrode, the droplet and the upper electrode are disposed on a substrate, and the droplet is enclosed between the lower electrode and the upper electrode by an ink jet printing method. | 02-13-2014 |
20150043610 | STRESS DETECTION SYSTEM ON SMALL AREAS AND METHOD THEREOF - A system and a method for stress detection on small areas are disclosed. The method is applied to a strain gauge, which uses the Joule heating effect-generated temperature difference to monitor and to localize compressive and tensile strains. Furthermore, the invention provides a systematic extrapolation prediction methodology for strains. | 02-12-2015 |
Patent application number | Description | Published |
20150380112 | MEMORY INTEGRATED CIRCUIT WITH A PAGE REGISTER/STATUS MEMORY CAPABLE OF STORING ONLY A SUBSET OF ROW BLOCKS OF MAIN COLUMN BLOCKS - An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns. | 12-31-2015 |
20160005481 | MEMORY PAGE BUFFER - Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement. | 01-07-2016 |
20160077153 | MEMORY UTILIZING BUNDLE-LEVEL STATUS VALUES AND BUNDLE STATUS CIRCUITS - An integrated circuit memory includes a memory array, including a plurality of data lines. A buffer structure is coupled to the plurality of data lines, including a plurality of storage elements to store bit-level status values for the plurality of data lines. The memory includes logic to indicate bundle-level status values of corresponding bundles of storage elements in the buffer structure based on the bit-level status values of bits in the corresponding bundles. A plurality of bundle status circuits is arranged in a daisy chain and coupled to respective bundles in the buffer structure, producing an output of the daisy chain indicating detection of a bundle in the first status. Control circuitry executes cycles to determine the output of the daisy chain, each cycle clearing a bundle status circuit indicating the first status if the output indicates detection of a bundle in the first status in the cycle. | 03-17-2016 |
Patent application number | Description | Published |
20140027823 | METHOD FOR FORMING THIN METAL COMPOUND FILM AND SEMICONDUCTOR STRUCTURE WITH THIN METAL COMPOUND FILM - A method for forming a metal compound film includes: providing a substrate structure; forming a first metal layer on the substrate structure; performing a first microwave annealing process to conduct a reaction between the first metal layer and the substrate structure so as to form a first polycrystalline film of a metal compound; and performing a second microwave annealing process to transform the first polycrystalline film into a second polycrystalline film of the metal compound with an enlarged grain size, wherein a microwave power output used in the second microwave annealing process is higher than that used in the first microwave annealing process. | 01-30-2014 |
20140094023 | FABRICATING METHOD OF SEMICONDUCTOR CHIP - A fabricating method of a semiconductor chip includes the following steps. Firstly, a substrate is provided, wherein an amorphous semiconductor layer is formed in a first surface of the substrate. Then, a first metal layer is formed on the amorphous semiconductor layer. Then, a thermal-treating process is performed to result in a chemical reaction between the first metal layer and a part of the amorphous semiconductor layer, thereby producing an amorphous metal semiconductor compound layer. Afterwards, a microwave annealing process is performed to recrystallize the amorphous metal semiconductor compound layer as a polycrystalline metal semiconductor compound layer. | 04-03-2014 |
20140374834 | GERMANIUM STRUCTURE, GERMANIUM FIN FIELD EFFECT TRANSISTOR STRUCTURE AND GERMANIUM COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR STRUCTURE - A germanium (Ge) structure includes a substrate, a Ge layer and at least a Ge spatial structure. The Ge layer is formed on the substrate, and a surface of the Ge layer is a Ge {110} lattice plane. The Ge spatial structure is formed in the Ge layer and includes a top surface and a sidewall surface, wherein the top surface is a Ge {110} lattice plane and the sidewall surface is perpendicular to the top surface. An axis is formed at a junction of the sidewall surface and the top surface, and an extensive direction of the axis is parallel to a Ge [112] lattice vector on the surface of the Ge layer, therefore the sidewall surface is a Ge {111} lattice plane. Because Ge {111} surface channels have very high electron mobility, this Ge spatial structure may be applied for fabricating high-performance Ge semiconductor devices. | 12-25-2014 |
Patent application number | Description | Published |
20100202179 | MEMORY DEVICE - A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line. | 08-12-2010 |
20110156102 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line. | 06-30-2011 |
20120273842 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line. | 11-01-2012 |
Patent application number | Description | Published |
20120025258 | LIGHT EMITTING DIODE PACKAGE AND LIGHT EMITTING DIODE MODULE - An exemplary LED module includes a board and an LED package mounted on the plate. The LED package includes a base, an LED chip mounted on a top surface of the base, two electrodes formed on the base and electrically connected to the LED chip and the board, and an encapsulant encapsulating the LED chip. A plurality of grooves are defined in the bottom surface of the base. When the LED package is secured on the plate via solder paste, the grooves function as a container for receiving excessive solder paste, thereby preventing the solder paste from spilling and floating or inclination of the LED package. | 02-02-2012 |
20130280834 | METHOD FOR MANUFACTURING LED - A method for manufacturing an LED package includes following steps: providing a base with an LED chip mounted on the base; providing a porous carrier with a plurality of holes, and disposing the base on the porous carrier; providing a film with a phosphor layer attached on the film; providing a mold, and putting the porous carrier, the base, the LED chip, and the film into the mold; extracting air from the mold to an external environment through the holes of the porous carrier, and/or, blowing air toward the film to urge the film to move toward the LED chip, resulting in that the film is conformably attached onto the LED chip and the base; and solidifying the phosphor layer on the LED chip by means of heating whereby the phosphor is conformably and securely attached on the LED chip. | 10-24-2013 |
20130285093 | LIGHT EMITTING DIODE PACKAGE STRUCTURE HAVING A SUBSTRATE INCLUDING CERAMIC FIBERS - An LED package structure includes a substrate and an LED chip formed on the substrate. The substrate has a first electrode and a second electrode formed on an upper surface thereof. The LED chip is formed on the first electrode of the substrate and electrically connected with the first electrode and the second electrode respectively. The substrate is made of a composite including a base material and ceramic fibers mixed in the base material. | 10-31-2013 |
20130285097 | SIDE-VIEW LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A side-view LED package includes a substrate, a pair of electrodes connected to the substrate, an LED die electrically connected to the electrodes, a reflective cup formed on the substrate, an opening defined at a lateral side of the reflective cup, an encapsulation formed on the substrate to cover the LED die, and a reflective layer coated on a top of the encapsulation and a top of the reflective cup, wherein part of light emitting from the LED die is reflected by the reflective cup and the reflective layer and then emits out of the side-view LED package from the opening. The present disclosure also provides a method for manufacturing the side-view LED package described above. | 10-31-2013 |
20130288407 | METHOD FOR MANUFACTURING LED PACKAGE - A method for manufacturing an LED package includes providing a substrate including an insulating layer inlayed with first and second electrodes. The first and second electrodes define a chip fastening area. An LED chip is fastened on the chip fastening area and electrically connected to the first and second electrodes. A buffer layer including a shelter and grooves is brought to be located over the substrate wherein the shelter covers the chip fastening area and the grooves are located over portions of the substrate beside the first and second electrodes. A reflecting layer is formed in the grooves of the buffer layer by injecting liquid material into the grooves. The buffer layer is removed after the liquid material is solidified and a through hole is defined. An encapsulant is formed to cover the LED chip by injecting the encapsulant into the through hole and the chip fastening area. | 10-31-2013 |
20130288408 | METHOD FOR MANUFACTURING LED - A method for manufacturing an LED includes steps: providing a base and an LED chip disposed on the base; providing an optical element and disposing the optical element on the base to cover the LED chip; providing a phosphor film and disposing the phosphor film on the optical element; providing a holding plate with capillary holes and disposing the base on the holding plate; providing a mold, wherein the mold and the holding plate cooperatively form a receiving room which receives the base, the LED chip, the optical element and the phosphor film therein; extracting air from the receiving room through the capillary holes of the holding plate, and/or, blowing air toward the phosphor film, whereby the phosphor film is conformably attached onto the optical element; and solidifying the phosphor film on the optical element. | 10-31-2013 |
20140167078 | LEAD FRAME AND LIGHT EMITTING DIODE PACKAGE HAVING THE SAME - An exemplary lead frame includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes a first connecting surface and a second connecting surface spaced from the first connecting surface. Top surfaces of the bonding electrode, the first connecting electrode and the second connecting electrode are exposed out of the substrate to support and electrically connect with light emitting chips. Light emitting chips can be mounted on the lead frame and electrically connect with each other in parallel or in series; thus, the light emitting chips can be connected with each in a versatile way. | 06-19-2014 |
20140175482 | LIGHT EMITTING DIODE PACKAGE WITH LIGHT REFLECTING CUP INTERNALLY SLANTED - An exemplary LED package includes a base, electrodes formed on the base, an LED chip electrically connecting the electrodes, and a reflecting cup mounted on the base and surrounding the LED chip therein. The reflecting cup includes a bottom surface and an inner surface recessed up from the bottom surface and slantwise oriented towards a top end of the reflecting cup. The reflecting cup is annular. The inner surface includes a reflecting portion slantwise extending from the top surface, and a transition portion extending downwardly from the reflecting portion. The transition portion defines a through hole therein. The reflecting portion defines a reflecting hole therein. An angle α is defined between the reflecting portion and an imaginary surface parallel to the bottom surface. An angle β is defined between the reflecting portion and the bottom surface. The angle β is larger than the angle α. | 06-26-2014 |
Patent application number | Description | Published |
20100079351 | SOLID DUAL-BAND ANTENNA DEVICE - A solid dual-band antenna device is provided. The solid dual-band antenna device includes a Z-shape antenna structure comprising a first turn having a first turning angle, and connected to a ground portion and a first radiating portion; and a second turn having a second turning angle, and connected to the first radiating portion and a second radiating portion; a feeding portion disposed at the second turn for feeding a signal; an extending ground portion non-coplanarly extended from an outer side of the ground portion; and an extending radiating portion non-coplanarly extended from an outer side of the second radiating portion, wherein a first slot is disposed at an arbitrary position of the second radiating portion, and a length of the first radiating portion is different from a length of the second radiating portion. | 04-01-2010 |
20100164811 | Solid Antenna - A solid antenna is provided in the present invention. The solid antenna configured on a substrate having an electronic circuit disposed thereon, including: an antenna body having at least one bending portion and a signal feed-in portion by which the antenna body is electrically connected to the electronic circuit and secured to the substrate, wherein the at least one bending portion is configured to be across the substrate. | 07-01-2010 |
20110122042 | Antenna with Multi-Bands - An antenna connected to an interface connection port is provided. The antenna comprises a ground surface having a plurality of bands thereon; a first radiation element disposed on the ground surface and including a first bending section and a second bending section, wherein the ground surface is extended from the first bending section; and a second radiation element having a shape of a strip, extended from the second bending section, including a first end and a second end, and having a first flange at the first end and a second flange at the second end. | 05-26-2011 |
20140285380 | ANTENNA STRUCTURE AND THE MANUFACTURING METHOD THEREFOR - An antenna structure is provided. The antenna structure includes a radiating portion having an approximately quadrangular body, wherein the quadrangular body has a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side; and a ground portion surrounding an entire length of the first side, an entire length of the fourth side, and at most a half of a length of the second side. | 09-25-2014 |
20150194729 | DUAL-BAND PRINTED MONOPOLE ANTENNA - A monopole antenna is disclosed. The monopole antenna includes a grounding terminal and a transmission line extending along a first direction and including a first terminal and a feeding terminal adjacent to the grounding terminal. The monopole antenna further includes a first radiator connected to the first terminal, extending along a second direction perpendicular to the first direction and operating within a first frequency range. The first radiator has a portion with a width increasing gradually along the second direction. The monopole antenna further includes a second radiator connected to the first terminal, extending along a third direction far away from the grounding terminal, having a first included angle with the transmission line, including a plurality of turns, and operating within a second frequency range. | 07-09-2015 |
20160049732 | ANTENNA AND THE MANUFACTURING METHOD THEREOF - A method of manufacturing an antenna is provided. The method includes steps of providing a substrate including a feed-in terminal and a ground terminal; and forming a ground conductor structure on the substrate extended from the feed-in terminal to the ground terminal and including a first conductor extended along a first direction, a second conductor extended from the first conductor along a second direction, a third conductor extended from the second conductor along a third direction, and a fourth conductor extended from the third conductor along a fourth direction, wherein a first obtuse angle is formed between the first direction and the second direction, a second obtuse angle is formed between the second direction and the third direction, and an acute angle is formed between the third direction and the fourth direction. | 02-18-2016 |
Patent application number | Description | Published |
20130208340 | ELECTROPHORETIC DISPLAY PANEL AND MANUFACTURING METHOD THEREOF AND ELECTROPHORETIC DISPLAY APPARATUS - An electrophoretic display panel including a transparent substrate, an active element array, a protective layer, plural electrophoretic display media and a transparent conductive layer is provided. The transparent substrate has an upper surface, a lower surface, plural first cavities located on the upper surface and plural second cavities located on the lower surface. The active element array is disposed on the upper surface and covers the upper surface and the first cavities. The protective layer is disposed on the upper surface and covers at least the active element array. The electrophoretic display media and the transparent conductive layer are disposed on the lower surface. The electrophoretic display media and the active element array overlap in at least a portion of their orthographic projections on the upper surface of the transparent substrate. The electrophoretic display media are located between the transparent conductive layer and the lower surface of the transparent substrate. | 08-15-2013 |
20140185128 | DISPLAY DEVICE AND FABRICATION METHOD OF DISPLAY DEVICE - A display device including a first substrate, a second substrate, a display layer, a color filter layer, a transparent electrode layer and a transparent sealing is provided. The first substrate is opposite to the second substrate. The display layer is disposed between the first substrate and the second substrate. The color filter layer is disposed between the display layer and the first substrate. The transparent electrode layer is disposed between the color filter layer and the display layer. The transparent sealing surrounds the display layer so that the display layer is sealed between the first substrate and the second substrate, wherein a curable temperature of the transparent sealing is lower than or equal to 40° C. A fabrication method of a display device is further provided herein. | 07-03-2014 |
20140204453 | ELECTROPHORETIC DISPLAY APPARATUS - An electrophoretic display apparatus includes a drive array substrate, a color filter layer and an electrophoretic display film. The drive array substrate has a plurality of pixel units, in which each of the pixel units includes a drive device. The color filter layer is disposed on the drive array substrate and has a plurality of color filter patterns, in which each of the color filter patterns is corresponding to at least two of the pixel units. The electrophoretic display film is disposed between the drive array substrate and the color filter layer and includes a plurality of display mediums, in which the display mediums corresponding to each of the color filter patterns are controlled by at least two of the drive devices. | 07-24-2014 |
20140333988 | COLOR FILTER STRUCTURE AND MANUFACTURING METHOD THEREOF - The disclosure provides a color filter structure used to a reflective display. The color filter structure includes a transparent substrate, a plurality of color resists, a plurality of light-impermeable structures and a reflective layer. The transparent substrate has a top surface and a bottom surface, and the color resists are positioned on the top surface of the transparent substrate. The light-impermeable structures are positioned in the transparent substrate, in which the adjacent two color resists are separated by one of the light-impermeable structures. The reflective layer is positioned on the bottom surface of the transparent substrate. And the method for manufacturing the color filter structure is also disclosed herein. | 11-13-2014 |
20150138246 | COLOR REFLECTIVE DISPLAY DEVICE AND OPERATING METHOD THEREOF - A color reflective display device includes a plurality of color sub-pixels and a control circuit. The control circuit is configured to provide a first driving signal to at least one of a plurality of mini-pixels of a first color sub-pixel, such that the at least one of mini-pixels receiving the first driving signal displays a first color, provide a second driving signal to another at least one of the mini-pixels of the first color sub-pixel, such that the another at least one of the mini-pixels receiving the second driving signal displays a second color, and provide a third driving signal to a second color sub-pixel of the color sub-pixels, such that the second color sub-pixel displays a third color. | 05-21-2015 |
20150146146 | COLOR FILTER SUBSTRATE AND DISPLAY DEVICE - A color filter substrate includes a transparent substrate and a plurality of color filter patterns. The transparent substrate has an upper surface and a lower surface opposite to each other, and a plurality of containing cavities. The containing cavities extend from the upper surface toward the lower surface and separate from each other. Each containing cavity has a bottom surface. The color filter patterns are disposed on the transparent substrate and located inside the containing cavities, respectively. The color filter patterns contact with the corresponding bottom surfaces, respectively. | 05-28-2015 |
20150287763 | PIXEL ARRAY - A pixel array includes a substrate and color filter patterns. The substrate has pixel areas. Each of the pixel areas has a first sub-pixel region, a second sub-pixel region, a third sub-pixel region and a fourth sub-pixel region. The first, the second, the third and the fourth sub-pixel regions are arranged sequentially in the clockwise direction. The color filter patterns are disposed on the pixel areas of the substrate and located in the first, the second, the third and the fourth sub-pixel regions. The color filter patterns located in the first, the second, the third and the fourth sub-pixel regions of each of the pixel areas respectively have different colors. The color filter patterns respectively disposed in four adjacent pixel areas and located in the first, the second, the third and the fourth sub-pixel regions adjacent to each other and arranged in the clockwise direction have the same color. | 10-08-2015 |
20150301424 | ELECTROPHORETIC DISPLAY APPARATUS - An electrophoretic display apparatus includes a first substrate, a plurality of sub-pixel structures, a color filter array, and an electrophoretic layer. The sub-pixel structures are disposed on the first substrate, and each of the sub-pixel structures includes a plurality of sub-pixel sub-structures. The color filter array is disposed above the sub-pixel structures, and includes a plurality of filter units. The filter units are divided into a plurality of groups having different colors, and the filter units belonging to the groups having different colors are alternately disposed above the sub-pixel structures. Each of the filter units corresponds to the sub-pixel sub-structures of at least one sub-pixel structure, and at least two of the sub-pixel sub-structures of the same sub-pixel structure are adapted to be applied different voltages. The electrophoretic layer is disposed on the sub-pixel structures. | 10-22-2015 |
Patent application number | Description | Published |
20110156249 | WAFER-TO-WAFER STACK WITH SUPPORTING PEDESTAL - An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer. | 06-30-2011 |
20120178212 | WAFER-TO-WAFER STACK WITH SUPPORTING PEDESTAL - A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses. | 07-12-2012 |
20130161829 | WAFER-TO-WAFER STACK WITH SUPPORTING POST - A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip. | 06-27-2013 |
20140084413 | PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME - A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a top surface and a bottom surface opposing the top surface; an insulating protective layer formed on the top surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and passive components provided on or embedded in the interposer. By integrating the passive components into the package substrate, when a chip is provided on the interposer, the conductive path between the chip and the passive components can be shortened, and the pins of the chip have a stable voltage. Therefore, the overall electrical performance is enhanced. | 03-27-2014 |
20140117557 | PACKAGE SUBSTRATE AND METHOD OF FORMING THE SAME - A package substrate and a method for forming the package substrate are disclosed. The package substrate includes an interposer having a plurality of conductive through vias and a first insulating layer formed on the sidewalls of the conductive through vias, a second insulating layer formed on one side of the interposer, and a plurality of conductive vias formed in the second insulating layer and electrically connected to the conductive through vias. By increasing the thickness of the first insulating layer, the face diameter of the conductive through vias can be reduced, and the layout density of the conductive through vias in the interposer can thus be increased. | 05-01-2014 |
Patent application number | Description | Published |
20080277721 | THIN FILM TRANSISTOR, PIXEL STRUCTURE AND FABRICATING METHOD THEREOF - A fabricating method of a TFT includes first forming a source on a substrate. Then, a first insulation pattern layer is formed to cover parts of the source and the substrate. The first insulation pattern layer has an opening exposing a part of the source. Thereafter, a gate pattern layer is formed on the first insulation pattern layer. Then, the gate pattern layer and a second insulation pattern layer formed thereon surround the opening. Moreover, a second lateral protection wall is formed on an edge of the gate pattern layer in the opening. Afterwards, a channel layer is formed in the opening and covers the second lateral protection wall and the source. Then, a passivation layer with a contact window is formed on the channel layer and the second insulation pattern layer to expose a portion of the channel layer. Thereafter, a drain is formed on the exposed channel layer. | 11-13-2008 |
20100136753 | FABRICATING METHOD OF THIN FILM TRANSISTOR - A fabricating method of a TFT includes first forming a source on a substrate. Then, a first insulation pattern layer is formed to cover parts of the source and the substrate. The first insulation pattern layer has an opening exposing a part of the source. Thereafter, a gate pattern layer is formed on the first insulation pattern layer. Then, the gate pattern layer and a second insulation pattern layer formed thereon surround the opening. Moreover, a second lateral protection wall is formed on an edge of the gate pattern layer in the opening. Afterwards, a channel layer is formed in the opening and covers the second lateral protection wall and the source. Then, a passivation layer with a contact window is formed on the channel layer and the second insulation pattern layer to expose a portion of the channel layer. Thereafter, a drain is formed on the exposed channel layer. | 06-03-2010 |
Patent application number | Description | Published |
20120017427 | METHOD FOR FORMING ANTENNA STRUCTURE - A method for forming an antenna structure is provided, including the following steps of: providing a non-conductive frame and disposing a plating resist material on the non-conductive frame, removing a part of the plating resist material within a predetermined region on the non-conductive frame and forming a roughened surface on the non-conductive frame within the predetermined region by laser marking, forming a medium layer on the roughened surface, wherein the medium layer comprises Pd or Ag, removing the plating resist material on the non-conductive frame, and forming a metal layer on the medium layer. | 01-26-2012 |
20120027951 | METHOD FOR FORMING ANTENNA STRUCTURE - A method for forming an antenna structure is provided, including the following steps of: providing a non-conductive frame and forming a photosensitive medium layer on the non-conductive frame, wherein the medium layer comprises a catalyzer for electroless deposition; applying a light beam through a transparent portion of a mask to the medium layer, such that a part of the medium layer is solidified within a predetermined region on the non-conductive frame; removing a part of the medium layer outside of the predetermined region; and forming a metal layer on the medium layer within the predetermined region. | 02-02-2012 |
20120042505 | METHOD FOR MANUFACTURING ANTENNA - A method for manufacturing an antenna includes steps as follows. First, a substrate is provided, wherein a surface of the substrate has an antenna region. Then, the surface of the substrate is electroless plated with a metal medium, so that the surface is covered with the metal medium. Then, the metal medium is covered with a resist. Then, a portion of the resist in the antenna region is removed. Then, the antenna region is electroplated with metal material to form an antenna main body. Then, a remaining portion of the resist is removed, and excluding a portion of the metal medium in the antenna region, the other portion of the metal medium is also removed from the substrate. | 02-23-2012 |
Patent application number | Description | Published |
20100258171 | SOLAR PHOTOVOLTAIC DEVICE - A solar photovoltaic device is provided and includes a solar cell body, a window layer on the solar cell body, and a current collection layer on the window layer. The current collection layer includes a patterned structure, and a portion of the window layer is exposed by the patterned structure. | 10-14-2010 |
20110005595 | SOLAR CELL MODULE AND THE FABRICATION METHOD OF THE SAME - The application illustrates a solar cell module, included a base device, a solar cell on the base device, and a concentrator on the solar cell. The concentrator directly contacts with the solar cell and concentrates the light to the solar cell for opto-electric transformation. | 01-13-2011 |
20120002291 | ELECTROMAGNETIC WAVE GATHERING DEVICE AND SOLAR CELL MODULE HAVING THE SAME - An electromagnetic wave gathering device includes a pillared electromagnetic waveguide body and a reflective structure. The reflective structure is located at about an axis of the pillared electromagnetic waveguide body. The reflective structure comprises a plurality of bicone reflective units. Each of the reflective units has a first reflective surface. The electromagnetic wave gathering device may have a smaller volume and is handy for use. | 01-05-2012 |
20130081681 | PHOTOVOLTAIC DEVICE - This disclosure discloses a light-emitting device. The light-emitting device comprises a substrate; a first photovoltaic cell disposed over the substrate comprising a base layer having a first conductivity type; an emitter layer having a second conductivity type; a window layer having the second conductivity type; an intermediate structure between the emitter layer and the window layer having the second conductivity type, and comprising a first portion adjacent to the emitter layer and a second portion on the first portion. The first portion comprises a bandgap energy higher than that of the emitter layer and the intermediate structure is substantially lattice matched with the emitter layer. | 04-04-2013 |
20130286634 | METHOD FOR MANUFACTURING OPTOELECTRONIC DEVICES - A method for manufacturing optoelectronic devices comprising the steps of: providing a common growth substrate; forming a light-emitting epitaxy structure on the common growth substrate; forming a stripping layer on the light-emitting epitaxy structure; forming a solar cell epitaxy structure on the stripping layer; forming an adhesive layer on the solar cell epitaxy structure; proving a solar cell permanent substrate on the adhesive layer; and removing the stripping layer to form a light-emitting device and a solar cell device separately. | 10-31-2013 |
20130298972 | OPTOELECTRONIC DEVICE AND THE MANUFACTURING METHOD THEREOF - A method for manufacturing an optoelectronic device includes steps of: providing an optoelectronic structure; forming a first contact layer having a pattern on the upper surface of the optoelectronic structure; forming a dielectric layer on the first contact layer and the optoelectronic structure; removing the dielectric layer on the first contact layer; and forming an electrode structure on the first contact layer. | 11-14-2013 |
20140196782 | METHOD FOR MAKING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MADE THEREBY - Disclosed is a method for yield enhancement of making a semiconductor device. The method for yield enhancement of making a semiconductor device comprises the steps of: providing the semiconductor device comprising an epitaxial layer including a defect; forming a dielectric layer on the epitaxial layer; detecting and identifying a location of the defect; and etching the dielectric layer and leaving a part of the dielectric layer to cover an area substantially corresponding to the detected defect. The semiconductor device made by the method is also disclosed. | 07-17-2014 |
20140199784 | Method and Apparatus for Making a Semiconductor Device - Disclosed is an apparatus and method for yield enhancement of making a semiconductor device. The apparatus for yield enhancement of making a semiconductor device comprises: a semiconductor device comprising an epitaxial layer in which a defect is included, and a photo-resistor on the epitaxial layer and covering the defect; an image recognition system to detect and identify a location of the defect; and an exposing module comprising a first light source to expose a part of the photo-resistor substantially corresponding to the detected defect identified by the image recognition system. | 07-17-2014 |
20140217359 | Light-Emitting Apparatus - The present application discloses a light-emitting apparatus comprising a first light-emitting semiconductor stack, a first intermediate layer formed on the first light-emitting semiconductor stack and a second light-emitting semiconductor stack formed on the first intermediate layer. The first intermediate layer comprises a first conductive semiconductor layer, a second conductive semiconductor layer and an intermediate region. The intermediate region has a discontinuous structure located between the first conductive semiconductor layer and the second conductive semiconductor layer. | 08-07-2014 |
20150155433 | LIGHT-EMITTING DEVICE - A light-emitting device includes: a Distributed Bragg reflector comprising alternate first semiconductor layers and second semiconductor layers, wherein each first semiconductor layer comprises a low-refractive-index part having a depth; and a light-emitting semiconductor stack associated with the Distributed Bragg reflector; wherein the depths of the low-refractive-index parts of the first semiconductor layers are gradually changed in a direction toward the light-emitting semiconductor stack. | 06-04-2015 |
20150222094 | LIGHT-EMITTING ARRAY - A light-emitting array comprises a plurality of light-emitting elements, wherein each of the plurality of light-emitting elements comprises a first semiconductor stack; and a plurality of bridge structures connected to the plurality of light-emitting elements, wherein the plurality of light-emitting elements are spaced apart by the plurality of bridge structures, wherein each of the plurality of bridge structures comprise a second semiconductor stack which has the same epitaxial stack as the first semiconductor stack. | 08-06-2015 |