Hong, Shanghai
Bo Hong, Shanghai CN
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20100322232 | MODEM AND CALLING PACKET PROCESSING METHOD THEREOF - A modem to process calling packets includes receiving a calling request packet from a software phone of a communication terminal, and determining if the calling request packet includes a special tag. If the IP phone is idle, the modem records a source IP address of the calling request packet, and modifies the source IP of the calling request packet to be an IP address of the IP phone, then the modem transmits the modified calling request packet to a server, and receives a calling reply packet from the server, then modifies a destination IP address of the calling reply packet to be the IP address of the communication terminal. The modem transmits the modified calling reply packet to the software phone to establish the call. | 12-23-2010 |
Cheng Hong, Shanghai CN
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20110221406 | REFERENCE VOLTAGE GENERATION CIRCUIT - Disclosed is a reference voltage generation circuit comprising a reference voltage generation and comparison unit, a drive unit, and M drive unit candidate circuits. The reference voltage generation and comparison unit generates reference voltage. An output voltage output from the reference voltage generation circuit is input into the reference voltage generation and comparison unit as a negative feedback voltage. After being compared with the reference voltage, the output voltage is output from the reference voltage generation and comparison unit to the drive unit and the M drive unit candidate circuits. When power supply voltage of the reference voltage generation circuit varies, after being driven by the drive unit and the drive unit candidate circuits, the output voltage is output to an output terminal of the reference voltage generation circuit so that the output voltage can be stabilized at the level of the reference voltage. | 09-15-2011 |
20120001551 | SEMICONDUCTOR APPARATUS AND METHOD OF CONTROLLING OPERATION THEREOF - A semiconductor apparatus includes an input terminal to which an input voltage is applied; an output terminal at which an output voltage is obtained; a power supply circuit unit configured to generate the output voltage from the input voltage, the output voltage having a value corresponding to a duty cycle of a voltage setting signal that is externally applied to the semiconductor apparatus; and a determination circuit unit determining whether the voltage setting signal has a predetermined signal level for the duration of a first predetermined time or longer. The determination circuit unit activates the power supply circuit unit when the voltage setting signal does not have the predetermined signal level for the duration of the first predetermined time or longer. The power supply circuit unit is deactivated when the voltage setting signal has the predetermined signal level for the duration of the first predetermined time or longer. | 01-05-2012 |
20150351653 | Systems and Methods for Detecting ECG Subwaveforms - Systems and methods are provided to detect subwaveforms of an ECG waveform. Electrical impulses are detected between at least one pair of electrodes of two or more electrodes placed proximate to a beating heart and are converted to an ECG waveform for each heartbeat of the beating heart using the detector. One or more subwaveforms within P, Q, R, S, T, U, and J waveforms of the ECG waveform for each heartbeat or in an interval between the P, Q, R, S, T, U, and J waveforms that represent the depolarization or repolarization of an anatomically distinct portion of muscle tissue of the beating heart are detected using a signal processor. A processed ECG waveform that includes the one or more subwaveforms for each heartbeat is produced using the signal processor. The processed ECG waveform is received from the signal processor is displayed using a display device. | 12-10-2015 |
Chuan Hong, Shanghai CN
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20080277169 | HEIGHT AND WEIGHT MEASURING SCALE - A scale, comprising a body, wherein a supporting panel is disposed on the body; the supporting panel comprises an upper supporting panel and a lower supporting panel that can be folded and unfolded; the lower supporting panel is connected to the body via a rotatable axis disposed on a off-center position of the body, or a pair of slideways. The scale according to the invention is able to safely and effectively measure height and weight in a horizontal state, and the small size thereof is particularly useful in households. The scale is applicable to measuring the weight and height of infants, children, and adults. | 11-13-2008 |
20110072677 | HEIGHT MEASURING DEVICE - A height measuring device, including a scale, including graduation and a measuring part, and a positioning plate, the graduation and the measuring part are disposed on a right side of the scale, the measuring part is capable of moving along the graduation and indicating height, a measuring plate is disposed on the measuring part, and capable of folding as being perpendicular to or parallel to the scale, a top edge of the scale is capable of being buckled with a bottom edge of the positioning plate, a bottom edge of the scale is capable of being buckled with a top edge of the positioning plate, and a fixing part is disposed at the back of each of the scale and the positioning plate, and capable of being disposed in a vertical plane. | 03-31-2011 |
Chunlang Hong, Shanghai CN
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20150090575 | SAFETY MECHANISM FOR MEDICAL TREATMENT DEVICE AND ASSOCIATED METHODS - A safety mechanism for medical treatment devices includes a switch actuator that depresses a power activation switch after movement in a first direction followed movement in a second direction. The safety mechanism thus prevents accidental or unintentional delivery of power to a heating segment of the medical treatment device. | 04-02-2015 |
20150094704 | Medical Treatment Devices Having Adjustable Length and/or Diameter - The present embodiments enable the length and/or diameter of the heating segment of a medical treatment device to be adjusted on the fly during a treatment procedure, without a need to interrupt the procedure, thus allowing a single catheter to be used at different locations in a hollow anatomical structure. | 04-02-2015 |
20150094705 | MEDICAL TREATMENT DEVICES HAVING ADJUSTABLE LENGTH AND/OR DIAMETER - The present embodiments enable the length and/or diameter of the heating segment of a medical treatment device to be adjusted on the fly during a treatment procedure, without a need to interrupt the procedure, thus allowing a single catheter to be used at different locations in a hollow anatomical structure. | 04-02-2015 |
20150094706 | MEDICAL TREATMENT DEVICES HAVING ADJUSTABLE LENGTH AND/OR DIAMETER - The present embodiments enable the length and/or diameter of the heating segment of a medical treatment device to be adjusted on the fly during a treatment procedure, without a need to interrupt the procedure, thus allowing a single catheter to be used at different locations in a hollow anatomical structure. | 04-02-2015 |
20150094707 | CABLE MANAGEMENT SYSTEM FOR MEDICAL TREATMENT DEVICE - An enclosure of a power source for medical treatment devices includes a handle portion extending from a first surface of the enclosure. The handle portion includes a standoff extending away from the first surface, and a flange extending transversely from the standoff and defining a plane that is generally parallel to the first surface. Together, the first surface, the standoff, and the flange define an open annular space. A power cable may be wound about the standoff to at least partially occupy the open annular space. One or more notches in the flange are configured to seat the power cable to secure its loose end(s). In this manner, the power cable can be safely stored to reduce the risks that the power cable may become damaged, may interfere with other devices in the treatment area, or may be misplaced. | 04-02-2015 |
Chuyang Hong, Shanghai CN
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20130162826 | METHOD OF DETECTING AN OBSTACLE AND DRIVER ASSIST SYSTEM - To detect an obstacle in a single image captured using a single image sensor of a driver assist system, at least one image feature is established in the single image which extends along a line passing through a projection point of the image sensor. At least one line extending along a direction normal to a road surface in the world coordinate system is thereby identified based on the single image, which is used as a signature for an obstacle. | 06-27-2013 |
20150078619 | SYSTEM AND METHOD FOR DETECTING OBSTACLES USING A SINGLE CAMERA - The present application provides an obstacle detection system and method thereof. The obstacle detection method comprises: obtaining a first image captured by a camera at a first time point; identifying a vertical edge candidate in the first image, and measuring a first length of the vertical edge candidate based on the first image; obtaining a second image captured by the camera at a second time point; measuring a second length of the vertical edge candidate based on the second image; calculating a difference between the first length and the second length; and comparing the difference with a predetermined length difference threshold, if the difference is greater than the length difference threshold, outputting a message that an obstacle is found. | 03-19-2015 |
20150294167 | METHOD AND SYSTEM FOR DETECTING TRAFFIC LIGHTS - A method for detecting traffic lights is provided. The method includes: obtaining a color image captured by a camera; converting the color image into a first monochrome scale image; converting the first monochrome scale image into a first binary image; identifying a first set of candidate blobs in the first binary image based on at least one predetermined geometric parameter; and determine whether a first region in the color image, which first region corresponds to one of the first set of candidate blobs, is a green traffic light using a green traffic light classifier. The accuracy and efficiency may be improved. | 10-15-2015 |
20150332089 | SYSTEM AND METHOD FOR DETECTING PEDESTRIANS USING A SINGLE NORMAL CAMERA - The present application provides pedestrian detection system and method. A pedestrian detection method includes: obtaining an image captured by a camera; identifying a pedestrian candidate in the image; transforming the image into a top view image; calculating the actual height of the pedestrian candidate based on the top view image and extrinsic parameters of the camera; and determining whether the pedestrian candidate is a true positive by determining whether the actual height of the pedestrian candidate is within a predetermined pedestrian height range. The system and method of the present application have lower cost and higher accuracy compared with conventional technologies. | 11-19-2015 |
20150379354 | METHOD AND SYSTEM FOR DETECTING MOVING OBJECTS - A moving objects detection method is disclosed. The method may include: identifying a plurality of feature points based on a plurality of video frames; selecting from the plurality of feature points to form a first and a second groups of feature points based on correlations between the plurality of feature points; and identifying in at least one video frame two segments based on the first and the second groups of feature points, respectively, as detected moving objects, where a correlation between two feature points may include a distance component and a movement difference component, where the distance component is related to a distance between the two feature points, and the movement difference component is related to a difference between corresponding movements of the two feature points. A moving objects detection system is also provided. | 12-31-2015 |
Chu-Yang Hong, Shanghai CN
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20120301016 | IMAGE PROCESSING SYSTEM AND IMAGE PROCESSING METHOD - An image processing system and an image processing method are provided. The image processing method includes following steps. Transformation matrixes between color channel images are obtained according to feature points in the color channel images. A transformation matrix having the minimum distortion is selected to determine a shift datum color channel image. The other color channel images are transformed according to the transformation matrixes corresponding to the shift datum color channel image. The shift datum color channel image and the transformed color channel images are combined to obtain a shift calibrated image. Thereby, the dispersion problem is resolved. | 11-29-2012 |
20120301027 | IMAGE PROCESSING SYSTEM AND IMAGE PROCESSING METHOD - An image processing apparatus and a method thereof are provided. A plurality of target blur radii are obtained by calculating blur radiuses corresponding to the out of focus transform function between a deblurred datum color channel image and the other color channel images. A plurality of deblurred color channel images are obtained by respectively performing deblurring operations on the original channel images according to the target blur radii that are corresponding to the original channel images. The deblurred datum color channel image and the deblurred color channel images are combined to obtain a blur calibrated image. Accordingly, the image out of focus problem induced by dispersion can be solved. | 11-29-2012 |
Di Hong, Shanghai CN
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20150158879 | Novel indazoles for the treatment and prophylaxis of respiratory syncytial virus infection - The invention provides novel compounds having the general formula: | 06-11-2015 |
Fei Hong, Shanghai CN
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20140299852 | ORGANIC ELECTRONIC LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - An organic electronic light emitting device comprises a substrate; a first gate electrode formed on an upper surface of the substrate; a first insulating layer formed on the upper surface of the substrate and covering the first gate electrode; an organic layer formed on an upper surface of the first insulating layer and comprising at least two organic layers with different conductive type; a second insulating layer formed on an upper surface of the organic layer; a second gate electrode formed on an upper surface of the second insulating layer; and a source electrode and a drain electrode formed between the first and second insulating layers, and the source and drain electrodes located on both sides of the organic layer respectively. | 10-09-2014 |
James Hong, Shanghai CN
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20130099193 | Phase Change Memory and Manufacturing Method Therefor - The present invention discloses a phase change memory and a manufacturing method thereof. The phase change memory according to the present invention uses top electrodes provided on the top of storage nodes to heat the storage nodes such that a phase change layer in the storage nodes undergoes a phase change. In the phase change memory of embodiments of the present invention, the contact area between the top electrode and the storage node is relatively small, which is good for phase change. Moreover, each column of storage nodes is connected by the same linear top electrode, which can improve photo alignment shift margin. | 04-25-2013 |
20140070324 | SEMICONDUCTOR DEVICE WITH CONTACT HOLE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, a first barrier layer disposed on the substrate, a first dielectric layer disposed on the first barrier layer, and a second barrier layer disposed on the first barrier layer. The semiconductor device further includes a third barrier layer and a first metal gate each being disposed between a first portion of the second barrier layer and a second portion of the second barrier layer. The first metal gate is disposed between the third barrier layer and the substrate. The semiconductor device further includes a second dielectric layer. The third barrier layer is disposed between the first metal gate and the second dielectric layer. The semiconductor device further includes a second metal gate. The semiconductor device further includes a contact hole positioned between the first metal gate and the second metal gate. | 03-13-2014 |
20140151705 | NANOWIRES, NANOWIRE FIELDE-EFFECT TRANSISTORS AND FABRICATION METHOD - A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section. | 06-05-2014 |
20140312471 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has a plurality of closely spaced fins each coated at its top and sidewalls with a SiGe layer used for improving charge carrier mobility in a channel portion of the device. The sidewalls of the closely adjacent Fins are selectively thinned so as to prevent an undesired bridging of SiGe material between immediately adjacent ones of the Fins. A method of manufacturing the same comprises: providing a substrate having a plurality of tri-gate transistors, at least two fins of the tri-gate transistors being closely adjacent to each other, where respective top and sidewall surfaces of the fins are coated with a SiGe layer; performing a tilted ion implantation on the SiGe coated fins so as to partially convert the SiGe material into a predetermined etch resistant material (e.g., and oxide of the SiGe); and etching away the non-converted sidewall parts of the SiGe coating layers so as to provide greater spacing between the immediately adjacent sidewalls of the SiGe coated fins. | 10-23-2014 |
20150060767 | NANOWIRES AND NANOWIRE FIELDE-EFFECT TRANSISTORS - A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section. | 03-05-2015 |
Jason Hong, Shanghai CN
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20090300587 | DETERMINING DOMAIN DATA COVERAGE IN TESTING DATABASE APPLICATIONS - Testing systems and methods are provided for determining domain data coverage of a test of a codebase. The testing system may include a coverage program having a setup module configured to receive user input indicative of a target domain data table to be monitored during the test. The coverage program may further include a test module configured to programmatically generate a shadow table configured to receive coverage data, and to create one or more triggers on the target domain data table. The triggers may be configured, upon firing, to make entries of coverage data in the shadow table indicating that the trigger was fired during the test. The coverage program may also include an output module configured to compare the shadow table and the target domain data table to produce a coverage result, and to display the coverage result via a graphical user interface. | 12-03-2009 |
Jason Zhiqing Hong, Shanghai CN
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20080281692 | Virtual Points Clearinghouse - Systems and methods establish a virtual points clearinghouse. The clearinghouse redeems heterogeneous digital micro-payments-such as bonus points received from various points issuers-across diverse service providers. Points meant for exclusive redemption at one service provider may be directly redeemed for non-corresponding goods of a different service provider. In one implementation, the clearinghouse includes contracts between points issuers, service providers, and a clearinghouse, including intervening conversion rates. A user interface enables a user to manage multiple point balances from a computing device, cell phone, or other mobile device. The user interface enables the user to find diverse goods and to directly obtain the goods by redeeming diverse heterogeneous points. The clearinghouse includes an invoicing engine to enable money flow between users, points issuers, service providers, and the clearinghouse. | 11-13-2008 |
Jiannan Hong, Shanghai CN
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20130211051 | FUSION PROTEIN CONTAINING VEGI, AND PHARMACEUTICAL COMPOSITION AND USE THEREOF - Provided is an anti-angiogenic fusion protein, which comprises a vascular endothelial cell growth inhibitor (VEGI) or variant thereof, and other polypeptide such as IgG Fc. The fusion protein optionally comprises a linker. The fusion protein can induce the apoptosis of endothelial cells and inhibit the growtth of endothelial cells, so as to be used for treating tumor. Also provided are a pharmaceutical composition and use of the fusion protein. | 08-15-2013 |
Jingxian Hong, Shanghai CN
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20090297843 | NON-CHROME THIN ORGANIC-INORGANIC HYBRID COATING ON ZINCIFEROUS METALS - The present invention relates to a treatment solution for the deposition of a thin organic/inorganic hybrid coating on a zinciferous metal surface, comprising water and | 12-03-2009 |
Lei Hong, Shanghai CN
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20110264961 | SYSTEM AND METHOD TO TEST EXECUTABLE INSTRUCTIONS - This document discusses, among other things, a method of testing an Application Programming Interface (API) call that includes receiving data identifying a schema associated with web services together with an API call. Various example embodiments may relate to accessing a data repository associated with the schema to identify an API response corresponding to the API call. In some example embodiments, a message is returned that is based on a determination of whether the API call is valid. The example message may simulate an API response from web services. | 10-27-2011 |
20150212931 | SYSTEM AND METHOD TO TEST EXECUTABLE INSTRUCTIONS - This document discusses, among other things, a method of testing an Application Programming Interface (API) call that includes receiving data identifying a schema associated with web services together with an API call. Various example embodiments may relate to accessing a data repository associated with the schema to identify an API response corresponding to the API call. In some example embodiments, a message is returned that is based on a determination of whether the API call is valid. The example message may simulate an API response from web services. | 07-30-2015 |
Liang Hong, Shanghai CN
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20150259564 | EPOXY RESIN COMPOSITIONS - An epoxy resin composition including at least one epoxy resin having the Formula (I): | 09-17-2015 |
20160060383 | EPOXY RESIN COMPOSITIONS - A novel epoxy resin composition capable of forming a coating composition with a high volume solids content; a coating composition comprising such novel epoxy resin composition capable of providing a resultant coating films with balanced properties including good flexibility, good chemical resistance, short dry-hard time, desirable hardness, and good anti-corrosion performance; and the process of preparing the compositions. | 03-03-2016 |
Mike Hong, Shanghai CN
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20130072729 | METHODS AND COMPOSITIONS FOR INHIBITING POLYSTYRENE FORMATION DURING STYRENE PRODUCTION - Methods and compositions are provided for inhibiting the polymerization of a vinyl aromatic monomer, such as styrene monomer, during elevated temperature processing or distillation thereof. The compositions comprise an inhibitor combination of (A) a hydroxylamine and (B) a stable free radical plus a retarder that is either; (C) dinitrobutylphenol or (D) quinone methide. The ratio of (A) to (B) ranges from about 5% (A) to 95% (B) to about 95% (A) to about 5% (B). The compositions are added to the vinyl aromatic monomer in amounts sufficient to prevent polymerization during the distillation process. Typically the inhibitor combination is added to the vinyl aromatic monomer in an amount ranging from about 10 to 150 ppm of the monomer. Retarders are typically added in an amount ranging from 50 to 1500 ppm of the vinyl aromatic monomer. | 03-21-2013 |
20160052840 | METHODS AND COMPOSITIONS FOR INHIBITING POLYSTYRENE FORMATION DURING STYRENE PRODUCTION - Methods and compositions are provided for inhibiting the polymerization of a vinyl aromatic monomer, such as styrene monomer, during elevated temperature processing or distillation thereof. The compositions comprise an inhibitor combination of (A) a hydroxylamine and (B) a stable free radical plus a retarder that is either; (C) dinitrobutylphenol or (D) quinone methide. The ratio of (A) to (B) ranges from about 5% (A) to 95% (B) to about 95% (A) to about 5% (B). The compositions are added to the vinyl aromatic monomer in amounts sufficient to prevent polymerization during the distillation process. Typically the inhibitor combination is added to the vinyl aromatic monomer in an amount ranging from about 10 to 150 ppm of the monomer. Retarders are typically added in an amount ranging from 50 to 1500 ppm of the vinyl aromatic monomer. | 02-25-2016 |
Minghuang Hong, Shanghai CN
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20150057440 | TWO CRYSTAL FORMS OF GINSENOSIDE C-K AND METHOD FOR PREPARING SAME - Provided are ginsenoside C-K polymorphic forms and a method for preparing same. The ginsenoside C-K polymorphic forms are crystal form D and crystal form H. | 02-26-2015 |
20150065699 | GINSENOSIDE C-K POLYMORPHIC COMPOUNDS AND METHOD FOR PREPARING SAME - Provided are several types of ginsenoside polymorphic substances and a method for preparing same. In particular, new crystal form A, crystal form B, crystal form C, crystal form E, crystal form F, crystal form I, crystal form K, crystal form L, crystal form M, crystal form N, and crystal form O are involved. | 03-05-2015 |
Ping-Hua Hong, Shanghai CN
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20120124565 | LINKING MODEL INSTANCES TO PACKAGES - In a method | 05-17-2012 |
Ruiqing Hong, Shanghai CN
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20140001275 | Ultra-High-Pressure Fluid Injection Dynamic Orbit-Transfer System and Method Used in Aircraft | 01-02-2014 |
Shaozhi Hong, Shanghai CN
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20100307369 | TRAVELWAY STRUCTURE FOR MAGLEV TRANSPORTATION AND A METHOD FOR MANUFACTURING SAME - The present invention provides a travelway structure for maglev transportation comprises: a travelway girder having a concrete girder plate extending from two sides of the travelway girder; a pre-embedded member pre-embedded in the concrete girder plate; and a detachable member installed on the pre-embedded member via a fastener, wherein the pre-embedded member is machinable, and a position for installing the detachable member on the pre-embedded member is formed by a machining process after the travelway girder experiences deformations which lead to errors. A method for manufacturing a travelway structure for maglev transportation is also provided according to the present invention. Specifically, after a period of time, during which the travelway girder experiences most of the deformations caused by pre-stressed tension and gradual contraction and the like, the travelway girder along with the pre-embedded pieces are moved to the machine tools for machining the functional pre-embedded member. Consequently, the installing position of the detachable members can be precisely formed on the pre-embedded members. According to the present invention, the precision of the functional section of the travelway girder in each construction stage can be distributed reasonably so that the difficulty in controlling the precision of the functional section of the integral travelway girder can be overcome. Further, the defects of high cost, heavy weight, and inconvenience in transportation of the conventional travelway girder can be overcome. | 12-09-2010 |
Shouyu Hong, Shanghai CN
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20140141631 | PACKAGE MODULE, PACKAGE TERMINAL AND MANUFACTURING METHOD THEREOF - A package terminal is provided, which comprising: a base; an end portion with a first section; and a bent portion having a C-shape bend with a gradual change section, wherein the bent portion includes a first end and a second end, the first end is connected to the end portion, the second end is connected to the base, the bent portion includes a second section, and an area of the second section is smaller than an area of the first section. | 05-22-2014 |
20150216038 | PACKAGING SHELL AND A POWER MODULE HAVING THE SAME - The present invention provides a packaging shell and a power module having the same. The packaging shell mainly comprises an accommodating recess for receiving a substrate disposed with a plurality of electronic devices/components, so as to make the substrate be further assembled with a heat sink through the support of the packaging shell. Most importantly, in the present invention, the accommodating recess has a stepped surface for contacting with the substrate, and the stepped surface is a curve surface having a flatness difference. By such design, the compressional force generated when assembling the packaging shell, the heat sink and the system circuit board can be uniformly transmitted to substrate via the curve surface structure; such that the compressional force is avoid from being concentrated to a certain point on the substrate, and then the substrate is protected from being ruptured due to the action of the concentrated compressional force. | 07-30-2015 |
Shou-Yu Hong, Shanghai CN
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20090175014 | ASSEMBLED CIRCUIT AND ELECTRONIC COMPONENT - An assembled circuit comprising an inductive component, a connecting conductor, and a first electronic component is disclosed. The connecting conductor is adapted to wrap a first surface of the inductive component. The first electronic component stacks on the inductive component. The assembled circuit is electrically connected to the carrier via the connecting conductor. | 07-09-2009 |
20120327625 | ASSEMBLED CIRCUIT AND ELECTRONIC COMPONENT - An assembled circuit comprising a substrate, a coil, a first conductive segment, a second conductive segment, a first through-hole connector and a second through-hole connector is disclosed. The first conductive segment is electrically connected to one end of the first through-hole connector, the other end of the first through-hole connector is electrically connected to one end of the second through-hole connector via the first conductive segment, and the other end of the second through-hole connector is electrically connected to the second conductive segment. | 12-27-2012 |
20140085848 | ASSEMBLED CIRCUIT AND ELECTRONIC COMPONENT - An assembled circuit is disclosed, wherein the assembled circuit comprises an inductor having a top surface, a bottom surface and side surfaces, wherein each of a plurality of conductors extends from the top surface to the bottom surface via one of the side surfaces of the inductor, wherein a circuit board is disposed over the top surface of the first electronic component and electrically connected to the plurality of conductors and a plurality of pins disposed on the bottom surface of the inductor for connecting to another circuit board. | 03-27-2014 |
20140117495 | SWITCH CIRCUIT PACKAGE MODULE - A switch circuit package module includes a semiconductor switch unit and a capacitor unit. The semiconductor switch unit includes sub micro-switch elements. The capacitor unit is arranged at a periphery of the semiconductor switch unit or stacked on a surface of the semiconductor switch unit, such that impedances of commutation loops between the capacitor unit and the sub micro-switch elements are close to or the same with each other. | 05-01-2014 |
20150085454 | POWER MODULE - A power module is disclosed. The power module includes a first substrate, a first metal layer, at least one conductive structure and at least one power device. The first metal layer is disposed on the first substrate. The first metal layer has a first thickness d1. The first thickness d1 satisfies: 5 μm≦d1≦50 μm. The conductive structure is disposed at a position different to the first metal layer on the first substrate. The conductive structure has a second thickness d2. The second thickness d2 satisfies: d2≧100 μm. The power device is disposed on the first substrate, the first metal layer or the conductive structure. The driving electrode of the power device is electrically connected to the first metal layer. The power electrode of the power device is electrically coupled to the conductive structure. | 03-26-2015 |
20150180351 | POWER ELECTRONIC CIRCUIT AND POWER MODULE - Disclosed herein is a power electronic circuit having a reference ground and a differential mode loop unit. The differential mode loop unit has a capacitance component, a switch and an electronic component, wherein the capacitance component has a first end, the switch has a first end connecting in series with the capacitance component, the electronic component has a first end, the electronic component connects in series with the capacitance component and the switch, the capacitance component and switch are packaged in a power module, the power module has a trace and at least one output pin connected to reference ground, wherein the first end of the switch or the first end of the electronic component is only connected to the first end of the capacitance component through the trace, and the first end of the capacitance component is connected to reference ground through the output pin. | 06-25-2015 |
20150228400 | ASSEMBLED CIRCUIT AND ELECTRONIC COMPONENT - An electrical component is disclosed, the electrical component comprising: a magnetic body having a top surface, a bottom surface, wherein at least one first conductive through hole is formed from the top surface to bottom surface of the magnetic body; and a coil disposed in the magnetic body, wherein a first end of the coil is electrically connected to one of the at least one first conductive through hole. | 08-13-2015 |
20150318234 | SWITCH CIRCUIT PACKAGE MODULE - A switch circuit package module includes at least a semiconductor switch unit and at least a first capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element and the second semiconductor switch element include a plurality of sub micro-switch elements. The capacitor unit includes a plurality of capacitors configured to cooperate with the sub micro-switch elements. The capacitors are arranged in a symmetrical distribution surrounded the semiconductor switch unit, such that impedances of any two symmetrical commutation loops each of which mainly consists of one capacitor and two sub micro-switch elements from the first semiconductor switch element and second semiconductor switch element respectively are close to or the same with each other. | 11-05-2015 |
20150318242 | SWITCH CIRCUIT PACKAGE MODULE - A switch circuit package module includes a semiconductor switch unit and a capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The second semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The capacitor unit includes a plurality of capacitors. The semiconductor switch unit includes a plurality of common electrodes, each common electrode connects the source electrode of one sub micro-switch element in the first semiconductor switch element with the drain of one sub micro-switch element in the second semiconductor switch element and is disposed adjacent to at least one drain electrode from the first semiconductor switch element or one source electrode from the second semiconductor switch element. | 11-05-2015 |
Sujuan Hong, Shanghai CN
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20100222064 | METHOD AND DEVICE FOR INITIAL SYNCHRONIZATION BETWEEN GSM SYSTEM AND TD-SCDMA SYSTEM - A method for initial synchronization with TD-SCDMA system in the connection mode of GSM system, to resolve the problem of the downlink synchronization codes (DwPTS) may be undetectable or taking too much time to be detected when a TD-SCDMA/GSM dual-mode terminal is examining TD-SCDMA frames in GSM connection mode with prior art; in the connection mode of the GSM system, the method receives or transmits service data within the service time slots of the GSM frame at the radio frequency band of the GSM system, and receives TD-SCDMA signal within the idle time slots of the GSM frame at the radio frequency band of the TD-SCDMA system, and detects DwPTS in the received TD-SCDMA signal, thus the terminal in the connection mode of the GSM system can quickly detect the DwPTS in TD-SCDMA frames, achieving the initial synchronization of the TD-SCDMA/GSM dual-mode system. A GSM system processing apparatus and a communication apparatus are also disclosed in the invention. | 09-02-2010 |
Sun Hong, Shanghai CN
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20160111321 | DEVICE ISOLATION STRUCTURE AND MANUFACTURE METHOD - A method for forming a semiconductor device includes forming a buried doped layer in a semiconductor substrate and forming a plurality of first trenches that expose the buried doped layer. A first dielectric layer is formed covering sidewalls of the first trenches, and a doped polysilicon layer is formed covering side surfaces of the first dielectric layer and bottom portions of the first trenches. The method also includes forming a second trench in each of the plurality of first trenches, each second trench extending through a bottom portion of the doped polysilicon layer and the buried doped layer into a lower portion of the substrate. The method also includes forming a second dielectric layer inside each second trench. An isolation pocket structure is formed that includes the doped buried layer at the bottom and sidewalls that includes the doped polysilicon layer sandwiched between the first and second dielectric layers. | 04-21-2016 |
Tao Hong, Shanghai CN
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20140188875 | METHOD FOR MEASURING COEFFICIENT OF CONTACTS OF ONLINE SOCIAL NETWORK - The present disclosure relates to online social networks. In particularly it is relates to a method for measuring coefficient of contacts of online social network. A method for measuring coefficient of contacts of online social network comprises the following steps that: the social network comprises at least one tree system, the sum of the coefficients of contacts of each tree system is 1, and the tree system is composed of root-level users, trunk-level users and leaf-level users; each user in the social network belongs to a unique tree system and has a unique code; the leaf-level user has no subordinate relationship of contacts, thus the coefficient of contacts of the leaf-level user is zero; the coefficient of contacts of each of the trunk-level users of the tree system is as follows: Si=ΣSi+1+j/n/(i+1). The whole situation of contacts and specific situation of contacts of any group can be evaluated quantitatively in social network sites, so as to provide the basis for commercial activities and social media activities of the social network sites. | 07-03-2014 |
Wei Hong, Shanghai CN
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20150361208 | HYBRID LATEX COMPRISING POLYMERIC PARTICLES HAVING CORE-SHELL STRUCTURE AND ITS PREPARATION METHOD - The invention relates to a hybrid latex comprising polymeric particles having core-shell structure, wherein: (1) the comonomers of the core comprise: (a) monovinyl aromatic compounds, and (b) unsaturated carboxylic acid esters; (2) the comonomers of the shell comprise: (a) monovinyl aromatic compounds, and (b) conjugated dienes; wherein the glass transition temperature of the core is in the range of −50° C. to 50° C., and the glass transition temperature of the shell is in the range of −50° C. to 50° C. The invention also relates to the use of the hybrid latex in polymer waterproofing membrane and polymer modified mortars. | 12-17-2015 |
Weibi Hong, Shanghai CN
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20120153747 | USB CHARGER, ITS SWITCH CONTROL SYSTEM AND METHOD, AND A USB INTERFACE CHARGER FOR A LAPTOP - The present invention discloses a switch control system and its method for a USB charger, wherein the switch control system controls the on-off status of the charging circuit according to whether a charging load is connected or not. The switch control system comprises a first switch and an on-off control unit of the first switch. The first switch connects to a charging power and a converter; the on-off control unit of the first switch connects to the USB output interface and the first switch to control the on-off status of the first switch according to whether the charging load is connected or not. The switch control system and the method for the USB charger disclosed by the present invention realize automatic switching on and off of the USB operating circuit when a load is connected to or removed from the USB output interface. | 06-21-2012 |
20120212076 | PROTECTION CIRCUIT FOR ELECTRIC OUTLET - A protection circuit for electric outlet includes: a switch control circuit ( | 08-23-2012 |
20140126262 | INVERTER CIRCUIT - An inverter circuit includes a DC-AC inverter, a sampling circuit, a voltage-current conversion circuit, an isolation circuit and an electronic starter switch. The sampling circuit includes a first and a second diode connected in parallel and opposite in polarity. A forward voltage drop at the first diode blocks the conductance of a first transistor of the voltage-current conversion circuit when there is no load, and a forward voltage drop at the second diode turns on the first transistor when there is a load. The connection of the first and second diodes to a second AC output terminal of the DC-AC inverter nearly has no impact on the AC output of the inverter circuit. These enable the inverter circuit to have low power consumption when there is no load and to be immediately activated upon connection of a load, thereby achieving detection of a load smaller than 0.1 W. | 05-08-2014 |
Xiangchun Hong, Shanghai CN
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20140175151 | Linear Staple with a Multi-Functional Retaining Pin Subassembly - The present invention provides a linear stapler having a multi-functional retaining pin subassembly. The linear stapler comprises a handle stem connecting an anvil to a handle, and the retaining pin subassembly is movably supported on the handle stem and comprises a connecting cover having a retaining pin extending from the connecting cover. The present invention also provides a multi-functional retaining pin subassembly. The retaining pin subassembly can achieve cartridge alignment and tissue retention during the firing of the stapler and protect tissue from unintended damage. | 06-26-2014 |
Yu Hong, Shanghai CN
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20140365731 | Systems and Methods for Cache Management for Universal Serial Bus Systems - Systems and methods are provided for cache management. An example system includes a cache and a cache-management component. The cache includes a plurality of cache lines corresponding to a plurality of device endpoints, a device endpoint including a portion of a universal-serial-bus (USB) device. The cache-management component is configured to receive first transfer request blocks (TRBs) for data transfer involving a first device endpoint and determine whether a cache line in the cache is assigned to the first device endpoint. The cache-management component is further configured to, in response to no cache line in the cache being assigned to the first device endpoint, determine whether the cache includes an empty cache line that contains no valid TRBs, and in response to the cache including an empty cache line, assign the empty cache line to the first device endpoint and store the first TRBs to the empty cache line. | 12-11-2014 |
20150026369 | Systems and Methods for Managing USB Data Transfers - System and methods are provided for managing universal-serial-bus (USB) data transfers. An example system includes a non-transitory computer-readable storage medium including a first scheduling queue for sorting endpoints and a host controller. The host controller is configured to: store a plurality of endpoints for data transfers to the storage medium, an endpoint corresponding to a portion of a USB device; sort the plurality of endpoints in a first order; generate a first transmission data unit including multiple original data packets, the original data packets being allocated to the plurality of endpoints based at least in part on the first order; and transfer the first transmission data unit. | 01-22-2015 |
Yunhai Hong, Shanghai CN
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20130331312 | MEDICINAL COMPOSITION CONTAINING ECHINOCANDIN ANTIFUNGAL AGENT MICAFUNGIN AND PREPARATION METHOD AND USE THEREOF - The present invention provides a medicinal composition containing micafungin or a pharmaceutically acceptable salt thereof and trehalose as a stabilizing agent. | 12-12-2013 |
20130338060 | LIQUID MEDICINAL COMPOSITION CONTAINING ECHINOCANDIN ANTIFUNGAL AGENT MICAFUNGIN - The present invention provides a liquid medicinal composition containing micafungin or a pharmaceutically acceptable salt thereof and a stabilizing agent. | 12-19-2013 |
20140221274 | LOW IMPURITY CONTENT CASPOFUNGIN PREPARATION, METHOD FOR PREPARING SAME, AND USE THEREOF - Disclosed is a low impurity content caspofungin pharmaceutical composition, also disclosed is a method for preparing the low impurity content caspofungin pharmaceutical composition. The caspofungin pharmaceutical composition provided in the present invention is provided with great stability. | 08-07-2014 |
Zhiliang Hong, Shanghai CN
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20110068757 | Switching converter having a plurality N of outputs providing N output signals and at least one inductor and method for controlling such a switching converter - This invention provides a switching converter having a plurality N of outputs providing N output signals and at least one inductor, comprising a first controlling device for controlling the total energy flowing over the inductor to the N outputs dependent on a first control signal, at least a second controlling device for distributing the total energy between the N outputs by means of at least a second control signal, wherein the first controlling device is coupled to all N outputs for receiving a number M of the respective feedback output signals of the N outputs, M≦N, wherein the first controlling device comprises first means for weighting the M feedback output signals and second means for providing the first control signal dependent on the weighted M feedback output signals. | 03-24-2011 |
20120062030 | Switching converter and method for controlling a switching converter - This invention provides a switching converter having a number N of outputs providing N output signals, said switching converter being operable in at least a boost mode. The switching converter has at least one inductor, a number of switches, and a controlling device for controlling a charging time of the at least one inductor at least by the switches such that a discharging time of the at least one inductor is constant | 03-15-2012 |
Zhiqing Hong, Shanghai CN
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20100125762 | Form Validation with Table Driven Error Handling - Various embodiments provide a validation framework to validate whether data entered in a web application is valid. The framework includes a validation resource that contains a validation rule for the web application. The framework also includes a validation group web control that can generate client validation script that is useable by a client to validate whether the entered data is valid. In at least some embodiments, an event table that specifies the validation rules is used to present an error message when the entered data is not valid. | 05-20-2010 |
Zhongshan Hong, Shanghai CN
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20100123179 | Two-Step Self-Aligned Source Etch With Large Process Window - System and method for self-aligned etching. According to an embodiment, the present invention provides a method for performing self-aligned source etching process. The method includes a step for providing a substrate material. The method also includes a step for forming a layer of etchable oxide material overlying at least a portion of the substrate material. The layer of etchable oxide material can characterized by a first thickness. The layer of etchable oxide material includes a first portion, a second portion, and a third portion. The second portion is positioned between the first portion and the third portion. The method additionally includes a step for forming a plurality of structures overlying the layer of etchable oxide material. The plurality of structures includes a first structure and a second structure. | 05-20-2010 |
20110237009 | LCOS DISPLAY UNIT AND METHOD FOR FORMING THE SAME - An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shielding layer on a pixel switch circuit layer. Therefore the pixel switch circuit and the capacitor are in vertical distribution, that is, the switch circuit and the capacitor both have an allowable design area of the size of one pixel. Another embodiment of the present invention provides a method for forming a Liquid Crystal on Silicon (LCOS) display unit. | 09-29-2011 |
20120135594 | METHOD FOR FORMING A GATE ELECTRODE - A method for forming a gate electrode includes: providing a substrate; forming a gate dielectric layer and forming a sacrificial layer, the sacrificial layer including doping ions, a density of the doping ions in the sacrificial layer decreasing with increasing distance from the substrate; forming a hard mask layer; patterning the sacrificial layer and the hard mask layer; removing part of the patterned sacrificial layer by wet etching with the patterned hard mask layer as a mask, to form a dummy gate electrode which has a top width bigger than a bottom width, and removing the patterned hard mask layer; removing the dummy gate electrode and filling a gate trench with gate material to form a gate electrode which has a top width bigger than a bottom width, which facilitates the filling of the gate material and can avoid or reduce cavity forming in the gate material. | 05-31-2012 |
20120220128 | METHOD FOR MANUFACTURING A TRANSISTOR - The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer. | 08-30-2012 |
20120273851 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device includes forming a structure comprising an interlayer dielectric layer on a substrate, an ultra-low-k material layer on the interlayer dielectric layer and a plug. The plug passes through the interlayer dielectric layer and the ultra-low-k material layer, and is formed of a first metal material. The method further includes removing an upper portion of the plug by etching to form a recessed portion, and filling the recessed portion with a second metal material. According to the method, contact-hole photolithography is performed only once, and thus avoids alignment issues that may occur when contact-hole photolithography needs to be performed twice. | 11-01-2012 |
20120273962 | SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device having an air gap, includes: providing a substrate having a first dielectric layer and a second dielectric layer formed thereon successively; forming a mask layer on the second dielectric layer; patterning the first and the second dielectric layer by using the mask layer as a mask so as to form a plurality of grooves; filling a conducting material into the grooves; removing redundant conducting material on the second dielectric layer utill the second dielectric layer is exposed so as to form a plurality of conductive trenches; forming a molecular sieve on the second dielectric layer and the conductive trenches; and removing the second dielectric layer partly or completely by flowing a reactant gas towards the second dielectric layer through the molecular sieve, so as to form an air gap. It is novel and simple to form an air gap through molecular sieve. | 11-01-2012 |
20120276738 | METHOD FOR FORMING THROUGH SILICON VIA STRUCTURE - A method for forming a TSV structure includes providing a silicon substrate with an interlayer dielectric layer formed thereon, forming a hard mask structure including a first hard mask layer including a metal element on the interlayer dielectric layer and a second hard mask layer on the first hard mask layer; forming an opening through the hard mask structure and the interlayer dielectric layer, the opening has a bottom and sidewalls in the silicon substrate. The method further includes depositing an insulating material on the hard mask structure and on the bottom and the sidewalls of the opening, subsequently removing the insulating material and the second hard mask layer until the first hard mask layer is exposed, and filling a conductive material into the opening. The method also includes removing the conductive material and the first hard mask layer by a CMP process until the interlayer dielectric layer is exposed. | 11-01-2012 |
20130299875 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer. | 11-14-2013 |
20130341642 | MOS TRANSISTOR, FABRICATION METHOD THEREOF, AND SRAM MEMORY CELL CIRCUIT - Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a channel region including an asymmetric stressing layer having a stress gradually varied from a compressive stress to a tensile stress or from a tensile stress to a compressive stress from a first end of the channel region adjacent to a source region to a second end of the channel region adjacent to a drain region. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase a source-drain saturation current in a write operation and to reduce a source-drain saturation current in a read operation. Read and write margins of the SRAM can be increased. | 12-26-2013 |
20140001474 | CMOS DEVICE AND FABRICATION METHOD | 01-02-2014 |
20140110793 | CMOS TRANSISTOR AND FABRICATION METHOD - Exemplary embodiments provide transistors and methods for forming the transistors. An exemplary CMOS transistor can be formed by epitaxially forming a first stress layer in/on a semiconductor substrate having a first region including a first gate structure and a second region including a second gate structure. A barrier layer can be formed to cover the second region and to expose the first region. The barrier layer can be used as a mask to remove a portion of the first stress layer from the first region. A second stress layer can be formed in a groove formed in the semiconductor substrate on sides of the first gate structure in the first region. The fabrication method can be simplified and the formed CMOS transistors can have high carrier mobility. | 04-24-2014 |
20140145302 | MIM CAPACITOR AND FABRICATION METHOD - Various embodiments provide an MIM capacitor and fabrication method thereof. An exemplary MIM capacitor can include a dielectric layer disposed over a substrate containing a conductive layer. The dielectric layer can include a groove to expose the conductive layer in the substrate. A first metal layer can be disposed on a bottom surface and a bottom portion of a sidewall surface of the groove. A top surface of the first metal layer on the sidewall surface of the groove can be lower than a top surface of the dielectric layer. A dielectric material layer can be disposed on the first metal layer and on a top portion of the sidewall surface of the groove. A second metal layer can be disposed on the dielectric material layer; and a third metal layer can be disposed on the second metal layer to fill the groove. | 05-29-2014 |
20140191339 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second gate dielectric layer; and forming a first metal gate and a second metal gate on the first gate dielectric layer and the second gate dielectric layer, respectively. Further, the method includes forming a third dielectric layer on the second metal gate; and forming a second dielectric layer on the first dielectric layer. Further, the method also includes forming at least one opening exposing at least one first metal gate and one first doped region; and forming a contact layer contacting with the first metal gate and the first doped region to be used as a share contact structure. | 07-10-2014 |
20140291805 | SEMICONDUCTOR DEVICE CONTAINING MIM CAPACITOR AND FABRICATION METHOD - A semiconductor device containing an MIM capacitor and its fabrication method are provided. A metal-insulator-metal (MIM) capacitor is formed on a first interlayer dielectric layer covering a substrate. The MIM capacitor includes a bottom electrode layer and a top electrode layer that are isolated from and laterally staggered with one another. A second interlayer dielectric layer is formed to cover both the MIM capacitor and the first interlayer dielectric layer. A first conductive plug and a second conductive plug are formed each passing through the second interlayer dielectric layer. The first conductive plug contacts a sidewall and a surface portion of the top electrode layer of the MIM capacitor and the second conductive plug contacts a sidewall and a surface portion of the bottom electrode layer of the MIM capacitor. | 10-02-2014 |
20150035088 | SEMICONDUCTOR STRUCTURES - A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second gate dielectric layer; and forming a first metal gate and a second metal gate on the first gate dielectric layer and the second gate dielectric layer, respectively. Further, the method includes forming a third dielectric layer on the second metal gate; and forming a second dielectric layer on the first dielectric layer. Further, the method also includes forming at least one opening exposing at least one first metal gate and one first doped region; and forming a contact layer contacting with the first metal gate and the first doped region to be used as a share contact structure. | 02-05-2015 |
20150061087 | TRIPLE PATTERNING METHOD - A triple patterning method is provided. The method includes providing a substrate having a first region and a second region; and forming a first material layer. The method also includes forming a second material layer; and forming a plurality of core patterns on the second material layer in the first region. Further, the method includes forming sidewall spacers on side surfaces of the core patterns; and forming first patterns on the first material layer. Further, the method includes forming a third material layer on the first material layer and the first patterns; and forming second patterns on the third material layer in the first region and third patterns on the third material layer in the second region. Further, the method also includes forming fourth patterns; and forming triple patterns on the substrate in the first region and fifth patterns on the substrate in the second region. | 03-05-2015 |
20150108652 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device and its fabrication method are provided. A first dielectric layer is provided to cover a substrate. The first dielectric layer contains a plurality of first conductive layers. A portion of each first conductive layer is removed to form a plurality of first openings in the first dielectric layer. A second dielectric layer is formed in each first opening. A third dielectric layer having second-openings are formed on the first dielectric layer and on the second dielectric layers. Each second-opening exposes at least two adjacent second dielectric layers. Second dielectric layers exposed by a first second-opening are removed to form third openings to expose corresponding first conductive layers. Second conductive layers are formed in the third opening and the second-openings including the first second-opening. Stable electrical interconnections with high quality electrical isolations can be provided. | 04-23-2015 |
20150145043 | RF SOI SWITCH WITH BACKSIDE CAVITY AND THE METHOD TO FORM IT - An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer, a transistor disposed on the second semiconductor substrate and having a bottom insulated by the insulating layer, a plurality of shallow trench isolations disposed on opposite sides of the transistor, a cavity disposed below the bottom of the transistor, and a plurality of isolation plugs disposed on opposite sides of the cavity. By having a cavity located below the transistor, parasitic couplings between the transistor and the substrate are reduced and the performance of the integrated circuit is improved. | 05-28-2015 |
20150145045 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer. | 05-28-2015 |
20150187781 | MEMORY DEVICE AND METHOD FOR FORMING THE SAME - Various embodiments provide memory devices and methods for forming the same. A substrate is provided, the substrate having one or more adjacent memory cells formed thereon. Each memory cell includes a gate structure, a control gate layer, and a first mask layer. A portion of the control gate layer is removed, to reduce a size of an exposed portion of the control gate layer in a direction parallel to a surface of the substrate. An electrical contact layer is formed on an exposed sidewall of the control gate layer and an exposed surface of the substrate. A barrier layer is formed on a sidewall of the memory cell. A conductive structure is formed on the substrate. The conductive structure has a significantly larger distance from control gate layer than from the gate structure, and the barrier layer forms an isolation layer between the conductive structure and the control gate layer. | 07-02-2015 |
20150210536 | MEMS PRESSURE SENSORS AND FABRICATION METHOD THEREOF - A MEMS capacitive pressure sensor is provided. The pressure sensor includes a substrate having a first region and a second region, and a first dielectric layer formed on the substrate. The pressure sensor also includes a first electrode layer formed on the first dielectric layer, and a second dielectric layer having first openings formed on the first electrode layer. Further, the pressure sensor includes conductive sidewalls connecting with the first electrode layer formed on sidewalls of the first openings, and a second electrode layer with a portion formed on the second dielectric layer in the second region and the rest suspended over the conductive sidewalls in the first region. Further, the pressure sensor also includes a chamber between the conductive sidewalls and the second electrode layer; and a third dielectric layer formed on the second electrode layer exposing a portion of the second electrode layer in the first region. | 07-30-2015 |
20150255473 | FLASH MEMORY AND FABRICATION METHOD THEREOF - A flash memory fabrication method includes: providing a substrate having a plurality of floating gate structures separated by trenches, which includes at least a source trench and a drain trench, and source/drain regions; forming a metal film on the substrate and on the floating gate structures; performing a thermal annealing process on the metal film to form a first silicide layer on the source regions and a second silicide layer on the drain regions; removing portions of the metal film to form a metal layer on the bottom and lower sidewalls of the source trench and contacting with the first silicide layer, and forming a dielectric layer on the substrate and the floating gate structures, covering the source trench and the drain trench. Further, the method includes forming a first conducting structure and one or more second conducting structures in the dielectric layer. The first conducting structure is on the metal layer in the source trench, the second conducting structures are on the second silicide layer, and adjacent first conducting structure and second conducting structure have a predetermined distance. | 09-10-2015 |
20150279785 | ELECTRICAL INTERCONNECTION STRUCTURE AND FABRICATION METHOD THEREOF - An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and having a first lattice structure and a first grain size, wherein the first thickness is greater than the first grain size; and performing an annealing process to change the first lattice structure of the conductive film to a second lattice structure and to change the first grain size to a second grain size. The second grain size is greater than the first grain size, and the first thickness is greater than or equal to the second grain size. The method also includes etching portion of the conductive film to form at least one conductive layer; etching portion of the conductive layer to form at least one trench having a depth smaller than the first thickness in the conductive layer to form an electrical interconnection wire and conductive vias; and forming a dielectric layer covering the substrate, sidewalls of the conductive layer, and the trench. | 10-01-2015 |
20150295036 | NANOWIRE DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region. | 10-15-2015 |
20150318279 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and fabrication methods are provided. A semiconductor substrate is provided having dummy gate structures formed thereon. A stress layer is formed in the semiconductor substrate between adjacent dummy gate structures. A first dielectric layer is formed on the semiconductor substrate, the stress layers, and the sidewall spacers of the dummy gate structures, exposing dummy gate electrode layers. Gate structures are formed in the dielectric layer to replace the dummy gate structures. The gate structures include functional gate structures and at least one non-functional gate structure. The at least one non-functional gate structure is removed to form at least one second opening in the first dielectric layer. At least one third opening is formed in the semiconductor substrate at a bottom of the at least one second opening. A second dielectric layer is formed in the at least one second opening and the at least one third opening. | 11-05-2015 |
20160027659 | PATTERNED FEATURE AND MULTIPLE PATTERNING METHOD THEREOF - A multiple patterning method is provided. The multiple patterning method includes providing a substrate; and forming a sacrificial film on the substrate. The multiple patterning method also includes forming a first mask film on the sacrificial film; and forming a second mask film for subsequently forming a certain structure to protect the subsequently formed mask structures on the first mask film. Further, the multiple patterning method includes forming first mask structures and second mask structures by etching the second mask film, the first mask film, and the sacrificial film. | 01-28-2016 |
20160035816 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure is provided. The semiconductor structure includes a substrate; and a plurality of parallel first conductive layers formed on the substrate. The semiconductor structure also includes a composite magnetic structure having a plurality of magnetic layers and a plurality of insulation layers with a sandwich arrangement formed on a portion of the substrate and portions of surfaces of the plurality of first conductive layers. Further, the semiconductor structure includes a plurality of first conductive vias and a plurality of second conductive vias formed on the first conductive layers at both sides of the composite magnetic structure. Further, the semiconductor structure also includes a plurality of second conductive layers formed on a top surface of the composite magnetic structure, top surfaces of the first conductive vias, and top surfaces of the second conductive vias to form at least one coil structure wrapping around the composite magnetic structure. | 02-04-2016 |
20160087029 | MIM CAPACITOR - Various embodiments provide an MIM capacitor and fabrication method thereof. An exemplary MIM capacitor can include a dielectric layer disposed over a substrate containing a conductive layer. The dielectric layer can include a groove to expose the conductive layer in the substrate. A first metal layer can be disposed on a bottom surface and a bottom portion of a sidewall surface of the groove. A top surface of the first metal layer on the sidewall surface of the groove can be lower than a top surface of the dielectric layer. A dielectric material layer can be disposed on the first metal layer and on a top portion of the sidewall surface of the groove. A second metal layer can be disposed on the dielectric material layer; and a third metal layer can be disposed on the second metal layer to fill the groove. | 03-24-2016 |
20160093513 | SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHODS - A method for forming a semiconductor device includes providing a semiconductor structure which has a substrate and N sub-stack structures numbered from 1 to N, where N is an integer. Each sub-stack structure includes two sub-stacks, and a mask layer overlying the N sub-stack structures. The method also includes repeatedly removing a portion of the mask layer and removing exposed portions of the sub-stack structures to form a first stepped structure, and forming first spacers on sidewalls of the mask layer and the sub-stack structures in the stepped structure, each spacer covering a portion of the exposure portions of the sub-stack structures. The method further includes using the mask layer and the first spacers as masks to remove exposed portions of an upper sub-stack in the first stepped structure, and removing the mask layer and the spacers to form a second stepped structure. | 03-31-2016 |
20160093693 | METHODS FOR FORMING VERTICAL SEMICONDUCTOR PILLARS - A method for forming a semiconductor device includes providing a semiconductor structure, which includes a semiconductor substrate and a first mask layer on the substrate. The first mask layer is used to form a plurality of first trenches that extends into the substrate and extends laterally in a first direction and do not intersect each other. The first trenches are then filled with a fill material. Next, a second mask layer is formed on the semiconductor structure filled with the fill material. The second mask layer is then used to form a second plurality of trenches in the semiconductor substrate that extend laterally in a second direction and do not intersect each other. Each of the second trenches intersects at least one of the first plurality of trenches. Next, the fill material is removed to form a plurality of vertical pillars defined by intersecting first trenches and second trenches. | 03-31-2016 |
20160111516 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides semiconductor devices and fabrication methods thereof. A stacked substrate includes an insulating layer between a substrate and a semiconductor layer. First openings are formed in the semiconductor layer to define a first distance between adjacent sidewalls of adjacent first openings. Spacers are formed on sidewall surfaces of each first opening. Second openings corresponding to the first openings are formed through the insulating layer and into the substrate. The sidewall surfaces of the substrate in the second openings are etched to define a second distance between adjacent substrate sidewalls of adjacent etched second openings. The second distance is shorter than the first distance. An isolation layer is formed in the first and second openings. Conductive structures are formed on the semiconductor layer on both sides of a gate structure formed on the semiconductor layer. The conductive structures penetrate through the isolation layer and into the substrate. | 04-21-2016 |
Zhong Shan Hong, Shanghai CN
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20110089479 | SCALABLE FLASH EEPROM MEMORY CELL WITH FLOATING GATE SPACER WRAPPED BY CONTROL GATE AND METHOD OF MANUFACTURE - A polysilicon spacer as a floating gate of a Flash memory device. An advantage of such spacer structure is to reduce a cell size, which is desirable for state-of-the-art Flash memory technology. In a preferred embodiment, the floating gate can be self-aligned to a nearby and/or within a vicinity of the select gate of the cell select transistor. In a preferred embodiment, the present invention preserves a tunnel oxide layer after the removal, using dry etching, a polysilicon spacer structure on the drain side of the select transistor gate. More preferably, the present method provides for a certain amount of tunnel oxide to remain so as to prevent the active silicon area in the drain region of the memory cell from being etched by the dry etching gas. | 04-21-2011 |
20120146123 | SCALABLE FLASH EEPROM MEMORY CELL WITH FLOATING GATE SPACER WRAPPED BY CONTROL GATE AND METHOD OF MANUFACTURE - A flash memory cell includes a substrate having a surface region and a flash memory cell structure on the surface region. The flash memory cell structure includes a gate dielectric layer on the surface region, a select gate on the gate dielectric layer, a cap oxide layer on the select gate, an oxide spacer on a first edge of the select gate, a tunnel oxide layer on a first region and on a second region of the surface region. The second region is an active region. The flash memory cell structure further includes a poly spacer on the first edge of the oxide spacer and a portion of the tunnel oxide layer on the first region, an ONO layer on at least the poly spacer and a control gate layer on the ONO layer. | 06-14-2012 |
Zhongsheng Hong, Shanghai CN
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20090073118 | ELECTRONIC APPARATUS WITH DISPLAY SCREEN - The present invention provides an electronic apparatus with display screen, wherein a direction key is provided on a side of the electronic apparatus, the display screen and a second menu display area, a plurality of first menu items arranged in right-left direction are displayed in the first menu display area, and a plurality of second menu items arranged in upper-down direction are displayed in the second menu display area, wherein the direction key and the first menu display area are positioned substantially on the same straight line extending in the right-left direction; the first menu items in the first menu display area can be selected when front portion/back portion of the direction key is pressed; the second menu items corresponding to the selected first menu items can be selected in the second menu display area when upper portion/lower portion of the direction key is pressed; and the selected menu items can be confirmed when center portion of the direction key is pressed. Compared with the prior art, in the present invention, the position where the direction key is provided corresponds substantially to the first menu display area in the horizontal direction, therefore, there is the intuitive relationship of correspondence between the direction key and the first menu, and the user can operate it more intuitively and conveniently. | 03-19-2009 |