Robinett, US
Christopher Robinett, Powder River, WY US
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20150042191 | Brake Caliper Magnet Energy Generating Apparatus - This invention generates electric power from the rotational motion of the braking system of wheeled vehicle having brake rotors. As the brake rotor, comprised of conducting surface regions and non-conducting surface regions rotates, a magnet, which is disposed in close proximity to the brake rotor's conducting and non-conducting surface regions, generates an electric current to provide electric energy to a energy supply device, typically a battery. | 02-12-2015 |
David Martin Robinett, Overland Park, KS US
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20150081548 | METHODS AND SYSTEMS FOR MAKING MOBILE PAYMENTS - Systems and methods for mobile payments are provided. A customer may interact with the system via a voice interface. A customer may verbally communicate with a merchant to determine details of a transaction. The customer need not provide sensitive financial information for the transaction nor have stored payment information previously with the merchant. Information pertaining to the transaction may be processed and payment confirmation may occur through communication with a payment gateway. | 03-19-2015 |
Doug Robinett, Overland Park, KS US
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20080203238 | CABLE DUCT PUNCH TOOL AND METHOD - Embodiments provide a method of running cables from an already-installed cable duct to devices. According to the method, a portion of a duct from which it is desirable for cable to be dropped is selected upon consideration of a first location of a first device to which a connection is desired. The method also includes punching a first aperture in the duct proximate the first portion, snaking a first cable from the duct through the first aperture, and connecting the first cable to the first device. | 08-28-2008 |
Joanne Robinett, Bridgewater, NJ US
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20110306566 | TOPICAL SKIN TREATMENT KITS - This invention relates to benzoyl peroxide products for skin treatment, and more particularly to a kit containing a benzoyl peroxide product and a topical moisturizing product. In one embodiment the kit contains BenzaClin® brand clindamycin-benzoyl peroxide gel and Viscontour® brand hyaluronic acid serum. | 12-15-2011 |
Joseph Warren Robinett, Chapel Hill, NC US
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20100091662 | Defect-tolerant demultiplexers based on threshold logic - Embodiments of the present invention include defect-tolerant demultiplexer crossbars that employ, or that can be modeled by demultiplexer crossbars that employ, threshold logic “TL” elements. The threshold-logic elements provide for tolerance for signal variation on internal signals lines of a defect-tolerant demultiplexer crossbar, and thus tolerance for defects which produce internal signal variation. | 04-15-2010 |
20100094580 | Method and system for device reconfiguration for defect amelioration - Embodiments of the present invention are directed to cost-effective defect amelioration in manufactured electronic devices that include nanoscale components. Certain embodiments of the present invention are directed to amelioration of defects in electronic devices that contain nanoscale demultiplexers. In certain embodiments of the present invention, the nanoscale-demultiplexer-containing devices include reconfigurable encoders. In one embodiment of the present invention, the table of codes within a reconfigurable encoder is permuted, and a device is configured in accordance with the permuted codes, in order to produce a permuted table of codes that, when input to an appropriately configured nanoscale demultiplexer, produces correct outputs despite defects in the nanoscale demultiplexer. | 04-15-2010 |
J. Warren Robinett, Pittsboro, NC US
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20100293518 | Nanoscale interconnection interface - One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2 | 11-18-2010 |
Mark Robinett, San Rafael, CA US
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20090147505 | Rechargeable portable Light with Multiple Charging Systems - A rechargeable portable light having a housing member with an opening for the emission of light, and several possible charging systems including a solar panel, an AC charger, an auto charger, and a hand crank generator charger. An electronic circuit is located within the housing member and includes at least one electrochemical capacitor for power storage. The electrochemical capacitor is charged by a charging system. A power inverter circuit, a mechanical switch method, or a DC-DC IC is used to increase voltage and regulate current. The circuit also includes at least one light emitting diode (LED) positioned near the opening in the housing member, and a switch interposed between the capacitor and the LED. The switch is closed when power is delivered from the capacitor to the LED. | 06-11-2009 |
Robert L. Robinett, San Diego, CA US
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20120202561 | CDMA TRANSCEIVER WITH CDMA DIVERSITY RECEIVER PATH SHARED WITH TIME DUPLEXED RECEIVER - A wireless device including at least a first and second antenna and at least one processor may process signals received from a first wireless system (TD-SCDMA, GSM, TDD-LTE) exclusively on the first antenna, and may process signals received from a second wireless system (FDD, CDMA, WCDMA, LTE, TDMA) on the first and second antennas using receive diversity. According to aspects, the device may process signals transmitted from the first wireless system exclusively on the second antenna. | 08-09-2012 |
Robert Lioyd Robinett, San Diego, CA US
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20150270813 | DYNAMICALLY ADJUSTABLE POWER AMPLIFIER LOAD TUNER - An apparatus includes a power amplifier and a power amplifier load tuner. The power amplifier load tuner includes multiple input ports. A first input port of the power amplifier load tuner is selectively coupled to a corresponding power amplifier. The power amplifier load tuner has an adjustable impedance. | 09-24-2015 |
Robert Lloyd Robinett, San Diego, CA US
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20140376428 | MULTI-FREQUENCY RANGE PROCESSING FOR RF FRONT END - Techniques for supporting multi-frequency range signal processing for a wireless device. In an aspect, a first antenna is provided to support first and third frequency ranges. A second antenna is separately provided to support a second frequency range, wherein the second is between the first and third frequency ranges. In other aspects, the second antenna can further support a fourth frequency range higher than the third frequency range. Other frequency range combinations, dual antenna aspects, and carrier aggregation features are further disclosed herein. | 12-25-2014 |
20150126136 | LOW-NOISE AMPLIFIER MATCHING - Exemplary embodiments are related to a low-noise amplifier (LNA) matching device. A device may include an antenna for receiving a wireless signal and at least one LNA. The device may further include an LNA matching device coupled between the antenna and the at least one LNA and configured to receive one or more control signals to provide an optimal LNA match setting for each band of a plurality of frequency bands. | 05-07-2015 |
Warren Robinett, Palo Alto, CA US
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20150357034 | INTERCONNECTION ARCHITECTURE FOR MULTILAYER CIRCUITS - A computer readable memory includes a circuit layer, a multilayer memory stacked over the circuit layer to form a memory box, the memory box comprising a bottom surface interfacing with the circuit layer and four side surfaces, and a first switching crossbar array disposed on a first side of the memory box. A plurality of vias connects the circuit layer to the first switching crossbar layer. The first switching crossbar array accepts signals from the plurality of vias and selectively connects a crossbar in the multilayer memory to the circuit layer. A method for addressing multilayer memory is also provided. | 12-10-2015 |
Warren Robinett, Chapel Hill, NC US
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20080237886 | Three-dimensional crossbar array systems and methods for writing information to and reading information stored in three-dimensional crossbar array junctions - Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array. | 10-02-2008 |
20100197117 | MIXED-SCALE ELECTRONIC INTERFACES - Certain embodiments of the present invention are directed to a method of programming nanowire-to-conductive element electrical connections. The method comprises: providing a substrate including a number of conductive elements overlaid with a first layer of nanowires, at least some of the conductive elements electrically coupled to more than one of the nanowires through individual switching junctions, each of the switching junctions configured in either a low-conductance state or a high-conductance state; and switching a portion of the switching junctions from the low-conductance state to the high-conductance state or the high-conductance state to the low-conductance state so that individual nanowires of the first layer of nanowires are electrically coupled to different conductive elements of the number of conductive elements using a different one of the switching junctions configured in the high-conductance state. Other embodiments of the present invention are directed to a nanowire structure including a mixed-scale interface. | 08-05-2010 |
20110057683 | DEFECT-AND-FAILURE-TOLERANT DEMULTIPLEXER USING SERIES REPLICATION AND ERROR-CONTROL ENCODING - One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective. | 03-10-2011 |
20120098566 | Interconnection Architectures for Multilayer Crossbar Circuits - An interconnection architecture for multilayer circuits includes metal-insulator transition channels interposed between address leads and each bar in the multilayer circuit. An extrinsic variable transducer selectively transitions the metal-insulator channels between insulating and conducting states to selectively connect and disconnect the bars and the address leads. A method for accessing a programmable crosspoint device within a multilayer crossbar circuit is also provided. | 04-26-2012 |
20140028347 | IMPLEMENTING LOGIC CIRCUITS WITH MEMRISTORS - Implementing logic with memristors may include circuitry with at least three memristors and a bias resistor in a logic cell. One of the at least three memristors is an output memristor within the logic cell and the other memristors of the at least three memristors are input memristors. Each of the at least three memristors and the bias resistor are electrically connected to voltage sources wherein each voltage applied to each of the at least three memristors and the bias resistor and resistance states of the at least three memristors determine a resistance state of the output memristor. | 01-30-2014 |
Warren J. Robinett, Chapel Hill, SC US
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20080258767 | Computational nodes and computational-node networks that include dynamical-nanodevice connections - Embodiments of the present invention are employ dynamical, nanoscale devices, including memristive connections between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks and neural networks. In many embodiments of the present invention, neuron-like computational devices are constructed from silicon-based microscale and/or submicroscale components, and interconnected with one another by dynamical interconnections comprising nanowires and memristive connections between nanowires. In many massively parallel, distributed, dynamical computing systems, including the human brain, there may be a far greater number of interconnections than neuron-like computational nodes. Use of dynamical nanoscale devices for these connections results in enormous design, space, energy, and computational efficiencies. | 10-23-2008 |