Patent application number | Description | Published |
20080274610 | METHODS OF FORMING A SEMICONDUCTOR DEVICE INCLUDING A DIFFUSION BARRIER FILM - Methods of forming a semiconductor device that includes a diffusion barrier film are provided. The diffusion barrier film includes a metal nitride formed by using a MOCVD process and partially treated with a plasma treatment. Thus, a specific resistance of the diffusion barrier film can be decreased, and the diffusion barrier film may have distinguished barrier characteristics. | 11-06-2008 |
20080318421 | METHODS OF FORMING FILMS OF A SEMICONDUCTOR DEVICE - There is provided a method of forming a film of a semiconductor device. The method includes a step of adsorbing a liquefied metal ion source on the substrate; rinsing the substrate to remove any liquefied metal ion source that is not adsorbed to the substrate; depositing a metal layer on the substrate by reducing the liquefied metal ion source that is adsorbed on the substrate with a liquefied reducing agent; and rinsing the substrate to remove the remaining liquefied reducing agent and any reaction residual. | 12-25-2008 |
20090011583 | Method of manufacturing a semiconductor device - A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten. | 01-08-2009 |
20090166868 | Semiconductor devices including metal interconnections and methods of fabricating the same - A semiconductor device includes a first interlayer dielectric including a trench on a semiconductor layer, a mask pattern on the first interlayer dielectric, a first conductive pattern in the trench, and a second interlayer dielectric on the mask pattern. The second interlayer dielectric includes an opening over the first conductive pattern. A second conductive pattern is in the opening and is electrically connected to the first conductive pattern. The first conductive pattern has an upper surface lower than an upper surface of the mask pattern. | 07-02-2009 |
20090176124 | Bonding pad structure and semiconductor device including the bonding pad structure - A bonding pad structure for a semiconductor device includes a first lower metal layer beneath a second upper metal layer in a bonding region of the device. The lower metal layer is formed such that the metal of the lower metal layer is absent from the bonding region. As a result, if damage occurs to the structure during procedures such as probing or bonding at the bonding region, the lower metal is not exposed to the environment. Oxidation of the lower metal layer by exposure to the environment is prevented, thus improving reliability of the device. | 07-09-2009 |
20090298282 | Methods of Forming Interlayer Dielectrics Having Air Gaps - Methods of forming an interlayer dielectric having an air gap are provided including forming a first insulating layer on a semiconductor substrate. The first insulating layer defines a trench. A metal wire is formed in the trench such that the metal wire is recessed beneath an upper surface of the first insulating layer. A metal layer is formed on the metal wire, wherein the metal layer includes a capping layer portion filling the recess, a upper portion formed on the capping layer portion, and an overhang portion formed on the portion of the first insulating layer adjacent to the trench protruding sideward from the upper portion. The first insulating layer is removed and a second insulating layer is formed on the semiconductor substrate to cover the metal layer, whereby an air gap is formed below the overhang portion of the metal layer. A portion of the second insulating layer is removed to expose the upper portion of the metal layer. The upper portion and the overhang portion of the metal layer are removed. A third insulating layer is formed on the semiconductor substrate from which the upper portion and the overhang portion have been removed to maintain the air gap. | 12-03-2009 |
20100151672 | METHODS OF FORMING METAL INTERCONNECTION STRUCTURES - Methods of forming a metal interconnection structure are provided. The methods include forming an insulating layer on a semiconductor substrate including a first metal interconnection. The insulating layer is patterned to form an opening that exposes the first metal interconnection. A first diffusion barrier layer is formed on the exposed first metal interconnection. After forming the first diffusion barrier layer, a second diffusion barrier layer is formed on the first diffusion barrier layer in the opening, the second diffusion barrier layer contacting a sidewall of the opening. A second metal interconnection is formed on the second diffusion barrier layer. | 06-17-2010 |
20100237504 | Methods of Fabricating Semiconductor Devices Having Conductive Wirings and Related Flash Memory Devices - A conductive wiring for a semiconductor device is provided including a semiconductor substrate and a plurality of lower conductive structures on the semiconductor substrate. An insulating layer is provided that electrically insulates the plurality of lower conductive structures from one another. A first insulation interlayer pattern is provided on the insulation layer. The first insulation interlayer pattern includes a contact plug that contacts the substrate through the insulation layer. An etch-stop layer is provided on the contact plug and the first insulation interlayer pattern. A second insulation interlayer pattern is provided on the etch-stop layer. The second insulation interlayer pattern includes a conductive line that is electrically connected to the contact plug. Related methods and flash memory devices are also provided. | 09-23-2010 |