Patent application number | Description | Published |
20080261368 | WORK FUNCTION ADJUSTMENT WITH THE IMPLANT OF LANTHANIDES - Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor. | 10-23-2008 |
20080265336 | METHOD OF FORMING A HIGH-K GATE DIELECTRIC LAYER - A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon oxide layer on a semiconductor substrate, nitridating the silicon oxide layer to form a nitrided silicon oxide layer and incorporating lanthanide atoms into the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer. | 10-30-2008 |
20090104742 | METHODS FOR FORMING GATE ELECTRODES FOR INTEGRATED CIRCUITS - A method of forming an integrated circuit can include the steps of providing a substrate having a semiconducting surface and forming a plurality of semiconducting multilayer features on the substrate surface, the features comprising a base layer and a compositionally different capping layer on the base layer. The method can also include forming spacers on sidewalls of the plurality of features, etching the capping layer, where the etching comprises selectively removing the capping layer, removing at least a portion of the base layer to form a plurality of trenches, and forming gate electrodes in the trenches. | 04-23-2009 |
20090127632 | Semiconductor Device Manufactured by Removing Sidewalls During Replacement Gate Integration Scheme - One aspect of the invention provides a semiconductor device that includes gate electrodes comprising a metal or metal alloy located over a semiconductor substrate, wherein the gate electrodes are free of spacer sidewalls. The device further includes source/drains having source/drain extensions associated therewith, located in the semiconductor substrate and adjacent each of the gate electrodes. A first pre-metal dielectric layer is located on the sidewalls of the gate electrodes and over the source/drains, and a second pre-metal dielectric layer is located on the first pre-metal dielectric layer. Contact plugs extend through the first and second pre-metal dielectric layers. | 05-21-2009 |
20110006375 | METHOD OF FORMING A HIGH-K GATE DIELECTRIC LAYER - A method for manufacturing a semiconductor device includes forming a gate electrode over a gate dielectric. The gate dielectric is formed by forming a lanthanide metal layer over a nitrided silicon oxide layer, and then performing an anneal to inter-diffuse atoms to form a lanthanide silicon oxynitride layer. A gate electrode layer may be deposited before or after the anneal. In an embodiment, the gate electrode layer includes a non-lanthanide metal layer, a barrier layer formed over the non-lanthanide metal layer, and a polysilicon layer formed over the barrier layer. Hafnium atoms may optionally be implanted into the nitrided silicon oxide layer. | 01-13-2011 |
20110131838 | DYNAMICALLY ADJUSTABLE ORTHOTIC DEVICE - An orthotic device comprises a flexible support structure comprising at least one surface for contacting a body part of a user, a plurality of pressure sensors configured for coupling to a microcontroller, and a plurality of displacement regions. Each region defines a portion of said flexible support structure, wherein each portion includes at least one sensor disposed on or below the at least one surface and at least one electrically deformable unit. Each unit comprises at least one electroactive material and is configured for coupling to the microcontroller and to a power source. The device is dynamically adjustable to change its shape and support properties, when an electrical voltage is applied to the electroactive material under the control of a microcontroller. | 06-09-2011 |
20110223757 | WORK FUNCTION ADJUSTMENT WITH THE IMPLANT OF LANTHANIDES - Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor. | 09-15-2011 |
20130224940 | WORK FUNCTION ADJUSTMENT WITH THE IMPLANT OF LANTHANIDES - Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor. | 08-29-2013 |
20130324887 | DYNAMICALLY ADJUSTABLE ORTHOTIC DEVICE - An orthotic device comprises a flexible support structure comprising at least one surface for contacting a body part of a user, a plurality of pressure sensors configured for coupling to a microcontroller, and a plurality of displacement regions. Each region defines a portion of said flexible support structure, wherein each portion includes at least one sensor disposed on or below the at least one surface and at least one electrically deformable unit. Each unit comprises at least one electroactive material and is configured for coupling to the microcontroller and to a power source. The device is dynamically adjustable to change its shape and support properties, when an electrical voltage is applied to the electroactive material under the control of a microcontroller. | 12-05-2013 |
20140315377 | WORK FUNCTION ADJUSTMENT WITH THE IMPLANT OF LANTHANIDES - Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor. | 10-23-2014 |
Patent application number | Description | Published |
20080274598 | Doped WGe to form dual metal gates - A method of fabricating a dual metal gate structures in a semiconductor device, the method comprising forming a gate dielectric layer above a semiconductor body, forming a work function adjusting layer on the dielectric gate layer in the PMOS region, depositing a tungsten germanium gate electrode layer above the work function adjusting material in the PMOS region, depositing a tungsten germanium gate electrode layer above the gate dielectric in the NMOS region annealing the semiconductor device, depositing a metal nitride barrier layer on the tungsten germanium layer, depositing a polysilicon layer over the metal nitride, patterning the polysilicon layer, the metal nitride layer, the tungsten germanium layer, work function adjusting layer and the gate dielectric layer to form a gate structure, and forming a source/drain on opposite sides of the gate structure. | 11-06-2008 |
20080283941 | FABRICATION OF TRANSISTORS WITH A FULLY SILICIDED GATE ELECTRODE AND CHANNEL STRAIN - An integrated circuit includes one or more transistors on or in a semiconductor substrate. At least one of the transistors includes a gate electrode and source and drain structures. The gate electrode has a fully silicided gate electrode layer with a ratio of Ni:Si ranging from about 2:1 to about 3:1. The source and drain structures are located in openings of the substrate and adjacent to the gate electrode. The source and drain structures are filled with SiGe to produce stress in the transistor channel region. | 11-20-2008 |
20090117726 | Integration Scheme for an NMOS Metal Gate - A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor. | 05-07-2009 |
20100173502 | LOW k1 HOLE PRINTING USING TWO INTERSECTING FEATURES - A method of forming one or more features during semiconductor device fabrication can comprise exposing a photosensitive layer to a first pattern at an exposure energy which is insufficient to fully expose the photosensitive layer, then exposing the photosensitive layer to a second pattern at an exposure energy which is insufficient to fully expose the photosensitive layer At an intersection of the first and second patterns, the energy does received during the first and second exposure is sufficient to fully expose the photosensitive layer. | 07-08-2010 |
20100178739 | INTEGRATION SCHEME FOR AN NMOS METAL GATE - A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor. | 07-15-2010 |