Mark R. Visokay
Mark R. Visokay, Richardson, TX US
Patent application number | Description | Published |
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20080274598 | Doped WGe to form dual metal gates - A method of fabricating a dual metal gate structures in a semiconductor device, the method comprising forming a gate dielectric layer above a semiconductor body, forming a work function adjusting layer on the dielectric gate layer in the PMOS region, depositing a tungsten germanium gate electrode layer above the work function adjusting material in the PMOS region, depositing a tungsten germanium gate electrode layer above the gate dielectric in the NMOS region annealing the semiconductor device, depositing a metal nitride barrier layer on the tungsten germanium layer, depositing a polysilicon layer over the metal nitride, patterning the polysilicon layer, the metal nitride layer, the tungsten germanium layer, work function adjusting layer and the gate dielectric layer to form a gate structure, and forming a source/drain on opposite sides of the gate structure. | 11-06-2008 |
20080283932 | Semiconductor Device Manufactured Using a Gate Silicidation Involving a Disposable Chemical/Mechanical Polishing Stop Layer - In one aspect, there is provided a method of manufacturing a semiconductor device that comprises placing a blocking layer, a CMP stop layer and a bulk oxide layer over an oxide cap layer that is located over gate structures and source/drains located adjacent thereto. The bulk oxide layer and the CMP stop layer are removed with a CMP process to expose the top of gate electrodes and are removed from over the source/drain areas with a wet etch. The CMP stop layer has a CMP removal rate that is less than a CMP removal rate of the bulk oxide layer and has a wet etch removal rate that is greater than a wet etch removal rate of the blocking layer. | 11-20-2008 |
Mark R. Visokay, Dallas, TX US
Patent application number | Description | Published |
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20120164820 | SEMICONDUCTOR DEVICE FABRICATED USING A METAL MICROSTRUCTURE CONTROL PROCESS - The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal. | 06-28-2012 |