Patent application number | Description | Published |
20080272797 | Intergrated Circuit Self-Test Architecture - An integrated circuit ( | 11-06-2008 |
20100308329 | LITHOGRAPHY ROBUSTNESS MONITOR - The present invention relates to a method and device for monitoring a lithographic process of an integrated circuit. In a first step a design for an integrated circuit is provided. The integrated circuit comprises at least an integrated circuit transistor pair having a gate of a first transistor connected to a gate of a second transistor. The gate of the second transistor is designed such that it has a predetermined overlap with respect to a source and a drain of the second transistor. A detection circuit is connected to the at least an integrated circuit transistor pair for detecting if in operation functionality of the second transistor of each of the at least an integrated circuit transistor pair is one of a transistor and a short circuit. The integrated circuit is then manufactured in dependence upon the desogn. After manufacturing, the detection circuit is used to determine the functionality of the second transistor of each of the at least an integrated circuit transistor pair. | 12-09-2010 |
20110128055 | DLL FOR PERIOD JITTER MEASUREMENT | 06-02-2011 |
20110140730 | DETECTION CIRCUITRY FOR DETECTING BONDING CONDITIONS ON BOND PADS - The present invention relates to a detection circuitry for detecting bonding conditions on segmented bond pads of a semiconductor device, the bonding conditions representing good or bad contacts on the bond pads. The detection circuitry comprises a segmented bond pad ( | 06-16-2011 |
20110156755 | FLEXIBLE CMOS LIBRARY ARCHITECTURE FOR LEAKAGE POWER AND VARIABILITY REDUCTION - Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes. | 06-30-2011 |