Bronner, US
Derek Bronner, Chittenango, NY US
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20090165142 | EXTENSIBLE SOFTWARE TOOL FOR INVESTIGATING PEER-TO-PEER USAGE ON A TARGET DEVICE - In general, the invention provides for analyzing a target computer for computer crimes such as illegal sharing of files or sharing of illegal files on peer-to-peer clients. The target computer may have software for a plurality of peer-to-peer clients. Only one extensible forensic device may be necessary to analyze the plurality of peer-to-peer clients for downloaded or shared files. For example, the invention may provide for a method comprising determining whether one or more peer-to-peer clients are or have been installed on a target device by identifying information associated with one or more peer-to-peer modules, wherein each module is associated with a different one of the one or more peer-to-peer clients. The method further includes, gathering usage information for the one or more peer-to-peer clients that had been determined to be installed on the target computer, analyzing the usage information, and automatically generating a report of the analyzed usage information. | 06-25-2009 |
20100299430 | AUTOMATED ACQUISITION OF VOLATILE FORENSIC EVIDENCE FROM NETWORK DEVICES - Examples disclosed herein are directed to techniques for automatically retrieving and processing forensic data from network devices connected to a communications network without requiring device-specific knowledge or training. A mobile forensic device includes and extensible forensic analysis tool that allows on-scene forensic investigators to quickly and automatically acquire data from network devices without device-specific knowledge. The extensible forensic analysis tool is designed for use on handheld mobile computers, enabling on-scene investigators to quickly and easily acquire forensic data from network devices in the field without losing volatile data or shutting down the network. | 11-25-2010 |
Derek P. Bronner, Chittenango, NY US
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20120209983 | CONFIGURABLE FORENSIC INVESTIGATIVE TOOL - This disclosure provides example techniques to invoke one or more forensic tools, with a forensic investigative tool. The forensic investigative tool provides a common framework that allows investigators to invoke their own trusted forensic tools or third-party generated forensic tools. The forensic investigative tool described herein seamlessly and transparently invokes the forensic tools in accordance with an investigative profile created by the investigator. | 08-16-2012 |
20120210427 | CONFIGURABLE INVESTIGATIVE TOOL - This disclosure provides example techniques to invoke one or more tools, with an investigative tool. The investigative tool provides a common framework that allows investigators to invoke their own trusted tools or third-party generated tools. The investigative tool described herein seamlessly and transparently invokes the tools in accordance with an investigative profile created by the investigator. | 08-16-2012 |
Ethan A. Bronner, Colorado Springs, CO US
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20150225982 | Deadbolt Indicator - An apparatus for a cylindrical deadbolt assembly indicates whether the deadbolt is locked or unlocked. The apparatus comprises a trim piece, such as an escutcheon or collar, configured to be mounted on the inside face of a door, a dial mounted on an inside surface of the trim piece, and a cam. The trim piece comprises one or more windows for displaying information from the dial. The dial is operative to travel between first and second positions to provide a first indication when the deadbolt is locked and a second indication when the deadbolt is unlocked. The cylinder tail piece turns the cam to move the dial between its first and second positions. | 08-13-2015 |
Gary Bronner, Los Altos, CA US
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20100025811 | INTEGRATED CIRCUIT WITH BUILT-IN HEATING CIRCUITRY TO REVERSE OPERATIONAL DEGENERATION - An integrated circuit device ( | 02-04-2010 |
20110275356 | Methods and Circuits for Detecting and Reporting High-Energy Particles Using Mobile Phones and Other Portable Computing Devices - Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or packaging modifications. The low cost supports a broad distribution of detectors. Data collected from constellations of detector-equipped mobile phones can be used to locate mislaid or stolen nuclear materials or other potentially dangerous radiation sources. Phone users can be alerted to radiation dangers in their vicinity, and aggregated phone-specific error data can serve as user-specific dosimeters. | 11-10-2011 |
Gary B. Bronner, Stormville, NY US
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20090101995 | PROCESS FOR FABRICATION OF FINFETs - A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate. | 04-23-2009 |
Gary B. Bronner, Los Altos, CA US
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20100230807 | Method and Apparatus to Repair Defects in Nonvolatile Semiconductor Memory Devices - A method of repairing a nonvolatile semiconductor memory device to eliminate defects includes monitoring a memory endurance indicator for a nonvolatile semiconductor memory device contained in a semiconductor package. It is determined whether that the memory endurance indicator exceeds a predefined limit. Finally, in response to determining that the memory endurance indicator exceeds the predefined limit, the device is annealed. | 09-16-2010 |
20100290286 | MULTI-PAGE PARALLEL PROGRAM FLASH MEMORY - A NAND flash memory device having a bit line and a plurality of storage cells coupled thereto. Programming circuitry is coupled to the plurality of storage cells concurrently to program two or more of the storage cells in different NAND strings associated with the same bit line. | 11-18-2010 |
20110004726 | PIECEWISE ERASURE OF FLASH MEMORY - Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-erase commands within the memory device may be insufficient to erase the information stored in the storage cell. Moreover, the first circuit includes an interface that receives the multiple piecewise-erase commands from the control logic and that transmits the multiple piecewise-erase commands to the memory device. | 01-06-2011 |
20110060875 | FRACTIONAL PROGRAM COMMANDS FOR MEMORY DEVICES - A memory system ( | 03-10-2011 |
20110286280 | Pulse Control For NonVolatile Memory - This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a “rest period” between pulses typically is chosen to be on the order of about a hundred nanoseconds or greater (e.g., one microsecond). Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of (50) nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); if desired, segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust. | 11-24-2011 |
20110299317 | INTEGRATED CIRCUIT HEATING TO EFFECT IN-SITU ANNEALING - In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device. | 12-08-2011 |
20120211722 | THREE-DIMENSIONAL MEMORY ARRAY STACKING STRUCTURE - A memory device includes a planar substrate, a plurality of horizontal conductive planes above the planar substrate, and a plurality of horizontal insulating layers interleaved with the plurality of horizontal conductive planes. An array of vertical conductive columns, perpendicular to the pluralities of conductive planes and insulating layers, passes through apertures in the pluralities of conductive planes and insulating layers. The memory device includes a plurality of programmable memory elements, each of which couples one of the horizontal conductive planes to a respective vertical conductive column. | 08-23-2012 |
20120230134 | DRAM SENSE AMPLIFIER THAT SUPPORTS LOW MEMORY-CELL CAPACITANCE - The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping. In another variation, the sense amplifier additionally includes a cross-coupled pair of latching NFETs. These latching NFETs are normally doped and are configured to latch the voltage on the bit line after the lightly doped NFETs finish sensing the voltage on the bit line. | 09-13-2012 |
20120236668 | MEMORY MODULE WITH DISCRETE HEATING ELEMENT - A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects. | 09-20-2012 |
20140247656 | Pulse Control For NonVolatile Memory - A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust. | 09-04-2014 |
20140254286 | THERMAL ANNEAL USING WORD-LINE HEATING ELEMENT - In response to detecting an event during operation of an integrated-circuit memory device containing charge-storing memory cells, an electric current is enabled to flow through a word line coupled to the charge-storing memory cells for a brief interval to heat the charge-storing memory cells to an annealing temperature range. | 09-11-2014 |
20150103605 | DRAM SENSE AMPLIFIER THAT SUPPORTS LOW MEMORY-CELL CAPACITANCE - The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping. In another variation, the sense amplifier additionally includes a cross-coupled pair of latching NFETs. These latching NFETs are normally doped and are configured to latch the voltage on the bit line after the lightly doped NFETs finish sensing the voltage on the bit line. | 04-16-2015 |
20160027498 | REDUCED REFRESH POWER - N out of every M number of refresh commands are ignored (filtered out) by a buffer chip on a memory module. N and M are programmable. The buffer receives refresh commands (e.g., auto-refresh commands) from the command-address channel, but does not issue a proportion of these commands to the DRAMs on the module. This reduces the power consumed by refresh operations. The buffer may replace some auto-refresh (REF) commands with activate (ACT) and precharge (PRE) commands directed to specific rows. These rows may have known ‘weak’ cells that require refreshing more often than a majority of the other rows on the module (or component). By ignoring some auto-refresh commands, and directing some others to specific rows that have ‘weak’ cells, the power consumed by refresh operations can be reduced. | 01-28-2016 |
20160027515 | Pulse Control For Non-Volatile Memory - A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust. | 01-28-2016 |
20160071608 | DYNAMIC MEMORY RANK CONFIGURATION - Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa. | 03-10-2016 |
Gary B. Bronner, Mountain View, CA US
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20130148437 | THERMAL ANNEAL USING WORD-LINE HEATING ELEMENT - In response to detecting an event during operation of an integrated-circuit memory device containing charge-storing memory cells, an electric current is enabled to flow through a word line coupled to the charge-storing memory cells for a brief interval to heat the charge-storing memory cells to an annealing temperature range. | 06-13-2013 |
Gary B. Bronner, Los Angeles, CA US
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20130250657 | System and Method for Writing Data to an RRAM Cell - A resistive RAM device includes a bit line, a word line, an RRAM cell coupled to the word line and to the bit line, a write driver and a disable circuit. The write driver is coupled to the bit line. The disable circuit stops a write operation performed by the write driver on a respective RRAM cell when a predefined condition on the bit line is achieved. The predefined condition depends on a mode of operation of the RRAM cell. | 09-26-2013 |
Gary Bela Bronner, Los Altos, CA US
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20140269006 | FAST READ SPEED MEMORY DEVICE - A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node between a first terminal of the first resistive memory element and a first terminal of the second resistive memory element, and a transistor comprising a gate electrically coupled with the common node. | 09-18-2014 |
20150162382 | 1D-2R MEMORY ARCHITECTURE - A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element, and a two-terminal switching element. The first resistive memory element is electrically coupled to the second resistive memory element and to the switching element at a common node. | 06-11-2015 |
Gary Bela Bronner, Stormville, NY US
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20080272398 | CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING - A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide. | 11-06-2008 |
Gary Bella Bronner, Los Altos, CA US
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20140112058 | RESISTANCE MEMORY CELL - A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low-resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell. | 04-24-2014 |
Greg Bronner, Sabina, OH US
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20090302046 | Collapsible Containers - Collapsible containers dimensioned to integrate into less-than-load operations are provided. The container may include a base, a pair of first and second opposing walls, each first and second opposing wall including a top edge, two side edges and a bottom edge. The container further includes a top panel removably attached to the top edge of the pairs of first and second opposing walls and a plurality of engaging devices positioned along the perimeter of the base and along the two side edges and bottom edge of the pairs of first and second opposing walls. The plurality of engaging devices are configured to removably connect the pair of first opposing walls to the pair of second opposing walls and to removably connect the pairs of first and second opposing walls to the base. | 12-10-2009 |
20100018966 | Collapsible Containers - Collapsible containers dimensioned to integrate into motor carrier operations are provided. The container may include a base, a pair of first and second opposing walls, each first and second opposing wall including a top edge, two side edges and a bottom edge. The container further includes a top panel removably attached to the top edge of the pairs of first and second opposing walls and a plurality of engaging devices positioned along the perimeter of the top panel and base and along the two side edges and top and bottom edges of the pairs of first and second opposing walls. The plurality of engaging devices are configured to removably connect the pair of first opposing walls to the pair of second opposing walls and to removably connect the pairs of first and second opposing walls to the top panel and base. | 01-28-2010 |
Hans R. Bronner, Irvington, NJ US
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20100229306 | Infant Head Cradle - A head-restraint system includes a rotatable base portion; a stationary platform positioned underneath the base portion, wherein the platform supports the base portion; a rotatable head cradle positioned within an open region of the base portion; a first pivoting mechanism that allows the head cradle to rotate with respect to the base portion; and a second pivoting mechanism that allows the base portion to rotate with respect to the platform. | 09-16-2010 |
Joseph Bronner, Warren, NJ US
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20100037552 | Side mounted drill bolt and threaded anchor system for veneer wall tie connection - In accordance with one aspect of the present invention, a load transfer system includes a back-up wall and at least one panel disposed adjacent the back-up wall. A veneer wall is spaced from the back-up wall. A drill bolt having a generally cylindrical shaft extending between first and second ends is provided. A portion of the shaft adjacent the first end is secured to the back-up wall and a portion of the shaft adjacent the second end extends through a penetration hole in the at least one panel. A clip is disposed on the second end of the drill bolt within the space between the back-up wall and the veneer wall. A wire tie extends between the clip and the veneer wall. | 02-18-2010 |
20110061333 | Twist On Wire Tie Wall Connection System And Method - A wire tire includes an embedment end having first and second ends. First and second leg portions extend from the first and second ends, respectively. First and second moment arms extend from the first and second leg portions, respectively. First and second hook arms extend from the first and second moments arms, respectively. | 03-17-2011 |
20110094176 | Winged Anchor and Spiked Spacer for Veneer Wall Tie Connection System and Method - A spacer for an anchor includes a base having first and second sides. The first side is adapted for engagement with an anchor. At least two spikes extend from the second end of the base. An opening is provided within the base. | 04-28-2011 |
20130340371 | WINGED ANCHOR AND SPIKED SPACER FOR VENEER WALL TIE CONNECTION SYSTEM AND METHOD - An anchor includes a barrel having a bore extending therethrough. First and second wings extend laterally from the barrel. Further, first and second grooves are provided within the first and second wings, respectively. | 12-26-2013 |
Marianne Bronner, La Canada, CA US
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20130273596 | NEURAL CREST ENHANCERS AND METHODS FOR USE - DNA enhancer sequences are provided for use in constructs to identify early stage embryonic cells. The enhancer sequences can be used in parallel with short-hairpin RNA in a vector construct for endogenously regulated gene knockdowns. The disclosed enhancer sequences can be used to isolate a selected population of early stage embryonic cells. | 10-17-2013 |
Mary Patricia Bronner, Moreland Hills, OH US
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20080318225 | COMPOSITIONS AND METHODS FOR DETECTING CANCER - The present invention provides methods and compositions involving detecting the presence of and/or assessing the risk of cancer in a subject. These methods include methods of detecting and diagnosing cancer in an individual; methods of identifying individuals at risk of developing a cancer; and methods of staging a cancer. The methods generally involve detecting a palladin gene nucleotide sequence alteration that has been found to be associated with cancer and/or detecting a level of a palladin mRNA and/or protein in a biological sample. The present invention further provides nucleic acid probes, nucleic acid primers, and antibodies, as well as kits comprising one or more of the same, for use in a subject method. | 12-25-2008 |
20110104694 | COMPOSITIONS AND METHODS FOR DETECTING CANCER - The present invention provides methods and compositions involving detecting the presence of and/or assessing the risk of cancer in a subject. These methods include methods of detecting and diagnosing cancer in an individual; methods of identifying individuals at risk of developing a cancer; and methods of staging a cancer. The methods generally involve detecting a palladin gene nucleotide sequence alteration that has been found to be associated with cancer and/or detecting a level of a palladin mRNA and/or protein in a biological sample. The present invention further provides nucleic acid probes, nucleic acid primers, and antibodies, as well as kits comprising one or more of the same, for use in a subject method. | 05-05-2011 |
Nathaniel H. Bronner, Atlanta, GA US
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20130174322 | ADVERTISING HEADPIECE - A headpiece that provides shade, which also includes one or more areas carrying readable information that is intended to be communicated to persons viewing the headpiece while it is being worn by a wearer. | 07-11-2013 |
Raymond A. Bronner, Agawam, MA US
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20110220207 | SOLENOID GAS METER MOUNTING BRACKET VALVE - A solenoid gas meter mounting bracket valve may be used to shut down the flow of fuel, such as natural gas, to a building. The solenoid valve may be incorporated with the gas meter bracket, as a single unit. This configuration may be safer and more secure than a separate valve, which may be damaged when installed at the exterior of the building. The solenoid gas meter mounting bracket valve may not only secure the gas meter, for example, but may also be the solenoid valve for controlling the fuel flow. The solenoid valve may be closed from signals received from various detectors located, for example, in the structure and in the ground, do detect carbon monoxide, carbon dioxide, radon, air quality, and the like. | 09-15-2011 |
Samantha L. Bronner, Seattle, WA US
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20160089851 | NONWOVEN DECORATIVE LAMINATES AND METHODS OF MAKING THE SAME - A decorative laminate for application to a structural component is provided. The decorative laminate has a substrate layer of a nonwoven fabric material with or without a flame retardant material. The decorative laminate further has an embossable layer disposed upon the substrate layer. The embossable layer includes an embossing resin material and the flame retardant material. The decorative laminate further has a protective layer disposed upon the embossable layer. The protective layer includes a polyvinyl fluoride-based material and has a decorative material printed on a first side of the protective layer facing the embossable layer. An adhesive layer is applied to the substrate layer of the decorative laminate. The decorative laminate is applied to the structural component with the substrate layer facing a bonding surface of the structural component and with an adhesive layer applied between the decorative laminate and the bonding surface of the structural component. | 03-31-2016 |
Sarah Bronner, Pasadena, CA US
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20140316149 | ALDEHYDE-SELECTIVE WACKER-TYPE OXIDATION OF UNBIASED ALKENES - This disclosure is directed to methods of preparing organic aldehydes, each method comprising contacting a terminal olefin with an oxidizing mixture comprising: | 10-23-2014 |
Shawn E. Bronner, Detroit, MI US
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20120036957 | MANUAL TRANSMISSION REVERSE LOCKOUT SYSTEM - A shifter assembly may include a shift lever, an actuation member, a coupling, a first cable and a second cable. The shift lever may be connected to a housing for pivotable motion relative to the housing. The actuation member may be connected to the shift lever and may be movable relative thereto between a first position and a second position. The coupling may be connected to the shift lever and may include first and second members slidably engaging each other. The first cable may have a first end connected to the second member and a second end that can be coupled to a reverse lockout mechanism. The second cable may be connected to the actuation member and the second member of the coupling such that movement of the actuation member relative to the shift lever causes corresponding motion of the second member relative to the shift lever. | 02-16-2012 |
20120172167 | AXLE ASSEMBLY - An axle assembly for a vehicle including a first gear, and a second gear joined to a shaft extending along a longitudinal axis. The second gear engages the first gear. A bearing is disposed over the shaft distal the second gear. A housing is disposed about at least a portion of the shaft. The housing includes a first lubricant pathway spaced apart from a second lubricant pathway, wherein the first lubricant pathway routes lubricant towards the bearing and the second lubricant pathway routes lubricant away from the bearing. The first and second lubricant pathways are not in a position coplanar with a plane of rotation of the first gear. | 07-05-2012 |