Patent application number | Description | Published |
20110221812 | System and Method For Improving Throughput For Duplex Printing Operations In An Indirect Printing System - A method for performing duplex printing enables increased throughput in an indirect printing system. The method includes measuring a coverage parameter for image data to be printed, and transforming operation of the printer from a first printing process timing sequence to a second printing process timing sequence in response to the coverage parameter exceeding a predetermined threshold. | 09-15-2011 |
20140055796 | METHODS AND SYSTEMS FOR CREATING STRUCTURAL DOCUMENTS WITH SECURITY FEATURES - A method of creating a structural document may include determining a shape of a structural document, determining a plurality of dimensions of the structural document, receiving information associated with one or more content items, identifying one or more security features associated with the structural document and causing a graphical representation of the structural document to be displayed at a user computing device. A shape of the graphical representation may correspond to the determined shape, a plurality of dimensions of the graphical representation may be representative of the determined plurality of dimensions, and the graphical representation may include at least a portion of the received content items and at least a portion of the identified security features. The method may include receiving an indication that a user is finished creating the structural document, generating a print document including an encoded data mark, and providing the print document to print-related devices. | 02-27-2014 |
20140055820 | METHODS AND SYSTEMS FOR CREATING STRUCTURAL DOCUMENTS - A method of creating a structural document may include determining, by a host computing device in a cloud system, a shape of a structural document, determining, by the host computing device, a plurality of dimensions of the structural document, receiving information associated with one or more content items, and causing a graphical representation of the structural document to be displayed at a user computing device. A shape of the graphical representation may correspond to the determined shape, a plurality of dimensions of the graphical representation may correspond to the determined plurality of dimensions, and the graphical representation may include at least a portion of the received content items. The method may include receiving an indication that a user is finished creating the structural document, generating a print document including an encoded data mark, and providing the print document to one or more print-related devices. | 02-27-2014 |
20140055821 | METHODS AND SYSTEMS FOR CREATING STRUCTURAL DOCUMENT PACKAGES FOR PRODUCTS - A method of creating a structural document may include receiving, by a host computing device in a cloud system, content information pertaining to one or more contents of a structural document that may be configured to encase the contents, determining a shape of a structural document based at least in part on the received content information, determining a plurality of dimensions of the structural document based at least in part on the received content information, receiving content item information associated with one or more content items, and causing a graphical representation of the structural document to be displayed at the user computing device. The method may include receiving an indication that a user is finished creating the structural document, generating a print document including an encoded data mark, and providing the print document to one or more print-related devices. | 02-27-2014 |
20140055822 | METHODS AND SYSTEMS FOR CREATING STRUCTURAL DOCUMENTS HAVING CONTACT INFORMATION FOR UTILIZING PRODUCT INFORMATION - A method may include determining a shape of a structural document, determining a plurality of dimensions of the structural document, receiving information associated with one or more content items, receiving contact information to include on the structural document, receiving an indication of a location on the structural document where the contact information is to be displayed, and causing a graphical representation of the structural document to be displayed at a computing device. A shape and dimensions of the graphical representation may correspond to the determined shape and dimensions, the contact information may be displayed on the graphical representation at the location, and the graphical representation may include at least a portion of the received content items. The method may include receiving an indication that a user is finished creating the structural document, generating a print document including an encoded data mark, and providing the print document to print-related devices. | 02-27-2014 |
Patent application number | Description | Published |
20100233879 | METHOD FOR UNIFORM NANOSCALE FILM DEPOSITION - Ultrathin layers are deposited by chemical vapor deposition (CVD) with reduced discontinuities, such as pinholes. Embodiments include depositing a material on a wafer by CVD while rotating the CVD showerhead and/or the wafer mounting surface, e.g., at least 45°. Embodiments include rotating the showerhead and/or mounting surface continuously through the deposition of the material. Embodiments also include forming subfilms of the material and rotating the showerhead and/or mounting surface after the deposition of each subfilm. The rotation of the showerhead and/or mounting surface averages out the non-uniformities introduced by the CVD showerhead, thereby eliminating discontinuities and improving within wafer and wafer-to-wafer uniformity. | 09-16-2010 |
20110275214 | DUAL DAMASCENE-LIKE SUBTRACTIVE METAL ETCH SCHEME - Metal interconnects are formed with larger grain size and improved uniformity. Embodiments include patterning metal layers into metal interconnects and vias prior to depositing a dielectric layer. An embodiment includes forming metal layers on a substrate, patterning the metal layers to form metal interconnect lines and vias, and forming a dielectric layer on the substrate, metal interconnect lines, and vias, thereby filling gaps between the metal interconnect lines and between the vias. The metal layers may be annealed prior to patterning. A liner may be formed on the sidewalls of the metal interconnect lines and vias prior to forming the dielectric layer. The dielectric layer may be formed of a porous material with a dielectric constant less than 2.4. | 11-10-2011 |
20130072019 | METHODS FOR FORMING SEMICONDUCTOR DEVICES - Embodiments of methods for forming a semiconductor device are provided. The method includes forming a metal layer overlying a dielectric material. A thickness of the metal layer is reduced including oxidizing an exposed outer portion of the metal layer to form a metal oxide portion overlying a remaining portion of the metal layer and removing the metal oxide portion. | 03-21-2013 |
20130175680 | DIELECTRIC MATERIAL WITH HIGH MECHANICAL STRENGTH - A multiphase ultra low k dielectric process is described incorporating a first precursor comprising at least one of carbosilane and alkoxycarbosilane molecules containing the group Si—(CH | 07-11-2013 |
20130221524 | INTEGRATED CIRCUITS WITH IMPROVED INTERCONNECT RELIABILITY USING AN INSULATING MONOLAYER AND METHODS FOR FABRICATING SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes an interlayer dielectric material having a top surface and overlying semiconductor devices formed on a semiconductor substrate. The integrated circuit includes a metal interconnect formed in the interlayer dielectric material. The metal interconnect includes an upper surface to which an insulating monolayer is bonded. The integrated circuit further includes a dielectric cap that overlies the top surface of the interlayer dielectric material and encapsulates the insulating monolayer. | 08-29-2013 |
20130241062 | INTEGRATED CIRCUITS AND METHODS FOR PROCESSING INTEGRATED CIRCUITS WITH EMBEDDED FEATURES - Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate. | 09-19-2013 |
20130299994 | INTEGRATED CIRCUITS AND PROCESSES FOR FORMING INTEGRATED CIRCUITS HAVING AN EMBEDDED ELECTRICAL INTERCONNECT WITHIN A SUBSTRATE - Integrated circuits and processes for forming integrated circuits are provided. An exemplary process for forming an integrated circuit includes providing a substrate including an oxide layer and a protecting layer disposed over the oxide layer. A recess is etched through the protecting layer and at least partially into the oxide layer. A barrier material is deposited in the recess to form a barrier layer over the oxide layer and protecting layer in the recess. Electrically-conductive material is deposited over the barrier layer in the recess to form the embedded electrical interconnect. The embedded electrical interconnect and barrier layer are recessed to an interconnect recess depth and a barrier recess depth, respectively, within the substrate. At least a portion of the protecting layer remains over the oxide layer after recessing the barrier layer and is removed after recessing the barrier layer. | 11-14-2013 |
20130309868 | METHODS FOR FORMING AN INTEGRATED CIRCUIT WITH STRAIGHTENED RECESS PROFILE - Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened. | 11-21-2013 |
20140145332 | METHODS OF FORMING GRAPHENE LINERS AND/OR CAP LAYERS ON COPPER-BASED CONDUCTIVE STRUCTURES - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a graphene liner layer in at least the trench/via, forming a copper-based seed layer on the graphene liner layer, depositing a bulk copper-based material on the copper-based seed layer so as to overfill the trench/via, and performing at least one chemical mechanical polishing process to remove at least excess amounts of the bulk copper-based material and the copper-based seed layer positioned outside of the trench/via to thereby define a copper-based conductive structure with a graphene liner layer positioned between the copper-based conductive structure and the layer of insulating material. | 05-29-2014 |
20140374915 | INTEGRATION OF OPTICAL COMPONENTS IN INTEGRATED CIRCUITS - Methodologies enabling integration of optical components in ICs and a resulting device are disclosed. Embodiments include: providing a first substrate layer of an IC separated from a second substrate level by an insulator layer; providing a transistor on the second substrate layer; and providing an optical component on the first substrate layer, the optical component being connected to the transistor. | 12-25-2014 |
Patent application number | Description | Published |
20120244698 | METHODS FOR FORMING COPPER DIFFUSION BARRIERS FOR SEMICONDUCTOR INTERCONNECT STRUCTURES - Embodiments of methods for forming Cu diffusion barriers for semiconductor interconnect structures are provided. The method includes oxidizing an exposed outer portion of a copper line that is disposed along a dielectric substrate to form a copper oxide layer. An oxide reducing metal is deposited onto the copper oxide layer. The copper oxide layer is reduced with at least a portion of the oxide reducing metal that oxidizes to form a metal oxide barrier layer. A dielectric cap is deposited over the metal oxide barrier layer. | 09-27-2012 |
20130043589 | Methods of Forming a Non-Planar Cap Layer Above Conductive Lines on a Semiconductor Device - Disclosed herein are various methods of forming methods of forming a non-planar cap layer above a conductive line on a semiconductor device, and to devices incorporating such a non-planar cap layer. In one illustrative example, the method includes forming a conductive structure in a layer of insulating material, recessing an upper surface of the conductive structure relative to an upper surface of the layer of insulating material such that the recessed upper surface of the conductive structure and the upper surface of the layer of insulating material are positioned in different planes and, after recessing the upper surface of the conductive structure, forming a first cap layer on the conductive structure and the layer of insulating material. In another example, the device includes a conductive structure positioned in a layer of insulating material and a first cap layer formed on the layer of insulating material and the conductive structure, wherein a first interface between the first cap layer and the layer of insulating material is located in a first plane and a second interface between the first cap layer and the conductive structure is located in a second plane that is different from the first plane. | 02-21-2013 |
20140213037 | METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING CONFINED EPITAXIAL GROWTH REGIONS - Methods are provided for fabricating integrated circuits. In accordance with one embodiment, the method includes forming a portion of a semiconductor substrate at least partially bounded by a confinement isolation material. A liner dielectric is formed overlying the confinement isolation material and is treated to passivate a surface thereof An epitaxial layer of semiconductor material is then grown overlying the portion of semiconductor substrate. | 07-31-2014 |
20140217588 | METHODS OF FORMING COPPER-BASED NITRIDE LINER/PASSIVATION LAYERS FOR CONDUCTIVE COPPER STRUCTURES AND THE RESULTING DEVICE - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material. | 08-07-2014 |
20140220775 | METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING EMBEDDED ELECTRICAL INTERCONNECTS - A method for fabricating integrated circuits includes providing a substrate including a protecting layer over an oxide layer and etching a recess through the protecting layer and into the oxide layer. A barrier material is deposited over the substrate to form a barrier layer including a first region in the recess and a second region outside the recess. A conductive material is deposited over the barrier layer and forms an embedded electrical interconnect in the recess and an overburden region outside the recess. The overburden region of the conductive material is removed and a portion of the embedded electrical interconnect is recessed. Thereafter, the barrier layer is etched to remove the second region of the barrier layer and to recess a portion of the first region of the barrier layer. After etching the barrier layer, the protecting layer is removed from the oxide layer. | 08-07-2014 |
20140252617 | BARRIER LAYER CONFORMALITY IN COPPER INTERCONNECTS - A process of modulating the thickness of a barrier layer deposited on the sidewalls and floor of a recessed feature in a semiconductor substrate is disclosed. The process includes altering the surface of the conductive feature on which the barrier layer is deposited by annealing in a reducing atmosphere and optionally additionally, silylating the dielectric surface that forms the sidewalls of the recessed feature. | 09-11-2014 |
20140256064 | METHODS OF REPAIRING DAMAGED INSULATING MATERIALS BY INTRODUCING CARBON INTO THE LAYER OF INSULATING MATERIAL - One illustrative method disclosed herein includes providing a layer of a carbon-containing insulating material having a nominal carbon concentration, performing at least one process operation on the carbon-containing insulating material that results in the formation of a reduced-carbon-concentration region in the layer of carbon-containing insulating material, wherein the reduced-carbon-concentration region has a carbon concentration that is less than the nominal carbon concentration, performing a carbon-introduction process operation to introduce carbon atoms into at least the reduced-carbon-concentration region and thereby define a carbon-enhanced region having a carbon concentration that is greater than the carbon concentration of the reduced-carbon-concentration region and, after introducing the carbon atoms, performing a heating process on at least the carbon-enhanced region. | 09-11-2014 |
20140302671 | Selective etching of copper and copper-barrier materials by an aqueous base solution with fluoride addition - Wet-etch solutions for conductive metals (e.g., copper) and metal nitrides (e.g., tantalum nitride) can be tuned to differentially etch the conductive metals and metal nitrides while having very little effect on nearby oxides (e.g., silicon dioxide hard mask materials), and etching refractory metals (e.g. tantalum) at an intermediate rate. The solutions are aqueous base solutions (e.g., ammonia-peroxide mixture or TMAH-peroxide mixture) with just enough hydrofluoric acid (HF) added to make the solution's pH about 8-10. Applications include metallization of sub-micron logic structures. | 10-09-2014 |
20140353802 | METHODS FOR INTEGRATION OF PORE STUFFING MATERIAL - A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided. | 12-04-2014 |
20140353805 | METHODS OF SEMICONDUCTOR CONTAMINANT REMOVAL USING SUPERCRITICAL FLUID - A process is provided for the removal of contaminants from a semiconductor device, for example, removing contaminants from pores of an ultra-low k film. In one aspect, a method includes: providing a dielectric layer with contaminant-containing pores and exposing the dielectric layer to a supercritical fluid. The supercritical fluid can dissolve and remove the contaminants. In another aspect, an intermediate semiconductor device structure is provided that contains a dielectric layer with contaminant-containing pores and a supercritical fluid within the pores. In another aspect, a semiconductor device structure with a dielectric layer containing uncontaminated pores is provided. | 12-04-2014 |
20140353835 | METHODS OF SELF-FORMING BARRIER INTEGRATION WITH PORE STUFFED ULK MATERIAL - A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench. | 12-04-2014 |
20140361435 | METHODS OF FORMING COPPER-BASED NITRIDE LINER/PASSIVATION LAYERS FOR CONDUCTIVE COPPER STRUCTURES AND THE RESULTING DEVICE - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material. | 12-11-2014 |
20150126028 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SURFACE MODIFICATION TO SELECTIVELY INHIBIT ETCHING - Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first exposed surface including an elemental metal material and a second exposed surface including a barrier material. The elemental metal material has a first etch rate when exposed to a wet etchant and the barrier material has a second etch rate when exposed to the wet etchant. Further, the method includes modifying the first exposed surface to form a modified first exposed surface so as to reduce the first etch rate when exposed to the wet etchant and applying the wet etchant simultaneously to the modified first exposed surface and to the second exposed surface. | 05-07-2015 |
20150130065 | method to etch cu/Ta/TaN selectively using dilute aqueous Hf/h2so4 solution - Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and H | 05-14-2015 |
20150255340 | METHOD TO ETCH CU/TA/TAN SELECTIVELY USING DILUTE AQUEOUS HF/HCL SOLUTION - Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm. | 09-10-2015 |
20150340274 | METHODS FOR PRODUCING INTEGRATED CIRCUITS WITH AN INSULTATING LAYER - Methods for producing integrated circuits are provided. A method for producing an integrated circuit includes forming an insulating layer overlying a substrate, where the insulating layer is formed within a trench. The insulating layer is infused with water, and the insulating layer is annealed while being irradiated. The insulating layer is annealed at a dry anneal temperature of about 800 degrees centigrade or less. | 11-26-2015 |
20150348833 | Method to etch cu/Ta/TaN selectively using dilute aqueous Hf/hCl solution - Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm. | 12-03-2015 |
20150371898 | INTEGRATED CIRCUITS INCLUDING MODIFIED LINERS AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes contacting a liner that is disposed adjacent to a porous interlayer dielectric (ILD) layer of dielectric material with a selectively reactive gas at reaction conditions. A portion of the liner is reacted with the selectively reactive gas to form a converted expanded portion that is disposed between a remaining portion of the liner and the porous ILD layer. | 12-24-2015 |
Patent application number | Description | Published |
20090075472 | METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS - Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure. | 03-19-2009 |
20090179306 | ADVANCED LOW k CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES - A carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. In some embodiments, the dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen. The carbon-rich silicon carbide-like dielectric film can be used as a dielectric cap layer in an interconnect structure. The inventive dielectric film is highly robust to UV curing and remains compressively stressed after UV curing. Moreover, the inventive dielectric film has good oxidation resistance and prevents metal diffusion into an interconnect dielectric layer. The present invention also provides an interconnect structure including the inventive dielectric film as a dielectric cap. A method of fabricating the inventive dielectric film is also provided. | 07-16-2009 |
20100122711 | WET CLEAN METHOD FOR SEMICONDUCTOR DEVICE FABRICATION PROCESSES - A wet clean method for semiconductor device fabrication begins by providing a semiconductor device structure having a substrate and features protruding from the substrate. The features are formed from a dielectric material, such as an ultra-low-k material. The method continues by cleaning the semiconductor device structure with an aqueous solution and, following the cleaning step, displacing the aqueous solution with a first solvent. Thereafter, the features are exposed to a second solvent that contains a hydrophobic treatment agent that reacts with sidewalls of the features to form a hydrophobic layer on the sidewalls. | 05-20-2010 |
20110021028 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES INCLUDING AZEOTROPIC DRYING PROCESSES - Embodiments of a method for fabricating a semiconductor device are provided. In one embodiment, the method includes the steps of providing a partially-completed semiconductor device including a first feature formed in a porous material, wet cleaning the partially-completed semiconductor device with an aqueous cleaning solvent, exposing the partially-completed semiconductor device to a liquid chemical that forms an azeotropic mixture with water, and inducing evaporation of the azeotropic mixture to remove residual water from within the porous material absorbed during the wet cleaning step. | 01-27-2011 |
20120193767 | ADVANCED LOW k CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES - A carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen. The carbon-rich silicon carbide-like dielectric film can be used as a dielectric cap layer in an interconnect structure. | 08-02-2012 |
20120202354 | ADVANCED LOW k CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES - A method of forming a carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen. | 08-09-2012 |
20120329269 | METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS - Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure. | 12-27-2012 |
20140179119 | ADVANCED LOW k CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES - A method of forming a carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen. | 06-26-2014 |
Patent application number | Description | Published |
20080271606 | CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - A carbon nanotube filter, a use for a carbon nanotube filter and a method of forming a carbon nanotube filter. The method including (a) providing a carbon source and a carbon nanotube catalyst; (b) growing carbon nanotubes by reacting the carbon source with the nanotube catalyst; (c) forming chemically active carbon nanotubes by forming a chemically active layer on the carbon nanotubes or forming chemically reactive groups on sidewalls of the carbon nanotubes; and (d) placing the chemically active nanotubes in a filter housing. | 11-06-2008 |
20080282893 | CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - A carbon nanotube filter. The filter including a filter housing; and chemically active carbon nanotubes within the filter housing, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and media containing the chemically active carbon nanotubes. | 11-20-2008 |
20080284992 | EXPOSURES SYSTEM INCLUDING CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - An exposure system for exposing a photoresist layer on a top surface of a wafer to light. The exposure system including: an environment chamber containing a light source, one or more focusing lenses, a mask holder, a slit and a wafer stage, the light source, all aligned to an optical axis, the wafer stage moveable in two different orthogonal directions orthogonal to the optical axis, the mask holder and the slit moveable in one of the two orthogonal directions; a filter in a sidewall of the environment chamber, the filter including: a filter housing containing chemically active carbon nanotubes, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and means for forcing air or inert gas first through the filter then into the environment chamber and then out of the environment chamber. | 11-20-2008 |
20080286466 | CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - A carbon nanotube filter, a use for a carbon nanotube filter and a method of forming a carbon nanotube filter. The method including (a) providing a carbon source and a carbon nanotube catalyst; (b) growing carbon nanotubes by reacting the carbon source with the nanotube catalyst; (c) forming chemically active carbon nanotubes by forming a chemically active layer on the carbon nanotubes or forming chemically reactive groups on sidewalls of the carbon nanotubes; and (d) placing the chemically active nanotubes in a filter housing. | 11-20-2008 |
20100119422 | CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - A carbon nanotube filter. The filter including a filter housing; and chemically active carbon nanotubes within the filter housing, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and media containing the chemically active carbon nanotubes. | 05-13-2010 |
Patent application number | Description | Published |
20100118528 | LED CYCLORAMA LIGHT - A cyclorama light includes a generally enclosed housing forming an interior compartment having a normally horizontal housing axis and an open front defining a window generally arranged within a plane parallel to said axis. A reflector substantially covers the window and has an operative portion that has a substantially uniform cross-section along the housing axis. An LED light emitter array extends along a line substantially parallel to the housing axis, the reflector having a surface configuration and the LED array being arranged in relation to the reflector surface to provide a higher flux density directed toward a far end of a wall or surface to be illuminated and provide a lower flux density directed toward a direction of the near end of the surface to be illuminated, generating a transition flux density between the far and near ends of the surface to be illuminated. The LED array and/or the reflector have optical features for eliminating shadows in the projected light over the entire illuminated surface. | 05-13-2010 |
20110181200 | POWER AND DATA TRACK LIGHTING SYSTEM - A combined power and data track lighting system includes an elongated track, having a number of longitudinal guide ways, for attachment to a support surface, as well as a number of current carrying conductors arranged within at least some of the guide ways. The first of these conductors are power conductors and the second conductors are data conductors, the conductors being electrically isolated from each other. The lighting system further contains a first adapter for connection to source of electrical power for the power conductors, and a second adapter for connection to a source of control data. There is at least one LED luminaire present in the system, and this luminaire contains a number of LEDs, each of which, when energized, generates a single color out of a discrete plurality of colors. A data converter converts data along the data lines to control the currents in the individual groups of color LEDs, so that they create a desired composite color. Further, at least electrically, the LED luminaire is electrically connected to the power conductors and data conductors located in the lighting track. Likewise, at least one each of a Quartz luminaire, Metal-Halide luminaire, Digital Light Processor (DLP) automated computer luminaire, Liquid Crystal Display (LCD) automated computer luminaire, and DMX controlled device can be used in the present system including support trusses. The main control data will be Remote Device Management RDM supplied by an external controller applied to the data conductors of the combined power and data track lighting system. | 07-28-2011 |
20120250315 | LED CYCLORAMA LIGHT - A cyclorama includes a generally enclosed housing having a normally horizontal housing axis and an open front. A reflector proximate the open front has an operative portion that has a substantially uniform cross-section along the housing axis. The reflector has a surface configuration and an LED array is arranged in relation to the reflector surface to provide a higher flux density directed toward a far end of a wall or surface to be illuminated and provide a lower flux density directed toward a direction of the near end of the surface to be illuminated, generating a transition flux density between the far and near ends of the surface to be illuminated. The LED array and/or the reflector have optical features for eliminating shadows in the projected light over the entire illuminated surface. | 10-04-2012 |
Patent application number | Description | Published |
20130049206 | Bond Pad Configurations for Controlling Semiconductor Chip Package Interactions - Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes at least one integrated circuit device and a bond pad that is electrically connected to the at least one integrated circuit device. Furthermore, the bond pad has an irregular overall configuration when viewed from above that corresponds to a first area portion that is defined by a first substantially regular geometric shape when viewed from above and a second area portion adjacent to the first area portion. Additionally, the second area portion is located at a greater distance from a centerline of the semiconductor chip than any part of the first area portion when viewed from above, and the bond pad is electrically connected to the at least one integrated circuit device. | 02-28-2013 |
20130062775 | Strain-Compensating Fill Patterns for Controlling Semiconductor Chip Package Interactions - Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes, among other things, a bond pad and a metallization layer below the bond pad, wherein the metallization layer is made up of a bond pad area below the bond pad and a field area surrounding the bond pad area. Additionally, the semiconductor device also includes a plurality of device features in the metallization layer, wherein the plurality of device features has a first feature density in the bond pad area and a second feature density in the field area that is less than the first feature density. | 03-14-2013 |
20130334532 | STRESS GAUGE COMPRISED OF A PIEZOELECTRIC MATERIAL FOR USE WITH INTEGRATED CIRCUIT PRODUCTS - In one example, a stress gauge for an integrated circuit product is disclosed that includes a layer of insulating material, a body positioned at least partially in the layer of insulating material, wherein the body is comprised of a material having a piezoelectric constant of at least about 0.1 pm/V, and a plurality of spaced apart conductive contacts, each of which is conductively coupled to the body. | 12-19-2013 |
20140021613 | MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE - A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer. | 01-23-2014 |
20140021615 | MULTI-LAYER BARRIER LAYER STACKS FOR INTERCONNECT STRUCTURES - The present disclosure is generally directed to multi-layer barrier layer stacks for interconnect structures that may be used to reduce mechanical stress levels between the interconnect structure and a dielectric material layer in which the interconnect structure is formed. One illustrative method disclosed herein includes forming a recess in a dielectric layer of a substrate and forming an adhesion barrier layer including an alloy of tantalum and at least one transition metal other than tantalum to line the recess, wherein forming the adhesion barrier layer includes creating a first stress level across a first interface between the adhesion barrier layer and the dielectric layer. The method also includes forming a stress-reducing barrier layer including tantalum over the adhesion barrier layer, wherein the stress-reducing barrier layer reduces the first stress level to a second stress level less than the first stress level, and filling the recess with a fill layer. | 01-23-2014 |
20140024212 | MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE - A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer. | 01-23-2014 |
20140026675 | DETECTING ANOMALOUS STIFF PILLAR BUMPS FORMED ABOVE A METALLIZATION SYSTEM - Generally, the subject matter disclosed herein relates to testing pillar bumps formed on a semiconductor chip so as to detect the presence of anomalous stiff pillar bumps. One illustrative method disclosed herein includes positioning a test probe adjacent to a side of a pillar bump formed above a metallization system of a semiconductor chip, and performing a lateral force test on the pillar bump by contacting the side of the pillar bump with the test probe while moving the test probe at a substantially constant speed that is less than approximately 1 μm/sec. | 01-30-2014 |
20140026676 | DETECTING ANOMALOUS WEAK BEOL SITES IN A METALLIZATION SYSTEM - Generally, the subject matter herein relates to detecting the presence of weak BEOL sites in a metallization system. One disclosed method includes performing a lateral force test on a pillar bump formed above a metallization system of a semiconductor chip, which includes contacting the pillar bump with a test probe while moving the test probe at a substantially constant speed that is less than approximately 1 μm/sec along a path that is oriented at a substantially non-zero angle relative to a plane of the metallization system. Furthermore, the test probe is moving substantially away from the metallization system so that a force imposed on the pillar bump by the test probe has an upward component that induces a tensile load on the metallization system. The disclosed method also includes determining a behavioral interaction between the pillar bump and the metallization system during the lateral force test. | 01-30-2014 |
20140027902 | REPAIRING ANOMALOUS STIFF PILLAR BUMPS - Generally, the subject matter disclosed herein relates to repairing anomalous stiff pillar bumps that may be detected above a metallization system of a semiconductor chip or wafer. One illustrative method disclosed herein includes, among other things, forming a pillar bump above a metallization system of a semiconductor chip, and forming a plurality of notches in the pillar bump, wherein the plurality of notches are adapted to adjust a flexibility of the pillar bump when the pillar bump is exposed to a lateral force. | 01-30-2014 |
20140027910 | METHOD FOR REDUCING WETTABILITY OF INTERCONNECT MATERIAL AT CORNER INTERFACE AND DEVICE INCORPORATING SAME - A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate, forming a first transition metal layer in the recess on corner portions of the recess, and forming a second transition metal layer in the recess over the first transition metal layer to line the recess. The method further includes filling the recess with a fill layer and annealing the substrate so that the first transition metal layer and the second transition metal layer form an alloy portion proximate the corner portions during the annealing, the alloy portion having a reduced wettability for a material of the fill layer than the second transition metal. Additionally, the method includes polishing the substrate to remove portions of the fill layer extending above the recess. | 01-30-2014 |
20140077368 | REPAIRING ANOMALOUS STIFF PILLAR BUMPS - A system for repairing pillar bumps includes a pillar bump repair device that is adapted to form a plurality of strain-relieving notches in a pillar bump that is positioned above a metallization system of a semiconductor chip. The system further includes a pillar bump support device that is adapted to substantially support the pillar bump while the pillar bump repair device is forming each of the plurality of strain-relieving notches. | 03-20-2014 |
20140145330 | BOND PAD CONFIGURATIONS FOR CONTROLLING SEMICONDUCTOR CHIP PACKAGE INTERACTIONS - A semiconductor chip includes at least one integrated circuit device and a bond pad that is electrically connected to the at least one integrated circuit device. The bond pad has an irregular configuration when viewed from above that corresponds to a first area portion that is defined by a first substantially regular geometric shape when viewed from above and a second area portion adjacent to the first area portion. The second area portion is located at a greater distance from a centerline of the semiconductor chip than any part of the first area portion when viewed from above, and two sides of the first area portion are substantially aligned with and substantially flush with two respective sides of the second area portion. | 05-29-2014 |
20140210088 | METHOD FOR REDUCING WETTABILITY OF INTERCONNECT MATERIAL AT CORNER INTERFACE AND DEVICE INCORPORATING SAME - A semiconductor device includes a recess defined in a dielectric layer, the recess having an upper sidewall portion extending to an upper corner of the recess and a lower sidewall portion below the upper sidewall portion. An interconnect structure is positioned in the recess. The interconnect structure includes a continuous liner layer having upper and lower layer portions positioned laterally adjacent to the upper and lower sidewall portions, respectively. The upper layer portion includes an alloy of a first transition metal and a second transition metal and the lower layer portion includes the second transition metal but not the first transition metal. The interconnect structure also includes a fill material substantially filling the recess, wherein the second transition metal has a higher wettability for the fill material than the alloy. | 07-31-2014 |
20140217591 | MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE - A semiconductor device includes a dielectric layer positioned above a substrate of the semiconductor device and a recess defined in the dielectric layer. An adhesion barrier layer is positioned on and in direct contact with at least the sidewalls of the recess, a barrier layer interface being defined where the adhesion barrier layer directly contacts the dielectric layer. A stress-reducing barrier layer is positioned adjacent to the adhesion barrier layer, wherein the stress-reducing barrier layer is adapted to reduce a stress level across the barrier layer interface from a first stress level to a second stress level that is less than the first stress level. At least one layer of a conductive fill material is positioned over the stress-reducing barrier layer, the at least one layer of the conductive fill material substantially filling the recess. | 08-07-2014 |
20140246775 | METHODS OF FORMING NON-CONTINUOUS CONDUCTIVE LAYERS FOR CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a non-continuous layer comprised of a plurality of spaced-apart conductive structures on the layer of insulating material in the trench/via, wherein portions of the layer of insulating material not covered by the plurality of spaced-apart conductive structures remain exposed, forming at least one barrier layer on the non-continuous layer, wherein the barrier layer contacts the spaced-apart conductive structures and the exposed portions of the layer of insulating material, forming at least one liner layer above the barrier layer, and forming a conductive structure in the trench/via above the liner layer. | 09-04-2014 |
20140264876 | MULTI-LAYER BARRIER LAYER STACKS FOR INTERCONNECT STRUCTURES - A semiconductor device includes a recess defined in a dielectric layer and an interconnect structure defined in the recess. The interconnect structure includes a first barrier layer lining the recess, the first barrier layer including an alloy of tantalum and a first transition metal other than tantalum, wherein a first interface between the first barrier layer and the dielectric layer has a first stress level. A second barrier layer is positioned on the first barrier layer, the second barrier layer including at least one of tantalum and tantalum nitride, wherein a second interface between the second barrier layer and the first barrier layer has a second stress level that is less than the first stress level. The interconnect structure further includes a fill material substantially filling the recess. | 09-18-2014 |
20140291847 | METHODS OF FORMING A BARRIER SYSTEM CONTAINING AN ALLOY OF METALS INTRODUCED INTO THE BARRIER SYSTEM, AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH A BARRIER SYSTEM - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier system comprised of at least one barrier material and at least two metallic elements, and performing a heating process to form a metal alloy comprised of the at least two metallic elements in the barrier system. Also disclosed is a device that comprises a trench/via in a layer of insulating material, a barrier system positioned in the trench/via, wherein the barrier system comprises at least one barrier material and a metal alloy comprised of at least two metallic elements that are comprised of materials other than the at least one barrier material, and a conductive structure positioned in the trench/via above the barrier system. | 10-02-2014 |