Antonio Maria
Antonio Maria Borneo, Matera IT
Patent application number | Description | Published |
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20080270769 | PROCESS FOR RUNNING PROGRAMS ON PROCESSORS AND CORRESPONDING PROCESSOR SYSTEM - Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of instructions. The instructions are compiled as instruction words of given length executable on a first processor. At least some of the instruction words of given length are converted into modified-instruction words executable on a second processor. The operation of modifying comprises in turn at least one operation chosen in the group consisting of: splitting the instruction words into modified-instruction words; and entering no-operation instructions in the modified-instruction words. | 10-30-2008 |
20090160866 | METHOD AND SYSTEM FOR VIDEO DECODING BY MEANS OF A GRAPHIC PIPELINE, COMPUTER PROGRAM PRODUCT THEREFOR - A system for decoding a stream of compressed digital video images comprises a graphics accelerator for reading the stream of compressed digital video images, creating, starting from said stream of compressed digital video images, three-dimensional scenes to be rendered, and converting the three-dimensional scenes to be rendered into decoded video images. The graphics accelerator is preferentially configured as pipeline selectively switchable between operation in a graphics context and operation for decoding the stream of video images. The graphics accelerator is controllable during operation for decoding the stream of compressed digital video images via a set of application programming interfaces comprising, in addition to new APIs, also standard APIs for operation of the graphics accelerator in a graphics context. | 06-25-2009 |
Antonio Maria Gabello, Bergamo IT
Patent application number | Description | Published |
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20110080680 | METHOD FOR MANAGING A FAULT EVENT IN A NETWORK FOR DISTRIBUTING ELECTRICAL ENERGY, AND A CORRESPONDING ELECTRONIC PROTECTION UNIT - A method is provided for managing a fault event in a network for distributing low-voltage or high-voltage electrical energy, which comprises at least one voltage source and a load. The method includes performing at least one step of a first procedure for detecting the existence of fault conditions in the load and performing at least one step of a second procedure for determining, on the basis of the evolution in time of the derivative of the instantaneous current in the load, the state of execution of an interruption manoeuvre started by at least one protection device adapted to interrupt locally the passage of current in the load. An electronic protection unit is also provided that is able to execute the aforesaid method. | 04-07-2011 |
Antonio Maria Scalia, Catania IT
Patent application number | Description | Published |
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20120195093 | MEMORY SUPPORT PROVIDED WITH MEMORY ELEMENTS OF FERROELECTRIC MATERIAL AND IMPROVED NON-DESTRUCTIVE READING METHOD THEREOF - A method is for non-destructive reading of an information datum stored in a memory that includes a first wordline, a first bitline and a second bitline, and a first ferroelectric transistor, which is connected between the bitlines and has a control terminal coupled to the first wordline. The method includes applying to the first wordline a first reading electrical quantity, generating a first difference of potential between the first and second bitlines, generating a first output electrical quantity, and applying to the first wordline a second reading electrical quantity. The method further includes generating a second difference of potential between the first and second bitlines, generating a second output electrical quantity, and comparing the first and second output electrical quantities with one another. On the basis of a result of said comparison, the method includes determining the logic value of the information data. | 08-02-2012 |
20120195094 | MEMORY SUPPORT PROVIDED WITH ELEMENTS OF FERROELECTRIC MATERIAL AND PROGRAMMING METHOD THEREOF - Logic data is written in a memory having a first word line and a first bit line, with the memory including a first memory cell having a first ferroelectric transistor. The first ferroelectric transistor includes a layer of ferroelectric material and has a first conduction terminal coupled to the first bit line, and a control terminal coupled to the first word line. The logic data is written based on biasing the control terminal of the first ferroelectric transistor at a first biasing value, biasing the first conduction terminal of the first ferroelectric transistor at a second biasing value different from the first biasing value, and generating a stable variation of the state of polarization of the layer of ferroelectric material of the first ferroelectric transistor to write the logic data in the first memory cell. | 08-02-2012 |
20120195095 | MEMORY SUPPORT PROVIDED WITH MEMORY ELEMENTS OF FERROELECTRIC MATERIAL AND NON-DESTRUCTIVE READING METHOD THEREOF - A method for non-destructive reading of logic data stored in a memory includes applying to a first wordline a reading voltage so as not to cause a variation of the stable state of polarization of a layer of ferroelectric material, and generating a difference of potential between first and second bitlines. An output current is generated comparing the output current with a plurality of comparison values, and determining the logic value of the logic data to be read on the basis of the comparison. | 08-02-2012 |
20130225944 | FLEXIBLE SENSOR ASSEMBLY - A sensor assembly includes: an electrically insulating and flexible body ( | 08-29-2013 |