Van Acht, Waalre
Victor Van Acht, Waalre NL
Patent application number | Description | Published |
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20120230100 | PROGRAMMABLE PHASE-CHANGE MEMORY AND METHOD THEREFOR - A non-volatile memory is disclosed. A contiguous layer of phase change material is provided. Proximate the contiguous layer of phase change material is provided a first pair of contacts for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a first region. Also adjacent the contiguous layer is provided a second pair of contacts disposed for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a second region thereof, the second region different from the first region. | 09-13-2012 |
Victor Martinus Van Acht, Waalre NL
Patent application number | Description | Published |
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20090122590 | CONTROL OF A MEMORY MATRIX WITH RESISTANCE HYSTERESIS ELEMENTS - A control circuit ( | 05-14-2009 |
20090129190 | DRIVING A MEMORY MATRIX OF RESISTANCE HYSTERESIS ELEMENTS - A memory matrix ( | 05-21-2009 |
Victor M.g. Van Acht, Waalre NL
Patent application number | Description | Published |
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20080270681 | Non-Volatile Memory with Block Erasable Locations - A main memory ( | 10-30-2008 |
20080276036 | Memory with Block-Erasable Location - A non-volatile main memory ( | 11-06-2008 |
20080316070 | Encoding of Data Words Using Three or More Level Levels - A data processing circuit comprises an encoder circuit for encoding a data word, wherein each digit may have any one of three or more digit values. The data word is encoded so that digit counts in the data word satisfy predetermined criteria (the digit counts are counts of the numbers of the digits in the encoded data word that assume respective digit values). The encoder defines at least two digit maps, each digit map defining assignments of each of the available digit values to a respective different output digit value. The encoder selects at least two groups of digits within the input data word. Each group is associated with a respective one of the digit maps, the groups being selected so that when each digit map has been applied selectively to the digits from its associated group, digit counts of the number of times respective digit values occur in the data word will satisfy predetermined criteria. A data signal is generated that represents the input data word by information that identifies the selected groups and an output data word obtained by mapping the digits of each group in the input data word according to the digit map for that group. | 12-25-2008 |
20090070637 | ELECTRONIC CIRCUIT WITH A MEMORY MATRIX THAT STORES PAGES INCLUDING EXTRA DATA - An apparatus comprises a memory with a matrix ( | 03-12-2009 |
20090072212 | ANTI-FUSE MEMORY DEVICE - A One Time Programmable (OTP) memory cell ( | 03-19-2009 |
20100299494 | MEMORY WITH BLOCK-ERASABLE LOCATIONS AND A LINKED CHAIN OF POINTERS TO LOCATE BLOCKS WITH POINTER INFORMATION - A memory apparatus has a main memory ( | 11-25-2010 |
Victor M. G. Van Acht, Waalre NL
Patent application number | Description | Published |
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20090150748 | Data Storage and Replay Apparatus - A data storage and replay device uses measurements of the evolution of performance of the storage medium (typically a flash memory circuit) to predict an error rate of retrieval from a region of the storage medium. The prediction is used as a basis for dynamically selecting an ECC for encoding the data prior to storage of the data. The ECC is selected from a plurality of available ECC's so that a fastest encodable ECC is selected that is predicted to produce no more than a predetermined post-decoding error rate given said information. In this way the speed of transmission of data to the device can be maximized while keeping the error rate below an acceptable level in the predicted future after decoding. On decoding the data, which is typically audio or video data, is decoded and replayed at a predetermined speed. In another embodiment, the data stored using a plurality of ECC's together and an ECC is selected dynamically for decoding, so that an output data rate can be maximized or power consumption on replay can be minimized. | 06-11-2009 |
20100103751 | CIRCUIT WITH A MEMORY ARRAY AND A REFERENCE LEVEL GENERATOR CIRCUIT - A circuit comprises an array of memory cells ( | 04-29-2010 |
20100232245 | ELECTRONIC CIRCUIT THAT COMPRISES A MEMORY MATRIX AND METHOD OF READING FOR BITLINE NOISE COMPENSATION - Data is read from a memory matrix ( | 09-16-2010 |