Patent application number | Description | Published |
20080267286 | Image Encoding Device and Method - An image encoding device includes a prediction processing unit which performs prediction processing on m components among N components which constitute a quantized block; a first Coded Block Pattern (CBP) judging unit which judges whether or not (N−m) components include a non-zero component in a first operation mode, and whether or not (N−n) components include a non-zero component in a second operation mode; a second CBP judging unit which judges whether or not the m components on which the prediction processing has been performed include a non-zero component in the first operation mode, and whether or not n components include a non-zero component in the second operation mode; and a CBP generating unit which generates a CBP code indicating whether or not all the components of the block are 0 components based on the judgments made by the first and second judging units. | 10-30-2008 |
20080270658 | PROCESSOR SYSTEM, BUS CONTROLLING METHOD, AND SEMICONDUCTOR DEVICE - Provided is a simply structured multiprocessor system which equally distributes access performance for accessing a shared memory among plural master units accessing the shared memory. The multiprocessor system includes plural master units PU | 10-30-2008 |
20090037696 | PROCESSOR - A processor ( | 02-05-2009 |
20090037779 | EXTERNAL DEVICE ACCESS APPARATUS - In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit. | 02-05-2009 |
20090063734 | BUS CONTROLLER - A bus controller capable of shortening the time required before a flush is completed so as not to degrade the performance of a processor. A bus controller includes: a FIFO for temporarily holding, on a first-in first-out basis, data to be stored from a processor into a memory; a flush pointer for holding a pointer which indicates end data held by the FIFO at a time when a trigger signal is received; a memory control unit for writing a portion of the data held by the FIFO into the memory according to the trigger signal so as to partially flush the FIFO, the portion ranging from start data through end data indicated by the flush pointer; and a wait circuit for generating a wait signal for a specific access instruction, which is executed by the processor, until the memory control unit completes the partial flush. | 03-05-2009 |
20100180095 | BUFFER CONTROL DEVICE AND BUFFER MEMORY DEVICE - The buffer control device of this invention includes: a pointer holding unit which holds a virtual pointer different from a read pointer and a write pointer; an access control unit that controls an access to a ring buffer; a judging unit that judges whether or not one of the read pointer and the write pointer has reached an address substantially identical to an address indicated by the virtual pointer; and disabling unit that disables a normal access using the one of the read pointer and the write pointer, when the judging unit judges that the one of the read pointer and the write pointer has reached the address substantially identical to the address indicated by the virtual pointer, the normal access being controlled by the access control unit, wherein the access control unit further controls a reaccess to the ring buffer. | 07-15-2010 |
20100289674 | VARIABLE-LENGTH CODE DECODING APPARATUS AND METHOD - A variable-length code decoding apparatus that decodes a bitstream includes: a storage unit that stores a variable-length code table; a bitstream cutout unit that outputs a bit string of a fixed length; a reference unit that outputs decoded data and a code length with reference to the storage unit; a determination unit that determines whether a bit string of the fixed length is accumulated; a determination unit that determines whether a bit string of a length that is shorter than the fixed length is accumulated; and a selection unit that selects one of the determination results from the determination units. The bitstream cutout unit sets a starting bit based on the selected determination result, and the selection unit switches the selection of the determination results from the determination units. | 11-18-2010 |
20100318707 | EXTERNAL DEVICE ACCESS APPARATUS, CONTROL METHOD THEREOF, AND SYSTEM LSI - An external device access apparatus according to the present invention includes: an address control unit that accepts a prefetch request and a prefetch data readout request from a master and performs a prefetch operation and a prefetch data readout operation; a readout data storage unit that stores data read out through the prefetch operation; a storage operation status holding unit that holds a prefetch operation status indicating whether or not the prefetch operation has been completed; and an acceptance signal generation unit that outputs, to the master, an acceptance signal indicating that the prefetch data readout request has been accepted from the master. First information indicating a status of the prefetch operation is outputted to the master based on the prefetch operation status. | 12-16-2010 |
20120272044 | PROCESSOR FOR EXECUTING HIGHLY EFFICIENT VLIW - A 32-bit instruction | 10-25-2012 |
20140196045 | PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION - A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot. | 07-10-2014 |