Patent application number | Description | Published |
20080238538 | RECEIVING DEVICE AND RELATED METHOD FOR CALIBRATING DC OFFSET - A receiving device includes a mixer, an AC coupling circuit, a post-stage circuit, and a DC offset calibration circuit. The mixer is utilized for mixing an input signal with a local oscillating (LO) signal from an oscillator to generate a converted signal. The AC coupling circuit is coupled to the mixer and utilized for reducing at least one portion of DC offset of the converted signal to generate a filtered signal. The post-stage circuit is coupled to the AC coupling circuit and utilized for processing the filtered signal to generate an output signal. The DC offset calibration circuit is coupled to the post-stage circuit and utilized for providing at least a compensation current for the post-stage circuit to reduce DC offset of the output signal. | 10-02-2008 |
20100060348 | BANDWIDTH-ADJUSTABLE FILTER - A bandwidth-adjustable filter includes an operational amplifier, a first resistor, a first capacitor and a first resistor ladder circuit. The operational amplifier has a negative input terminal and a positive input terminal The first resistor is coupled to one of the input terminals of the operational amplifier. The first capacitor is coupled to the first resistor. The first resistor ladder circuit is coupled in parallel to the first resistor for changing the resistance of the first resistor so as to adjust the bandwidth of the filter. | 03-11-2010 |
20110089982 | Fast Lock-In All-Digital Phase-Locked Loop with Extended Tracking Range - An apparatus and a method for achieving lock-in of a phase-locked loop (PLL) are disclosed. The PLL receives a reference clock and generates an output clock according to the reference clock. The method comprises: adjusting an oscillation frequency of a controlled oscillator of the PLL close to a desired frequency by counting the number of rising edges of a first clock in a number of a second clock cycles; aligning a rising edge of a third clock and a rising edge of a fourth clock by temporarily changing the oscillation frequency of the digitally controlled oscillator; and locking the phases of the third and fourth clocks by a phase detector of the PLL, wherein the first and the third clocks correspond to the output clock and the second and fourth clocks correspond to the reference clock. | 04-21-2011 |
20120235763 | EQUALIZER AND EQUALIZING METHOD - An equalizer and a related equalizing method for equalizing signal reflection caused by a stub at a transmitting end are provided. The equalizer includes a summing device and a delay device. The summing device is utilized for adding a feedback delay signal to the input signal to generate the equalized signal. The delay device is coupled to the summing device, and utilized for delaying the equalized signal to generate the feedback delay signal. Wherein the delay device has a variable delay time and the variable delay time is a non-integer multiple of a bit time of the input signal. | 09-20-2012 |
20140062550 | PHASE LOCKED LOOP - A phase locked loop comprises a loop filter and a charge pump circuit. The loop filter comprises a parallel capacitor, a serial resistor and a serial capacitor. A first terminal of the serial resistor is electrically connected to a first terminal of the parallel capacitor. A first terminal of the serial capacitor is electrically connected to the second terminal of the serial resistor, and a second terminal of the serial capacitor is electrically connected to a second terminal of the parallel capacitor. The charge pump circuit comprises a first charge pump and a second charge pump. The first charge pump is electrically connected to the first terminal of the serial resistor, and the second charge pump is electrically connected to the second terminal of the serial resistor. The phase lock loop can reduce output jitter and therefore increases the performance of the phase lock loop. | 03-06-2014 |
Patent application number | Description | Published |
20080297271 | MULTI-PHASE LAYOUT STRUCTURE AND METHOD - The present invention provides a multi-phase layout structure and method. The layout structure comprises: a first layout layer; a second layout layer substantially parallel to the first layout layer; a plurality of traces, each transmitting a signal, and the plurality of signals having a phase difference between each other; wherein a horizontal coupling capacitance is provided between two neighboring traces configured on the same layer of the first layout layer and the second layout layer, a vertical coupling capacitance is provided between two neighboring traces configured on different layers of the first layout layer and the second layout layer, and the plurality of traces have substantially the same total coupling capacitance wherein the total coupling capacitance is defined by the horizontal coupling capacitance and the vertical coupling capacitance. | 12-04-2008 |
20080303595 | AMPLIFYING CIRCUIT - An amplifier includes: a class AB input stage, receiving an input signal, for generating an inner signal according to the input signal; class AB output stage, includes: a biasing circuit, for providing a first voltage and a second voltage according to the inner signal; and an output stage, for generating an output signal according to the first voltage and the second voltage; wherein a voltage difference between the first voltage and the second voltage generated by the biasing circuit is corresponding to the input signal. | 12-11-2008 |
20090066393 | SWITCH CIRCUIT - A switch circuit includes a pair of metal oxide semiconductor (MOS) switches and an adjusting unit. Each of the MOS switches has an input terminal and an output terminal. The MOS switches receive a pair of differential input voltages at the input terminals thereof, and output a pair of differential output voltages at the output terminals thereof when the MOS switches conduct. The adjusting unit changes a difference between common mode levels of the input terminals and the output terminals of the MOS switches so as to adjust linearity of differential mode resistances of the MOS switches. | 03-12-2009 |
20110037525 | CRYSTAL OSCILLATOR - This invention discloses a crystal oscillator, in which by appropriately designing the gain of an amplifier to achieve high trans-conductance and low power consumption. This crystal oscillator includes a first pad, coupled to a first node of a crystal, for receiving a crystal oscillating signal outputted from the crystal; an amplifier, coupled to the first pad, for amplifying the crystal oscillating signal to generate an amplifying signal; an inverter, coupled to the amplifier, for inverting the amplifying signal; and a second pad, coupled to a second node of the crystal, for outputting an oscillating signal to the crystal. | 02-17-2011 |
20110051799 | EQUALIZATION APPARATUS - This invention provides an equalization apparatus for equalizing an input signal on a cable. The equalization apparatus comprises a cable equalizer for equalizing a cable attenuation effect of the input signal to output a first equalization signal; and a stub equalizer for equalizing a stub effect of the first equalization signal to output an outputting equalization signal. | 03-03-2011 |
Patent application number | Description | Published |
20080268805 | High Linearity Passive Mixer and Method Thereof - A high linearity mixer circuit includes a commutation network comprising four switches to provide an electrical coupling between a first pair of circuit nodes and a second pair of circuit nodes, whereas the coupling has two states and is controlled by a pair of complementary logical signals. The mixer circuit further comprises a first pair of current-sourcing devices coupled to the first pair of circuit nodes and a second pair of current-sourcing devices coupled to the second pair of circuit nodes. The mixer circuit further includes a pair of capacitors to provide AC coupling, either between the first pair of circuit nodes and a first external circuit, or between the second pair of circuit nodes and a second external circuit. | 10-30-2008 |
20090134858 | VOLTAGE REGULATING APPARATUS AND METHOD AND VOLTAGE REGULATOR THEREOF - A voltage regulating apparatus and method and voltage regulator thereof are presented. The apparatus includes a first regulator and a second regulator. The first regulator is used for receiving an input voltage and outputting a first voltage according to the input voltage. When the input voltage reaches a steady voltage value, the second regulator is turned on so as to receive the first voltage provided by the first regulator and output a second voltage according to the first voltage or the input voltage. | 05-28-2009 |
20090206920 | SOFT-START DEVICE - A soft-start device including a current source, a first transistor, and a second transistor is described. The first transistor is coupled to the current source, and an amount of current conducted by the first transistor is determined according to a voltage. The second transistor is also coupled to the current source, and an amount of current conducted by the second transistor is determined according to a fixed bias. An initial voltage value of the voltage is smaller than a voltage value of the fixed bias. However, after a soft start, the voltage value of the first voltage is increased gradually to be larger than the voltage value of the fixed bias, such that the soft start may be implemented smoothly. | 08-20-2009 |
20110012657 | DIGITALLY CONTROLLED OSCILLATOR - A digitally controlled LC-tank oscillator is constructed by connecting different tuning circuits to a LC tank. The tuning circuit includes a single bank of tuning cells, a dual bank of tuning cells, or a fractional tuning circuit. Each of said tuning cells in the tuning circuit includes a tuning circuit element and a memory cell. | 01-20-2011 |
20110254631 | REFERENCE ASSISTED CONTROL SYSTEM AND METHOD THEREOF - A reference assisted control system and method thereof are disclosed. The method comprises: receiving a first input signal and a second control signal; generating a first intermediate signal in accordance with a difference between the first input signal and the first output signal; filtering the second control signal to generate a second intermediate signal; performing a weighted sum of the first intermediate signal and the second intermediate signal to generate the control signal; and outputting the first output signal in accordance with the control signal. | 10-20-2011 |
20110254633 | METHOD AND APPARATUS FOR ALLEVIATING CHARGE LEAKAGE OF VCO FOR PHASE LOCK LOOP - Methods and apparatuses for alleviating charge leakage of VCO for phase lock loop are disclosed. The method comprises: receiving an input signal; generating an error signal representing a timing difference between the input signal and an output signal; filtering the error signal into a control signal; buffering the control signal into a buffered control signal; and generating the output signal in accordance with the buffered control signal. Buffering the control signal comprising using a high input resistance and low output resistance buffer circuit. | 10-20-2011 |
20130169465 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND CONVERSION METHOD THEREOF - A successive approximation analog to digital converter and a conversion method thereof are provided. The successive approximation analog to digital converter includes a sample circuit, a conversion circuit, and a filtering control circuit. The sample circuit is configured to sample an analog voltage from an analog signal. The conversion circuit is configured to convert the analog voltage into a digital voltage. The filtering control circuit is configured to transmit a filtering control signal to the sample circuit according to the digital voltage. The sample circuit further samples a next analog voltage from the analog signal and adjusts the next analog voltage into an adjusted analog voltage according to the filtering control signal. The conversion circuit further converts the adjusted analog voltage into a next digital voltage, wherein the next digital voltage is a filtered digital voltage. | 07-04-2013 |