Patent application number | Description | Published |
20080228999 | Dual use for data valid signal in non-volatile memory - In some types of non-volatile memory devices, the same signal from a memory device may be used for two purposes: During a read operation, the signal may be used by a memory controller to latch the data that is being received from the memory device. During a block erase operation and/or a block write operation, the signal may be used to notify the memory controller that the operation has been completed by the memory device. | 09-18-2008 |
20110016268 | PHASE CHANGE MEMORY IN A DUAL INLINE MEMORY MODULE - Subject matter disclosed herein relates to management of a memory device. | 01-20-2011 |
20120047334 | FLEXIBLE SELECTION COMMAND FOR NON-VOLATILE MEMORY - Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently. | 02-23-2012 |
20120297231 | Interface for Storage Device Access Over Memory Bus - A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices. | 11-22-2012 |
20130067200 | MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM - A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer. | 03-14-2013 |
20130073834 | MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM - A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer. | 03-21-2013 |
20130305018 | MFENCE and LFENCE Micro-Architectural Implementation Method and System - A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer. | 11-14-2013 |
20130339572 | MULTI-LEVEL MEMORY WITH DIRECT ACCESS - Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system. | 12-19-2013 |
20130339589 | ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY - Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states. | 12-19-2013 |
20140075107 | INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS - A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices. | 03-13-2014 |
20140095781 | PHASE CHANGE MEMORY IN A DUAL INLINE MEMORY MODULE - Subject matter disclosed herein relates to management of a memory device. | 04-03-2014 |
20140258804 | REDUCED UNCORRECTABLE MEMORY ERRORS - Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively. | 09-11-2014 |
20140317474 | PHASE CHANGE MEMORY WITH SWITCH (PCMS) WRITE ERROR DETECTION - Methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices. Other embodiments are also disclosed and claimed. | 10-23-2014 |
Patent application number | Description | Published |
20080268733 | COATED MULTI-THREAT MATERIALS AND METHODS FOR FABRICATING THE SAME - According to some aspects, a method of manufacturing a coated multi-threat fabric, including providing a first fabric layer having a first surface, the first fabric layer having a plurality of high performance fibers, applying a first polymeric material onto the first surface of the first fabric layer, the polymeric material having a melt flow index of between about 0.7 to 1400 g/10 min, a Shore D hardness of between about 36 and 75, and ultimate tensile strength of between about 5 and 75 MPa, spreading the first polymeric material onto the first surface of the first fabric layer so as to form a raw coated fabric having a first coating layer, and heating the raw coated fabric to bond the first coating layer to the first fabric layer, wherein the first polymeric material is selected such that the coated multi-threat fabric is flexible enough to be stored on a roll of a predetermined size. In some aspects, a coated multi-threat fabric includes at least one layer of fabric, each layer having a plurality of high performance fibers, and at least one coating of polymeric material bonded to the at least one layer of fabric, the polymeric material comprising an ethylene acrylic acid copolymer selected to allow the coated multi-threat fabric to be stored on a roll of a predetermined size. | 10-30-2008 |
20110240168 | WOVEN MULTI-LAYER FABRICS AND METHODS OF FABRICATING SAME - A multi-layer ballistic woven fabric, including an upper woven layer having upper warp yarns and upper weft yarns that are interwoven together to form the upper woven layer. The multi-layer ballistic woven fabric also includes a lower woven layer having lower warp yarns and lower weft yarns that are interwoven together, and a plurality of securing yarns, each securing yarn interwoven with at least some of the upper yarns and some of the lower yarns so as to secure the upper and lower woven layers together. At least one of the securing yarns is woven underneath a first lower weft yarn, then above a second upper weft yarn adjacent the first lower weft yarn, then underneath a third lower weft yarn adjacent the second upper weft yarn and then above a fourth upper weft yarn adjacent the third lower weft yarn. The multi-layer ballistic woven fabric is formed by interweaving the securing yarns with the warp yarns and weft yarns as the upper woven layer and lower woven layer are made. | 10-06-2011 |
20130025736 | WOVEN MULTI-LAYER FABRICS AND METHODS OF FABRICATING SAME - A multi-layer ballistic woven fabric, including an upper woven layer having upper warp yarns and upper weft yarns that are interwoven together to form the upper woven layer. The multi-layer ballistic woven fabric also includes a lower woven layer having lower warp yarns and lower weft yarns that are interwoven together, and a plurality of securing yarns, each securing yarn interwoven with at least some of the upper yarns and some of the lower yarns so as to secure the upper and lower woven layers together. At least one of the securing yarns is woven underneath a first lower weft yarn, then above a second upper weft yarn adjacent the first lower weft yarn, then underneath a third lower weft yarn adjacent the second upper weft yarn and then above a fourth upper weft yarn adjacent the third lower weft yarn. | 01-31-2013 |
20140124085 | WOVEN MULTI-LAYER FABRICS AND METHODS OF FABRICATING SAME - A multi-layer ballistic woven fabric, including an upper woven layer having upper warp yarns and upper weft yarns that are interwoven together to form the upper woven layer. The multi-layer ballistic woven fabric also includes a lower woven layer having lower warp yarns and lower weft yarns that are interwoven together, and a plurality of securing yarns, each securing yarn interwoven with at least some of the upper yarns and some of the lower yarns so as to secure the upper and lower woven layers together. At least one of the securing yarns is woven underneath a first lower weft yarn, then above a second upper weft yarn adjacent the first lower weft yarn, then underneath a third lower weft yarn adjacent the second upper weft yarn and then above a fourth upper weft yarn adjacent the third lower weft yarn. The multi-layer ballistic woven fabric is formed by interweaving the securing yarns with the warp yarns and weft yarns as the upper woven layer and lower woven layer are made. | 05-08-2014 |